/*
 * Copyright (c) 2014, Freescale Semiconductor, Inc.
 * All rights reserved.
 *
 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 */
/*
 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
 *
 * This file was generated automatically and any changes may be lost.
 */
#ifndef __HW_LCD_REGISTERS_H__
#define __HW_LCD_REGISTERS_H__

#include "MKL46Z4.h"
#include "fsl_bitband.h"

/*
 * MKL46Z4 LCD
 *
 * Segment Liquid Crystal Display
 *
 * Registers defined in this header file:
 * - HW_LCD_GCR - LCD General Control Register
 * - HW_LCD_AR - LCD Auxiliary Register
 * - HW_LCD_FDCR - LCD Fault Detect Control Register
 * - HW_LCD_FDSR - LCD Fault Detect Status Register
 * - HW_LCD_PENL - LCD Pin Enable register
 * - HW_LCD_PENH - LCD Pin Enable register
 * - HW_LCD_BPENL - LCD Back Plane Enable register
 * - HW_LCD_BPENH - LCD Back Plane Enable register
 * - HW_LCD_WF3TO0 - LCD Waveform register
 * - HW_LCD_WF7TO4 - LCD Waveform register
 * - HW_LCD_WF11TO8 - LCD Waveform register
 * - HW_LCD_WF15TO12 - LCD Waveform register
 * - HW_LCD_WF19TO16 - LCD Waveform register
 * - HW_LCD_WF23TO20 - LCD Waveform register
 * - HW_LCD_WF27TO24 - LCD Waveform register
 * - HW_LCD_WF31TO28 - LCD Waveform register
 * - HW_LCD_WF35TO32 - LCD Waveform register
 * - HW_LCD_WF39TO36 - LCD Waveform register
 * - HW_LCD_WF43TO40 - LCD Waveform register
 * - HW_LCD_WF47TO44 - LCD Waveform register
 * - HW_LCD_WF51TO48 - LCD Waveform register
 * - HW_LCD_WF55TO52 - LCD Waveform register
 * - HW_LCD_WF59TO56 - LCD Waveform register
 * - HW_LCD_WF63TO60 - LCD Waveform register
 * - HW_LCD_WF0 - LCD Waveform Register 0.
 * - HW_LCD_WF1 - LCD Waveform Register 1.
 * - HW_LCD_WF2 - LCD Waveform Register 2.
 * - HW_LCD_WF3 - LCD Waveform Register 3.
 * - HW_LCD_WF4 - LCD Waveform Register 4.
 * - HW_LCD_WF5 - LCD Waveform Register 5.
 * - HW_LCD_WF6 - LCD Waveform Register 6.
 * - HW_LCD_WF7 - LCD Waveform Register 7.
 * - HW_LCD_WF8 - LCD Waveform Register 8.
 * - HW_LCD_WF9 - LCD Waveform Register 9.
 * - HW_LCD_WF10 - LCD Waveform Register 10.
 * - HW_LCD_WF11 - LCD Waveform Register 11.
 * - HW_LCD_WF12 - LCD Waveform Register 12.
 * - HW_LCD_WF13 - LCD Waveform Register 13.
 * - HW_LCD_WF14 - LCD Waveform Register 14.
 * - HW_LCD_WF15 - LCD Waveform Register 15.
 * - HW_LCD_WF16 - LCD Waveform Register 16.
 * - HW_LCD_WF17 - LCD Waveform Register 17.
 * - HW_LCD_WF18 - LCD Waveform Register 18.
 * - HW_LCD_WF19 - LCD Waveform Register 19.
 * - HW_LCD_WF20 - LCD Waveform Register 20.
 * - HW_LCD_WF21 - LCD Waveform Register 21.
 * - HW_LCD_WF22 - LCD Waveform Register 22.
 * - HW_LCD_WF23 - LCD Waveform Register 23.
 * - HW_LCD_WF24 - LCD Waveform Register 24.
 * - HW_LCD_WF25 - LCD Waveform Register 25.
 * - HW_LCD_WF26 - LCD Waveform Register 26.
 * - HW_LCD_WF27 - LCD Waveform Register 27.
 * - HW_LCD_WF28 - LCD Waveform Register 28.
 * - HW_LCD_WF29 - LCD Waveform Register 29.
 * - HW_LCD_WF30 - LCD Waveform Register 30.
 * - HW_LCD_WF31 - LCD Waveform Register 31.
 * - HW_LCD_WF32 - LCD Waveform Register 32.
 * - HW_LCD_WF33 - LCD Waveform Register 33.
 * - HW_LCD_WF34 - LCD Waveform Register 34.
 * - HW_LCD_WF35 - LCD Waveform Register 35.
 * - HW_LCD_WF36 - LCD Waveform Register 36.
 * - HW_LCD_WF37 - LCD Waveform Register 37.
 * - HW_LCD_WF38 - LCD Waveform Register 38.
 * - HW_LCD_WF39 - LCD Waveform Register 39.
 * - HW_LCD_WF40 - LCD Waveform Register 40.
 * - HW_LCD_WF41 - LCD Waveform Register 41.
 * - HW_LCD_WF42 - LCD Waveform Register 42.
 * - HW_LCD_WF43 - LCD Waveform Register 43.
 * - HW_LCD_WF44 - LCD Waveform Register 44.
 * - HW_LCD_WF45 - LCD Waveform Register 45.
 * - HW_LCD_WF46 - LCD Waveform Register 46.
 * - HW_LCD_WF47 - LCD Waveform Register 47.
 * - HW_LCD_WF48 - LCD Waveform Register 48.
 * - HW_LCD_WF49 - LCD Waveform Register 49.
 * - HW_LCD_WF50 - LCD Waveform Register 50.
 * - HW_LCD_WF51 - LCD Waveform Register 51.
 * - HW_LCD_WF52 - LCD Waveform Register 52.
 * - HW_LCD_WF53 - LCD Waveform Register 53.
 * - HW_LCD_WF54 - LCD Waveform Register 54.
 * - HW_LCD_WF55 - LCD Waveform Register 55.
 * - HW_LCD_WF56 - LCD Waveform Register 56.
 * - HW_LCD_WF57 - LCD Waveform Register 57.
 * - HW_LCD_WF58 - LCD Waveform Register 58.
 * - HW_LCD_WF59 - LCD Waveform Register 59.
 * - HW_LCD_WF60 - LCD Waveform Register 60.
 * - HW_LCD_WF61 - LCD Waveform Register 61.
 * - HW_LCD_WF62 - LCD Waveform Register 62.
 * - HW_LCD_WF63 - LCD Waveform Register 63.
 *
 * - hw_lcd_t - Struct containing all module registers.
 */

#define HW_LCD_INSTANCE_COUNT (1U) /*!< Number of instances of the LCD module. */

/*******************************************************************************
 * HW_LCD_GCR - LCD General Control Register
 ******************************************************************************/

/*!
 * @brief HW_LCD_GCR - LCD General Control Register (RW)
 *
 * Reset value: 0x08310003U
 *
 * Write: LCDEN anytime. Do not change SOURCE, LCLK, or DUTY while LCDEN = 1.
 * For proper operation, do not modify VSUPPLY while the LCDEN bit is asserted.
 * VSUPPLY must also be configured according to the external hardware power supply
 * configuration. The reset value of this register depends on the reset type: POR
 * -- 0x0831_0003
 */
typedef union _hw_lcd_gcr
{
    uint32_t U;
    struct _hw_lcd_gcr_bitfields
    {
        uint32_t DUTY : 3;             /*!< [2:0] LCD duty select */
        uint32_t LCLK : 3;             /*!< [5:3] LCD Clock Prescaler */
        uint32_t SOURCE : 1;           /*!< [6] LCD Clock Source Select */
        uint32_t LCDEN : 1;            /*!< [7] LCD Driver Enable */
        uint32_t LCDSTP : 1;           /*!< [8] LCD Stop */
        uint32_t LCDDOZE : 1;          /*!< [9] LCD Doze enable */
        uint32_t FFR : 1;              /*!< [10] Fast Frame Rate Select */
        uint32_t ALTSOURCE : 1;        /*!< [11] Selects the alternate clock source
                                        * */
        uint32_t ALTDIV : 2;           /*!< [13:12] LCD AlternateClock Divider */
        uint32_t FDCIEN : 1;           /*!< [14] LCD Fault Detection Complete Interrupt
                                        * Enable */
        uint32_t PADSAFE : 1;          /*!< [15] Pad Safe State Enable */
        uint32_t RESERVED0 : 1;        /*!< [16]  */
        uint32_t VSUPPLY : 1;          /*!< [17] Voltage Supply Control */
        uint32_t RESERVED1 : 2;        /*!< [19:18] Reserved */
        uint32_t LADJ : 2;             /*!< [21:20] Load Adjust */
        uint32_t RESERVED2 : 1;        /*!< [22] Reserved */
        uint32_t CPSEL : 1;            /*!< [23] Charge Pump or Resistor Bias Select */
        uint32_t RVTRIM : 4;           /*!< [27:24] Regulated Voltage Trim */
        uint32_t RESERVED3 : 3;        /*!< [30:28] Reserved */
        uint32_t RVEN : 1;             /*!< [31] Regulated Voltage Enable */
    } B;
} hw_lcd_gcr_t;

/*!
 * @name Constants and macros for entire LCD_GCR register
 */
/*@{*/
#define HW_LCD_GCR_ADDR(x)       ((x) + 0x0U)

#define HW_LCD_GCR(x)            (*(__IO hw_lcd_gcr_t *) HW_LCD_GCR_ADDR(x))
#define HW_LCD_GCR_RD(x)         (HW_LCD_GCR(x).U)
#define HW_LCD_GCR_WR(x, v)      (HW_LCD_GCR(x).U = (v))
#define HW_LCD_GCR_SET(x, v)     (BME_OR32(HW_LCD_GCR_ADDR(x), (uint32_t)(v)))
#define HW_LCD_GCR_CLR(x, v)     (BME_AND32(HW_LCD_GCR_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_GCR_TOG(x, v)     (BME_XOR32(HW_LCD_GCR_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_GCR bitfields
 */

/*!
 * @name Register LCD_GCR, field DUTY[2:0] (RW)
 *
 * Selects the duty cycle of the LCD controller driver.
 *
 * Values:
 * - 000 - Use 1 BP (1/1 duty cycle).
 * - 001 - Use 2 BP (1/2 duty cycle).
 * - 010 - Use 3 BP (1/3 duty cycle).
 * - 011 - Use 4 BP (1/4 duty cycle). (Default)
 * - 100 -
 * - 101 -
 * - 110 -
 * - 111 - Use 8 BP (1/8 duty cycle).
 */
/*@{*/
#define BP_LCD_GCR_DUTY      (0U)          /*!< Bit position for LCD_GCR_DUTY. */
#define BM_LCD_GCR_DUTY      (0x00000007U) /*!< Bit mask for LCD_GCR_DUTY. */
#define BS_LCD_GCR_DUTY      (3U)          /*!< Bit field size in bits for LCD_GCR_DUTY. */

/*! @brief Read current value of the LCD_GCR_DUTY field. */
#define BR_LCD_GCR_DUTY(x)   (BME_UBFX32(HW_LCD_GCR_ADDR(x), BP_LCD_GCR_DUTY, BS_LCD_GCR_DUTY))

/*! @brief Format value for bitfield LCD_GCR_DUTY. */
#define BF_LCD_GCR_DUTY(v)   ((uint32_t)((uint32_t)(v) << BP_LCD_GCR_DUTY) & BM_LCD_GCR_DUTY)

/*! @brief Set the DUTY field to a new value. */
#define BW_LCD_GCR_DUTY(x, v) (BME_BFI32(HW_LCD_GCR_ADDR(x), ((uint32_t)(v) << BP_LCD_GCR_DUTY), BP_LCD_GCR_DUTY, 3))
/*@}*/

/*!
 * @name Register LCD_GCR, field LCLK[5:3] (RW)
 *
 * Used as a clock divider to generate the SLCD frame frequency. LCD controller
 * duty cycle configuration is used to determine the LCD controller frame
 * frequency. LCD controller frame frequency calculations are provided in SLCD base
 * clock and frame frequency . LCD controller frame frequency = LCD clock/((DUTY + 1)
 * * 8 * (4 + LCLK[2:0]) * Y) where: 30 < LCD clock < 39.063 kHz Y = 2, 2, 3, 3,
 * 4, 5, 8, 16 chosen by module duty cycle configuration
 */
/*@{*/
#define BP_LCD_GCR_LCLK      (3U)          /*!< Bit position for LCD_GCR_LCLK. */
#define BM_LCD_GCR_LCLK      (0x00000038U) /*!< Bit mask for LCD_GCR_LCLK. */
#define BS_LCD_GCR_LCLK      (3U)          /*!< Bit field size in bits for LCD_GCR_LCLK. */

/*! @brief Read current value of the LCD_GCR_LCLK field. */
#define BR_LCD_GCR_LCLK(x)   (BME_UBFX32(HW_LCD_GCR_ADDR(x), BP_LCD_GCR_LCLK, BS_LCD_GCR_LCLK))

/*! @brief Format value for bitfield LCD_GCR_LCLK. */
#define BF_LCD_GCR_LCLK(v)   ((uint32_t)((uint32_t)(v) << BP_LCD_GCR_LCLK) & BM_LCD_GCR_LCLK)

/*! @brief Set the LCLK field to a new value. */
#define BW_LCD_GCR_LCLK(x, v) (BME_BFI32(HW_LCD_GCR_ADDR(x), ((uint32_t)(v) << BP_LCD_GCR_LCLK), BP_LCD_GCR_LCLK, 3))
/*@}*/

/*!
 * @name Register LCD_GCR, field SOURCE[6] (RW)
 *
 * This bit is used to select which clock source is the basis for LCD clock. The
 * clock sources are chip-specific. For the clock source assignments, see the
 * chapter that describes how modules are configured.
 *
 * Values:
 * - 0 - Selects the default clock as the LCD clock source.
 * - 1 - Selects output of the alternate clock source selection (see ALTSOURCE)
 *     as the LCD clock source.
 */
/*@{*/
#define BP_LCD_GCR_SOURCE    (6U)          /*!< Bit position for LCD_GCR_SOURCE. */
#define BM_LCD_GCR_SOURCE    (0x00000040U) /*!< Bit mask for LCD_GCR_SOURCE. */
#define BS_LCD_GCR_SOURCE    (1U)          /*!< Bit field size in bits for LCD_GCR_SOURCE. */

/*! @brief Read current value of the LCD_GCR_SOURCE field. */
#define BR_LCD_GCR_SOURCE(x) (BME_UBFX32(HW_LCD_GCR_ADDR(x), BP_LCD_GCR_SOURCE, BS_LCD_GCR_SOURCE))

/*! @brief Format value for bitfield LCD_GCR_SOURCE. */
#define BF_LCD_GCR_SOURCE(v) ((uint32_t)((uint32_t)(v) << BP_LCD_GCR_SOURCE) & BM_LCD_GCR_SOURCE)

/*! @brief Set the SOURCE field to a new value. */
#define BW_LCD_GCR_SOURCE(x, v) (BME_BFI32(HW_LCD_GCR_ADDR(x), ((uint32_t)(v) << BP_LCD_GCR_SOURCE), BP_LCD_GCR_SOURCE, 1))
/*@}*/

/*!
 * @name Register LCD_GCR, field LCDEN[7] (RW)
 *
 * Starts LCD controller waveform generator.
 *
 * Values:
 * - 0 - All front plane and back plane pins are disabled. The LCD controller
 *     system is also disabled, and all LCD waveform generation clocks are stopped.
 *     V LL3 is connected to V DD internally. All LCD pins, LCD_Pn, enabled
 *     using the LCD Pin Enable register, output a low value.
 * - 1 - LCD controller driver system is enabled, and front plane and back plane
 *     waveforms are generated. All LCD pins, LCD_Pn, enabled if PAD_SAFE is
 *     clearusing the LCD Pin Enable register, output an LCD driver waveform. The
 *     back plane pins output an LCD driver back plane waveform based on the
 *     settings of DUTY[2:0]. Charge pump or resistor bias is enabled.
 */
/*@{*/
#define BP_LCD_GCR_LCDEN     (7U)          /*!< Bit position for LCD_GCR_LCDEN. */
#define BM_LCD_GCR_LCDEN     (0x00000080U) /*!< Bit mask for LCD_GCR_LCDEN. */
#define BS_LCD_GCR_LCDEN     (1U)          /*!< Bit field size in bits for LCD_GCR_LCDEN. */

/*! @brief Read current value of the LCD_GCR_LCDEN field. */
#define BR_LCD_GCR_LCDEN(x)  (BME_UBFX32(HW_LCD_GCR_ADDR(x), BP_LCD_GCR_LCDEN, BS_LCD_GCR_LCDEN))

/*! @brief Format value for bitfield LCD_GCR_LCDEN. */
#define BF_LCD_GCR_LCDEN(v)  ((uint32_t)((uint32_t)(v) << BP_LCD_GCR_LCDEN) & BM_LCD_GCR_LCDEN)

/*! @brief Set the LCDEN field to a new value. */
#define BW_LCD_GCR_LCDEN(x, v) (BME_BFI32(HW_LCD_GCR_ADDR(x), ((uint32_t)(v) << BP_LCD_GCR_LCDEN), BP_LCD_GCR_LCDEN, 1))
/*@}*/

/*!
 * @name Register LCD_GCR, field LCDSTP[8] (RW)
 *
 * LCD driver, charge pump, resistor bias network, and voltage regulator stop
 * while in Stop mode.
 *
 * Values:
 * - 0 - Allows the LCD driver, charge pump, resistor bias network, and voltage
 *     regulator to continue running during Stop mode.
 * - 1 - Disables the LCD driver, charge pump, resistor bias network, and
 *     voltage regulator when MCU enters Stop mode.
 */
/*@{*/
#define BP_LCD_GCR_LCDSTP    (8U)          /*!< Bit position for LCD_GCR_LCDSTP. */
#define BM_LCD_GCR_LCDSTP    (0x00000100U) /*!< Bit mask for LCD_GCR_LCDSTP. */
#define BS_LCD_GCR_LCDSTP    (1U)          /*!< Bit field size in bits for LCD_GCR_LCDSTP. */

/*! @brief Read current value of the LCD_GCR_LCDSTP field. */
#define BR_LCD_GCR_LCDSTP(x) (BME_UBFX32(HW_LCD_GCR_ADDR(x), BP_LCD_GCR_LCDSTP, BS_LCD_GCR_LCDSTP))

/*! @brief Format value for bitfield LCD_GCR_LCDSTP. */
#define BF_LCD_GCR_LCDSTP(v) ((uint32_t)((uint32_t)(v) << BP_LCD_GCR_LCDSTP) & BM_LCD_GCR_LCDSTP)

/*! @brief Set the LCDSTP field to a new value. */
#define BW_LCD_GCR_LCDSTP(x, v) (BME_BFI32(HW_LCD_GCR_ADDR(x), ((uint32_t)(v) << BP_LCD_GCR_LCDSTP), BP_LCD_GCR_LCDSTP, 1))
/*@}*/

/*!
 * @name Register LCD_GCR, field LCDDOZE[9] (RW)
 *
 * LCD driver, charge pump, resistor bias network, and voltage regulator stop
 * while in Doze mode.
 *
 * Values:
 * - 0 - Allows the LCD driver, charge pump, resistor bias network, and voltage
 *     regulator to continue running during Doze mode.
 * - 1 - Disables the LCD driver, charge pump, resistor bias network, and
 *     voltage regulator when MCU enters Doze mode.
 */
/*@{*/
#define BP_LCD_GCR_LCDDOZE   (9U)          /*!< Bit position for LCD_GCR_LCDDOZE. */
#define BM_LCD_GCR_LCDDOZE   (0x00000200U) /*!< Bit mask for LCD_GCR_LCDDOZE. */
#define BS_LCD_GCR_LCDDOZE   (1U)          /*!< Bit field size in bits for LCD_GCR_LCDDOZE. */

/*! @brief Read current value of the LCD_GCR_LCDDOZE field. */
#define BR_LCD_GCR_LCDDOZE(x) (BME_UBFX32(HW_LCD_GCR_ADDR(x), BP_LCD_GCR_LCDDOZE, BS_LCD_GCR_LCDDOZE))

/*! @brief Format value for bitfield LCD_GCR_LCDDOZE. */
#define BF_LCD_GCR_LCDDOZE(v) ((uint32_t)((uint32_t)(v) << BP_LCD_GCR_LCDDOZE) & BM_LCD_GCR_LCDDOZE)

/*! @brief Set the LCDDOZE field to a new value. */
#define BW_LCD_GCR_LCDDOZE(x, v) (BME_BFI32(HW_LCD_GCR_ADDR(x), ((uint32_t)(v) << BP_LCD_GCR_LCDDOZE), BP_LCD_GCR_LCDDOZE, 1))
/*@}*/

/*!
 * @name Register LCD_GCR, field FFR[10] (RW)
 *
 * Increases the Frame Clock Frequency.
 *
 * Values:
 * - 0 - Standard Frame Rate
 * - 1 - Fast Frame Rate (Standard Frame Rate x2)
 */
/*@{*/
#define BP_LCD_GCR_FFR       (10U)         /*!< Bit position for LCD_GCR_FFR. */
#define BM_LCD_GCR_FFR       (0x00000400U) /*!< Bit mask for LCD_GCR_FFR. */
#define BS_LCD_GCR_FFR       (1U)          /*!< Bit field size in bits for LCD_GCR_FFR. */

/*! @brief Read current value of the LCD_GCR_FFR field. */
#define BR_LCD_GCR_FFR(x)    (BME_UBFX32(HW_LCD_GCR_ADDR(x), BP_LCD_GCR_FFR, BS_LCD_GCR_FFR))

/*! @brief Format value for bitfield LCD_GCR_FFR. */
#define BF_LCD_GCR_FFR(v)    ((uint32_t)((uint32_t)(v) << BP_LCD_GCR_FFR) & BM_LCD_GCR_FFR)

/*! @brief Set the FFR field to a new value. */
#define BW_LCD_GCR_FFR(x, v) (BME_BFI32(HW_LCD_GCR_ADDR(x), ((uint32_t)(v) << BP_LCD_GCR_FFR), BP_LCD_GCR_FFR, 1))
/*@}*/

/*!
 * @name Register LCD_GCR, field ALTSOURCE[11] (RW)
 *
 * Values:
 * - 0 - Select Alternate Clock Source 1 (default)
 * - 1 - Select Alternate Clock Source 2
 */
/*@{*/
#define BP_LCD_GCR_ALTSOURCE (11U)         /*!< Bit position for LCD_GCR_ALTSOURCE. */
#define BM_LCD_GCR_ALTSOURCE (0x00000800U) /*!< Bit mask for LCD_GCR_ALTSOURCE. */
#define BS_LCD_GCR_ALTSOURCE (1U)          /*!< Bit field size in bits for LCD_GCR_ALTSOURCE. */

/*! @brief Read current value of the LCD_GCR_ALTSOURCE field. */
#define BR_LCD_GCR_ALTSOURCE(x) (BME_UBFX32(HW_LCD_GCR_ADDR(x), BP_LCD_GCR_ALTSOURCE, BS_LCD_GCR_ALTSOURCE))

/*! @brief Format value for bitfield LCD_GCR_ALTSOURCE. */
#define BF_LCD_GCR_ALTSOURCE(v) ((uint32_t)((uint32_t)(v) << BP_LCD_GCR_ALTSOURCE) & BM_LCD_GCR_ALTSOURCE)

/*! @brief Set the ALTSOURCE field to a new value. */
#define BW_LCD_GCR_ALTSOURCE(x, v) (BME_BFI32(HW_LCD_GCR_ADDR(x), ((uint32_t)(v) << BP_LCD_GCR_ALTSOURCE), BP_LCD_GCR_ALTSOURCE, 1))
/*@}*/

/*!
 * @name Register LCD_GCR, field ALTDIV[13:12] (RW)
 *
 * Functions as a clock divider to divide the alternate clock before it is
 * selected as LCD clock source.
 *
 * Values:
 * - 0 - Divide factor = 1 (No divide)
 * - 1 - Divide factor = 8
 */
/*@{*/
#define BP_LCD_GCR_ALTDIV    (12U)         /*!< Bit position for LCD_GCR_ALTDIV. */
#define BM_LCD_GCR_ALTDIV    (0x00003000U) /*!< Bit mask for LCD_GCR_ALTDIV. */
#define BS_LCD_GCR_ALTDIV    (2U)          /*!< Bit field size in bits for LCD_GCR_ALTDIV. */

/*! @brief Read current value of the LCD_GCR_ALTDIV field. */
#define BR_LCD_GCR_ALTDIV(x) (BME_UBFX32(HW_LCD_GCR_ADDR(x), BP_LCD_GCR_ALTDIV, BS_LCD_GCR_ALTDIV))

/*! @brief Format value for bitfield LCD_GCR_ALTDIV. */
#define BF_LCD_GCR_ALTDIV(v) ((uint32_t)((uint32_t)(v) << BP_LCD_GCR_ALTDIV) & BM_LCD_GCR_ALTDIV)

/*! @brief Set the ALTDIV field to a new value. */
#define BW_LCD_GCR_ALTDIV(x, v) (BME_BFI32(HW_LCD_GCR_ADDR(x), ((uint32_t)(v) << BP_LCD_GCR_ALTDIV), BP_LCD_GCR_ALTDIV, 2))
/*@}*/

/*!
 * @name Register LCD_GCR, field FDCIEN[14] (RW)
 *
 * Enables an LCD interrupt event when fault detection is completed.
 *
 * Values:
 * - 0 - No interrupt request is generated by this event.
 * - 1 - When a fault is detected and FDCF bit is set, this event causes an
 *     interrupt request.
 */
/*@{*/
#define BP_LCD_GCR_FDCIEN    (14U)         /*!< Bit position for LCD_GCR_FDCIEN. */
#define BM_LCD_GCR_FDCIEN    (0x00004000U) /*!< Bit mask for LCD_GCR_FDCIEN. */
#define BS_LCD_GCR_FDCIEN    (1U)          /*!< Bit field size in bits for LCD_GCR_FDCIEN. */

/*! @brief Read current value of the LCD_GCR_FDCIEN field. */
#define BR_LCD_GCR_FDCIEN(x) (BME_UBFX32(HW_LCD_GCR_ADDR(x), BP_LCD_GCR_FDCIEN, BS_LCD_GCR_FDCIEN))

/*! @brief Format value for bitfield LCD_GCR_FDCIEN. */
#define BF_LCD_GCR_FDCIEN(v) ((uint32_t)((uint32_t)(v) << BP_LCD_GCR_FDCIEN) & BM_LCD_GCR_FDCIEN)

/*! @brief Set the FDCIEN field to a new value. */
#define BW_LCD_GCR_FDCIEN(x, v) (BME_BFI32(HW_LCD_GCR_ADDR(x), ((uint32_t)(v) << BP_LCD_GCR_FDCIEN), BP_LCD_GCR_FDCIEN, 1))
/*@}*/

/*!
 * @name Register LCD_GCR, field PADSAFE[15] (RW)
 *
 * Force safe state on LCD pad controls (all LCD frontplane and backplane
 * functions disabled) regardless of other LCD control bits.
 *
 * Values:
 * - 0 - LCD frontplane and backplane functions enabled according to other LCD
 *     control bits
 * - 1 - LCD frontplane and backplane functions disabled
 */
/*@{*/
#define BP_LCD_GCR_PADSAFE   (15U)         /*!< Bit position for LCD_GCR_PADSAFE. */
#define BM_LCD_GCR_PADSAFE   (0x00008000U) /*!< Bit mask for LCD_GCR_PADSAFE. */
#define BS_LCD_GCR_PADSAFE   (1U)          /*!< Bit field size in bits for LCD_GCR_PADSAFE. */

/*! @brief Read current value of the LCD_GCR_PADSAFE field. */
#define BR_LCD_GCR_PADSAFE(x) (BME_UBFX32(HW_LCD_GCR_ADDR(x), BP_LCD_GCR_PADSAFE, BS_LCD_GCR_PADSAFE))

/*! @brief Format value for bitfield LCD_GCR_PADSAFE. */
#define BF_LCD_GCR_PADSAFE(v) ((uint32_t)((uint32_t)(v) << BP_LCD_GCR_PADSAFE) & BM_LCD_GCR_PADSAFE)

/*! @brief Set the PADSAFE field to a new value. */
#define BW_LCD_GCR_PADSAFE(x, v) (BME_BFI32(HW_LCD_GCR_ADDR(x), ((uint32_t)(v) << BP_LCD_GCR_PADSAFE), BP_LCD_GCR_PADSAFE, 1))
/*@}*/

/*!
 * @name Register LCD_GCR, field VSUPPLY[17] (RW)
 *
 * Configures whether the LCD controller power supply is external or internal.
 * Avoid modifying this field while the LCD controller is enabled, for example, if
 * LCDEN = 1.
 *
 * Values:
 * - 0 - Drive VLL3internally from VDD
 * - 1 - Drive VLL3externally from VDD or drive VLL internally from vIREG
 */
/*@{*/
#define BP_LCD_GCR_VSUPPLY   (17U)         /*!< Bit position for LCD_GCR_VSUPPLY. */
#define BM_LCD_GCR_VSUPPLY   (0x00020000U) /*!< Bit mask for LCD_GCR_VSUPPLY. */
#define BS_LCD_GCR_VSUPPLY   (1U)          /*!< Bit field size in bits for LCD_GCR_VSUPPLY. */

/*! @brief Read current value of the LCD_GCR_VSUPPLY field. */
#define BR_LCD_GCR_VSUPPLY(x) (BME_UBFX32(HW_LCD_GCR_ADDR(x), BP_LCD_GCR_VSUPPLY, BS_LCD_GCR_VSUPPLY))

/*! @brief Format value for bitfield LCD_GCR_VSUPPLY. */
#define BF_LCD_GCR_VSUPPLY(v) ((uint32_t)((uint32_t)(v) << BP_LCD_GCR_VSUPPLY) & BM_LCD_GCR_VSUPPLY)

/*! @brief Set the VSUPPLY field to a new value. */
#define BW_LCD_GCR_VSUPPLY(x, v) (BME_BFI32(HW_LCD_GCR_ADDR(x), ((uint32_t)(v) << BP_LCD_GCR_VSUPPLY), BP_LCD_GCR_VSUPPLY, 1))
/*@}*/

/*!
 * @name Register LCD_GCR, field LADJ[21:20] (RW)
 *
 * Configures SLCD to handle different LCD glass capacitance. For CPSEL = 0
 * Adjust the resistor bias network for different LCD glass capacitance. 00 - Low
 * Load (LCD glass capacitance 2000 pF or lower). LCD or GPIO functions can be used
 * on V LL1 , V LL2 , V CAP1 and V CAP2 pins. 01 - Low Load (LCD glass
 * capacitance 2000 pF or lower). LCD or GPIO functions can be used on V LL1 , V LL2 , V
 * CAP1 and V CAP2 pins. 10 - High Load (LCD glass capacitance 8000 pF or lower)
 * LCD or GPIO functions can be used on V CAP1 and V CAP2 pins. . 11 - High Load
 * (LCD glass capacitance 8000 pF or lower). LCD or GPIO functions can be used on V
 * CAP1 and V CAP2 pins. For CPSEL = 1 Adjust the clock source for the charge
 * pump. Higher loads require higher charge pump clock rates. 00 - Fastest clock
 * source for charge pump (LCD glass capacitance 8000 pF or 4000pF or lower if FFR
 * is set ). 01 - Intermediate clock source for charge pump (LCD glass
 * capacitance 4000 pF or 2000pF or lower if FFR is set ). 10 - Intermediate clock source
 * for charge pump (LCD glass capacitance 2000 pF or 1000pF or lower if FFR is set
 * ). 11 - Slowest clock source for charge pump (LCD glass capacitance 1000 pF
 * or 500pF or lower if FFR is set ).
 */
/*@{*/
#define BP_LCD_GCR_LADJ      (20U)         /*!< Bit position for LCD_GCR_LADJ. */
#define BM_LCD_GCR_LADJ      (0x00300000U) /*!< Bit mask for LCD_GCR_LADJ. */
#define BS_LCD_GCR_LADJ      (2U)          /*!< Bit field size in bits for LCD_GCR_LADJ. */

/*! @brief Read current value of the LCD_GCR_LADJ field. */
#define BR_LCD_GCR_LADJ(x)   (BME_UBFX32(HW_LCD_GCR_ADDR(x), BP_LCD_GCR_LADJ, BS_LCD_GCR_LADJ))

/*! @brief Format value for bitfield LCD_GCR_LADJ. */
#define BF_LCD_GCR_LADJ(v)   ((uint32_t)((uint32_t)(v) << BP_LCD_GCR_LADJ) & BM_LCD_GCR_LADJ)

/*! @brief Set the LADJ field to a new value. */
#define BW_LCD_GCR_LADJ(x, v) (BME_BFI32(HW_LCD_GCR_ADDR(x), ((uint32_t)(v) << BP_LCD_GCR_LADJ), BP_LCD_GCR_LADJ, 2))
/*@}*/

/*!
 * @name Register LCD_GCR, field CPSEL[23] (RW)
 *
 * Selects the LCD controller charge pump or a resistor network to supply the
 * LCD voltages V LL1 , V LL2 , and V LL3 .
 *
 * Values:
 * - 0 - LCD charge pump is disabled. Resistor network selected. (The internal
 *     1/3-bias is forced.)
 * - 1 - LCD charge pump is selected. Resistor network disabled. (The internal
 *     1/3-bias is forced.)
 */
/*@{*/
#define BP_LCD_GCR_CPSEL     (23U)         /*!< Bit position for LCD_GCR_CPSEL. */
#define BM_LCD_GCR_CPSEL     (0x00800000U) /*!< Bit mask for LCD_GCR_CPSEL. */
#define BS_LCD_GCR_CPSEL     (1U)          /*!< Bit field size in bits for LCD_GCR_CPSEL. */

/*! @brief Read current value of the LCD_GCR_CPSEL field. */
#define BR_LCD_GCR_CPSEL(x)  (BME_UBFX32(HW_LCD_GCR_ADDR(x), BP_LCD_GCR_CPSEL, BS_LCD_GCR_CPSEL))

/*! @brief Format value for bitfield LCD_GCR_CPSEL. */
#define BF_LCD_GCR_CPSEL(v)  ((uint32_t)((uint32_t)(v) << BP_LCD_GCR_CPSEL) & BM_LCD_GCR_CPSEL)

/*! @brief Set the CPSEL field to a new value. */
#define BW_LCD_GCR_CPSEL(x, v) (BME_BFI32(HW_LCD_GCR_ADDR(x), ((uint32_t)(v) << BP_LCD_GCR_CPSEL), BP_LCD_GCR_CPSEL, 1))
/*@}*/

/*!
 * @name Register LCD_GCR, field RVTRIM[27:24] (RW)
 *
 * This 4-bit trim register is used to adjust the regulated input. Each bit in
 * the register has equal weight. The regulated input is changed by 1.5% for each
 * count.
 */
/*@{*/
#define BP_LCD_GCR_RVTRIM    (24U)         /*!< Bit position for LCD_GCR_RVTRIM. */
#define BM_LCD_GCR_RVTRIM    (0x0F000000U) /*!< Bit mask for LCD_GCR_RVTRIM. */
#define BS_LCD_GCR_RVTRIM    (4U)          /*!< Bit field size in bits for LCD_GCR_RVTRIM. */

/*! @brief Read current value of the LCD_GCR_RVTRIM field. */
#define BR_LCD_GCR_RVTRIM(x) (BME_UBFX32(HW_LCD_GCR_ADDR(x), BP_LCD_GCR_RVTRIM, BS_LCD_GCR_RVTRIM))

/*! @brief Format value for bitfield LCD_GCR_RVTRIM. */
#define BF_LCD_GCR_RVTRIM(v) ((uint32_t)((uint32_t)(v) << BP_LCD_GCR_RVTRIM) & BM_LCD_GCR_RVTRIM)

/*! @brief Set the RVTRIM field to a new value. */
#define BW_LCD_GCR_RVTRIM(x, v) (BME_BFI32(HW_LCD_GCR_ADDR(x), ((uint32_t)(v) << BP_LCD_GCR_RVTRIM), BP_LCD_GCR_RVTRIM, 4))
/*@}*/

/*!
 * @name Register LCD_GCR, field RVEN[31] (RW)
 *
 * Enables internal voltage regulator. It must have the charge pump enabled.
 *
 * Values:
 * - 0 - Regulated voltage disabled.
 * - 1 - Regulated voltage enabled.
 */
/*@{*/
#define BP_LCD_GCR_RVEN      (31U)         /*!< Bit position for LCD_GCR_RVEN. */
#define BM_LCD_GCR_RVEN      (0x80000000U) /*!< Bit mask for LCD_GCR_RVEN. */
#define BS_LCD_GCR_RVEN      (1U)          /*!< Bit field size in bits for LCD_GCR_RVEN. */

/*! @brief Read current value of the LCD_GCR_RVEN field. */
#define BR_LCD_GCR_RVEN(x)   (BME_UBFX32(HW_LCD_GCR_ADDR(x), BP_LCD_GCR_RVEN, BS_LCD_GCR_RVEN))

/*! @brief Format value for bitfield LCD_GCR_RVEN. */
#define BF_LCD_GCR_RVEN(v)   ((uint32_t)((uint32_t)(v) << BP_LCD_GCR_RVEN) & BM_LCD_GCR_RVEN)

/*! @brief Set the RVEN field to a new value. */
#define BW_LCD_GCR_RVEN(x, v) (BME_BFI32(HW_LCD_GCR_ADDR(x), ((uint32_t)(v) << BP_LCD_GCR_RVEN), BP_LCD_GCR_RVEN, 1))
/*@}*/

/*******************************************************************************
 * HW_LCD_AR - LCD Auxiliary Register
 ******************************************************************************/

/*!
 * @brief HW_LCD_AR - LCD Auxiliary Register (RW)
 *
 * Reset value: 0x00000000U
 *
 * The reset value of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_ar
{
    uint32_t U;
    struct _hw_lcd_ar_bitfields
    {
        uint32_t BRATE : 3;            /*!< [2:0] Blink-rate configuration */
        uint32_t BMODE : 1;            /*!< [3] Blink mode */
        uint32_t RESERVED0 : 1;        /*!< [4] Reserved */
        uint32_t BLANK : 1;            /*!< [5] Blank display mode */
        uint32_t ALT : 1;              /*!< [6] Alternate display mode */
        uint32_t BLINK : 1;            /*!< [7] Blink command */
        uint32_t RESERVED1 : 24;       /*!< [31:8] Reserved */
    } B;
} hw_lcd_ar_t;

/*!
 * @name Constants and macros for entire LCD_AR register
 */
/*@{*/
#define HW_LCD_AR_ADDR(x)        ((x) + 0x4U)

#define HW_LCD_AR(x)             (*(__IO hw_lcd_ar_t *) HW_LCD_AR_ADDR(x))
#define HW_LCD_AR_RD(x)          (HW_LCD_AR(x).U)
#define HW_LCD_AR_WR(x, v)       (HW_LCD_AR(x).U = (v))
#define HW_LCD_AR_SET(x, v)      (BME_OR32(HW_LCD_AR_ADDR(x), (uint32_t)(v)))
#define HW_LCD_AR_CLR(x, v)      (BME_AND32(HW_LCD_AR_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_AR_TOG(x, v)      (BME_XOR32(HW_LCD_AR_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_AR bitfields
 */

/*!
 * @name Register LCD_AR, field BRATE[2:0] (RW)
 *
 * Selects frequency at which the LCD blinks when the BLINK bit is asserted. The
 * following equation provides an expression for the LCD controller blink rate
 * and shows how BRATE field is used in the LCD blink-rate calculation. LCD
 * controller blink rate = LCD clock /2(12 + BRATE)
 */
/*@{*/
#define BP_LCD_AR_BRATE      (0U)          /*!< Bit position for LCD_AR_BRATE. */
#define BM_LCD_AR_BRATE      (0x00000007U) /*!< Bit mask for LCD_AR_BRATE. */
#define BS_LCD_AR_BRATE      (3U)          /*!< Bit field size in bits for LCD_AR_BRATE. */

/*! @brief Read current value of the LCD_AR_BRATE field. */
#define BR_LCD_AR_BRATE(x)   (BME_UBFX32(HW_LCD_AR_ADDR(x), BP_LCD_AR_BRATE, BS_LCD_AR_BRATE))

/*! @brief Format value for bitfield LCD_AR_BRATE. */
#define BF_LCD_AR_BRATE(v)   ((uint32_t)((uint32_t)(v) << BP_LCD_AR_BRATE) & BM_LCD_AR_BRATE)

/*! @brief Set the BRATE field to a new value. */
#define BW_LCD_AR_BRATE(x, v) (BME_BFI32(HW_LCD_AR_ADDR(x), ((uint32_t)(v) << BP_LCD_AR_BRATE), BP_LCD_AR_BRATE, 3))
/*@}*/

/*!
 * @name Register LCD_AR, field BMODE[3] (RW)
 *
 * Selects the blink mode displayed during the blink period.
 *
 * Values:
 * - 0 - Display blank during the blink period.
 * - 1 - Display alternate display during blink period (Ignored if duty is 5 or
 *     greater).
 */
/*@{*/
#define BP_LCD_AR_BMODE      (3U)          /*!< Bit position for LCD_AR_BMODE. */
#define BM_LCD_AR_BMODE      (0x00000008U) /*!< Bit mask for LCD_AR_BMODE. */
#define BS_LCD_AR_BMODE      (1U)          /*!< Bit field size in bits for LCD_AR_BMODE. */

/*! @brief Read current value of the LCD_AR_BMODE field. */
#define BR_LCD_AR_BMODE(x)   (BME_UBFX32(HW_LCD_AR_ADDR(x), BP_LCD_AR_BMODE, BS_LCD_AR_BMODE))

/*! @brief Format value for bitfield LCD_AR_BMODE. */
#define BF_LCD_AR_BMODE(v)   ((uint32_t)((uint32_t)(v) << BP_LCD_AR_BMODE) & BM_LCD_AR_BMODE)

/*! @brief Set the BMODE field to a new value. */
#define BW_LCD_AR_BMODE(x, v) (BME_BFI32(HW_LCD_AR_ADDR(x), ((uint32_t)(v) << BP_LCD_AR_BMODE), BP_LCD_AR_BMODE, 1))
/*@}*/

/*!
 * @name Register LCD_AR, field BLANK[5] (RW)
 *
 * Asserting this bit clears all segments in the LCD.
 *
 * Values:
 * - 0 - Normal or alternate display mode.
 * - 1 - Blank display mode.
 */
/*@{*/
#define BP_LCD_AR_BLANK      (5U)          /*!< Bit position for LCD_AR_BLANK. */
#define BM_LCD_AR_BLANK      (0x00000020U) /*!< Bit mask for LCD_AR_BLANK. */
#define BS_LCD_AR_BLANK      (1U)          /*!< Bit field size in bits for LCD_AR_BLANK. */

/*! @brief Read current value of the LCD_AR_BLANK field. */
#define BR_LCD_AR_BLANK(x)   (BME_UBFX32(HW_LCD_AR_ADDR(x), BP_LCD_AR_BLANK, BS_LCD_AR_BLANK))

/*! @brief Format value for bitfield LCD_AR_BLANK. */
#define BF_LCD_AR_BLANK(v)   ((uint32_t)((uint32_t)(v) << BP_LCD_AR_BLANK) & BM_LCD_AR_BLANK)

/*! @brief Set the BLANK field to a new value. */
#define BW_LCD_AR_BLANK(x, v) (BME_BFI32(HW_LCD_AR_ADDR(x), ((uint32_t)(v) << BP_LCD_AR_BLANK), BP_LCD_AR_BLANK, 1))
/*@}*/

/*!
 * @name Register LCD_AR, field ALT[6] (RW)
 *
 * For four back planes or less, the LCD back plane sequencer changes to output
 * an alternate display. ALT bit is ignored if DUTY[2:0] is 100 or greater.
 *
 * Values:
 * - 0 - Normal display mode.
 * - 1 - Alternate display mode.
 */
/*@{*/
#define BP_LCD_AR_ALT        (6U)          /*!< Bit position for LCD_AR_ALT. */
#define BM_LCD_AR_ALT        (0x00000040U) /*!< Bit mask for LCD_AR_ALT. */
#define BS_LCD_AR_ALT        (1U)          /*!< Bit field size in bits for LCD_AR_ALT. */

/*! @brief Read current value of the LCD_AR_ALT field. */
#define BR_LCD_AR_ALT(x)     (BME_UBFX32(HW_LCD_AR_ADDR(x), BP_LCD_AR_ALT, BS_LCD_AR_ALT))

/*! @brief Format value for bitfield LCD_AR_ALT. */
#define BF_LCD_AR_ALT(v)     ((uint32_t)((uint32_t)(v) << BP_LCD_AR_ALT) & BM_LCD_AR_ALT)

/*! @brief Set the ALT field to a new value. */
#define BW_LCD_AR_ALT(x, v)  (BME_BFI32(HW_LCD_AR_ADDR(x), ((uint32_t)(v) << BP_LCD_AR_ALT), BP_LCD_AR_ALT, 1))
/*@}*/

/*!
 * @name Register LCD_AR, field BLINK[7] (RW)
 *
 * Starts or stops SLCD blinking.
 *
 * Values:
 * - 0 - Disables blinking.
 * - 1 - Starts blinking at blinking frequency specified by LCD blink rate
 *     calculation.
 */
/*@{*/
#define BP_LCD_AR_BLINK      (7U)          /*!< Bit position for LCD_AR_BLINK. */
#define BM_LCD_AR_BLINK      (0x00000080U) /*!< Bit mask for LCD_AR_BLINK. */
#define BS_LCD_AR_BLINK      (1U)          /*!< Bit field size in bits for LCD_AR_BLINK. */

/*! @brief Read current value of the LCD_AR_BLINK field. */
#define BR_LCD_AR_BLINK(x)   (BME_UBFX32(HW_LCD_AR_ADDR(x), BP_LCD_AR_BLINK, BS_LCD_AR_BLINK))

/*! @brief Format value for bitfield LCD_AR_BLINK. */
#define BF_LCD_AR_BLINK(v)   ((uint32_t)((uint32_t)(v) << BP_LCD_AR_BLINK) & BM_LCD_AR_BLINK)

/*! @brief Set the BLINK field to a new value. */
#define BW_LCD_AR_BLINK(x, v) (BME_BFI32(HW_LCD_AR_ADDR(x), ((uint32_t)(v) << BP_LCD_AR_BLINK), BP_LCD_AR_BLINK, 1))
/*@}*/

/*******************************************************************************
 * HW_LCD_FDCR - LCD Fault Detect Control Register
 ******************************************************************************/

/*!
 * @brief HW_LCD_FDCR - LCD Fault Detect Control Register (RW)
 *
 * Reset value: 0x00000000U
 *
 * The reset value of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_fdcr
{
    uint32_t U;
    struct _hw_lcd_fdcr_bitfields
    {
        uint32_t FDPINID : 6;          /*!< [5:0] Fault Detect Pin ID */
        uint32_t FDBPEN : 1;           /*!< [6] Fault Detect Back Plane Enable */
        uint32_t FDEN : 1;             /*!< [7] Fault Detect Enable */
        uint32_t RESERVED0 : 1;        /*!< [8] Reserved */
        uint32_t FDSWW : 3;            /*!< [11:9] Fault Detect Sample Window Width */
        uint32_t FDPRS : 3;            /*!< [14:12] Fault Detect Clock Prescaler */
        uint32_t RESERVED1 : 17;       /*!< [31:15] Reserved */
    } B;
} hw_lcd_fdcr_t;

/*!
 * @name Constants and macros for entire LCD_FDCR register
 */
/*@{*/
#define HW_LCD_FDCR_ADDR(x)      ((x) + 0x8U)

#define HW_LCD_FDCR(x)           (*(__IO hw_lcd_fdcr_t *) HW_LCD_FDCR_ADDR(x))
#define HW_LCD_FDCR_RD(x)        (HW_LCD_FDCR(x).U)
#define HW_LCD_FDCR_WR(x, v)     (HW_LCD_FDCR(x).U = (v))
#define HW_LCD_FDCR_SET(x, v)    (BME_OR32(HW_LCD_FDCR_ADDR(x), (uint32_t)(v)))
#define HW_LCD_FDCR_CLR(x, v)    (BME_AND32(HW_LCD_FDCR_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_FDCR_TOG(x, v)    (BME_XOR32(HW_LCD_FDCR_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_FDCR bitfields
 */

/*!
 * @name Register LCD_FDCR, field FDPINID[5:0] (RW)
 *
 * Specifies the LCD pin to be checked by pullup fault detection.
 *
 * Values:
 * - 0 - Fault detection for LCD_P0 pin.
 * - 1 - Fault detection for LCD_P1 pin.
 */
/*@{*/
#define BP_LCD_FDCR_FDPINID  (0U)          /*!< Bit position for LCD_FDCR_FDPINID. */
#define BM_LCD_FDCR_FDPINID  (0x0000003FU) /*!< Bit mask for LCD_FDCR_FDPINID. */
#define BS_LCD_FDCR_FDPINID  (6U)          /*!< Bit field size in bits for LCD_FDCR_FDPINID. */

/*! @brief Read current value of the LCD_FDCR_FDPINID field. */
#define BR_LCD_FDCR_FDPINID(x) (BME_UBFX32(HW_LCD_FDCR_ADDR(x), BP_LCD_FDCR_FDPINID, BS_LCD_FDCR_FDPINID))

/*! @brief Format value for bitfield LCD_FDCR_FDPINID. */
#define BF_LCD_FDCR_FDPINID(v) ((uint32_t)((uint32_t)(v) << BP_LCD_FDCR_FDPINID) & BM_LCD_FDCR_FDPINID)

/*! @brief Set the FDPINID field to a new value. */
#define BW_LCD_FDCR_FDPINID(x, v) (BME_BFI32(HW_LCD_FDCR_ADDR(x), ((uint32_t)(v) << BP_LCD_FDCR_FDPINID), BP_LCD_FDCR_FDPINID, 6))
/*@}*/

/*!
 * @name Register LCD_FDCR, field FDBPEN[6] (RW)
 *
 * Enables "back plane" timing for the fault detect circuit. FDBPEN = 0
 * generates front plane timing. This bit specifies the type of pin selected under fault
 * detect test.
 *
 * Values:
 * - 0 - Type of the selected pin under fault detect test is front plane.
 * - 1 - Type of the selected pin under fault detect test is back plane.
 */
/*@{*/
#define BP_LCD_FDCR_FDBPEN   (6U)          /*!< Bit position for LCD_FDCR_FDBPEN. */
#define BM_LCD_FDCR_FDBPEN   (0x00000040U) /*!< Bit mask for LCD_FDCR_FDBPEN. */
#define BS_LCD_FDCR_FDBPEN   (1U)          /*!< Bit field size in bits for LCD_FDCR_FDBPEN. */

/*! @brief Read current value of the LCD_FDCR_FDBPEN field. */
#define BR_LCD_FDCR_FDBPEN(x) (BME_UBFX32(HW_LCD_FDCR_ADDR(x), BP_LCD_FDCR_FDBPEN, BS_LCD_FDCR_FDBPEN))

/*! @brief Format value for bitfield LCD_FDCR_FDBPEN. */
#define BF_LCD_FDCR_FDBPEN(v) ((uint32_t)((uint32_t)(v) << BP_LCD_FDCR_FDBPEN) & BM_LCD_FDCR_FDBPEN)

/*! @brief Set the FDBPEN field to a new value. */
#define BW_LCD_FDCR_FDBPEN(x, v) (BME_BFI32(HW_LCD_FDCR_ADDR(x), ((uint32_t)(v) << BP_LCD_FDCR_FDBPEN), BP_LCD_FDCR_FDBPEN, 1))
/*@}*/

/*!
 * @name Register LCD_FDCR, field FDEN[7] (RW)
 *
 * If LCDEN is 1, asserting FDEN inserts a test frame after normal LCD refresh
 * frame is completed. After the test frame is done, Fault detection complete flag
 * (FDCF) is set. When the test frame is done, a normal LCD refresh frame
 * starts. FDEN is one-shot register, it clears after FDCF is set. To initiate another
 * fault detection, FDEN must be set again.
 *
 * Values:
 * - 0 - Disable fault detection.
 * - 1 - Enable fault detection.
 */
/*@{*/
#define BP_LCD_FDCR_FDEN     (7U)          /*!< Bit position for LCD_FDCR_FDEN. */
#define BM_LCD_FDCR_FDEN     (0x00000080U) /*!< Bit mask for LCD_FDCR_FDEN. */
#define BS_LCD_FDCR_FDEN     (1U)          /*!< Bit field size in bits for LCD_FDCR_FDEN. */

/*! @brief Read current value of the LCD_FDCR_FDEN field. */
#define BR_LCD_FDCR_FDEN(x)  (BME_UBFX32(HW_LCD_FDCR_ADDR(x), BP_LCD_FDCR_FDEN, BS_LCD_FDCR_FDEN))

/*! @brief Format value for bitfield LCD_FDCR_FDEN. */
#define BF_LCD_FDCR_FDEN(v)  ((uint32_t)((uint32_t)(v) << BP_LCD_FDCR_FDEN) & BM_LCD_FDCR_FDEN)

/*! @brief Set the FDEN field to a new value. */
#define BW_LCD_FDCR_FDEN(x, v) (BME_BFI32(HW_LCD_FDCR_ADDR(x), ((uint32_t)(v) << BP_LCD_FDCR_FDEN), BP_LCD_FDCR_FDEN, 1))
/*@}*/

/*!
 * @name Register LCD_FDCR, field FDSWW[11:9] (RW)
 *
 * Specifies the sample window width of fault detection, in number of cycles in
 * the range from 4-512 (Sample window = 4*2 N ).
 *
 * Values:
 * - 0 - Sample window width is 4 sample clock cycles.
 * - 1 - Sample window width is 8 sample clock cycles.
 */
/*@{*/
#define BP_LCD_FDCR_FDSWW    (9U)          /*!< Bit position for LCD_FDCR_FDSWW. */
#define BM_LCD_FDCR_FDSWW    (0x00000E00U) /*!< Bit mask for LCD_FDCR_FDSWW. */
#define BS_LCD_FDCR_FDSWW    (3U)          /*!< Bit field size in bits for LCD_FDCR_FDSWW. */

/*! @brief Read current value of the LCD_FDCR_FDSWW field. */
#define BR_LCD_FDCR_FDSWW(x) (BME_UBFX32(HW_LCD_FDCR_ADDR(x), BP_LCD_FDCR_FDSWW, BS_LCD_FDCR_FDSWW))

/*! @brief Format value for bitfield LCD_FDCR_FDSWW. */
#define BF_LCD_FDCR_FDSWW(v) ((uint32_t)((uint32_t)(v) << BP_LCD_FDCR_FDSWW) & BM_LCD_FDCR_FDSWW)

/*! @brief Set the FDSWW field to a new value. */
#define BW_LCD_FDCR_FDSWW(x, v) (BME_BFI32(HW_LCD_FDCR_ADDR(x), ((uint32_t)(v) << BP_LCD_FDCR_FDSWW), BP_LCD_FDCR_FDSWW, 3))
/*@}*/

/*!
 * @name Register LCD_FDCR, field FDPRS[14:12] (RW)
 *
 * Fault detect sample clock frequency is:
 *
 * Values:
 * - 0 - 1/1 bus clock.
 * - 1 - 1/2 bus clock.
 */
/*@{*/
#define BP_LCD_FDCR_FDPRS    (12U)         /*!< Bit position for LCD_FDCR_FDPRS. */
#define BM_LCD_FDCR_FDPRS    (0x00007000U) /*!< Bit mask for LCD_FDCR_FDPRS. */
#define BS_LCD_FDCR_FDPRS    (3U)          /*!< Bit field size in bits for LCD_FDCR_FDPRS. */

/*! @brief Read current value of the LCD_FDCR_FDPRS field. */
#define BR_LCD_FDCR_FDPRS(x) (BME_UBFX32(HW_LCD_FDCR_ADDR(x), BP_LCD_FDCR_FDPRS, BS_LCD_FDCR_FDPRS))

/*! @brief Format value for bitfield LCD_FDCR_FDPRS. */
#define BF_LCD_FDCR_FDPRS(v) ((uint32_t)((uint32_t)(v) << BP_LCD_FDCR_FDPRS) & BM_LCD_FDCR_FDPRS)

/*! @brief Set the FDPRS field to a new value. */
#define BW_LCD_FDCR_FDPRS(x, v) (BME_BFI32(HW_LCD_FDCR_ADDR(x), ((uint32_t)(v) << BP_LCD_FDCR_FDPRS), BP_LCD_FDCR_FDPRS, 3))
/*@}*/

/*******************************************************************************
 * HW_LCD_FDSR - LCD Fault Detect Status Register
 ******************************************************************************/

/*!
 * @brief HW_LCD_FDSR - LCD Fault Detect Status Register (RW)
 *
 * Reset value: 0x00000000U
 *
 * The reset value of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_fdsr
{
    uint32_t U;
    struct _hw_lcd_fdsr_bitfields
    {
        uint32_t FDCNT : 8;            /*!< [7:0] Fault Detect Counter */
        uint32_t RESERVED0 : 7;        /*!< [14:8] Reserved */
        uint32_t FDCF : 1;             /*!< [15] Fault Detection Complete Flag */
        uint32_t RESERVED1 : 16;       /*!< [31:16] Reserved */
    } B;
} hw_lcd_fdsr_t;

/*!
 * @name Constants and macros for entire LCD_FDSR register
 */
/*@{*/
#define HW_LCD_FDSR_ADDR(x)      ((x) + 0xCU)

#define HW_LCD_FDSR(x)           (*(__IO hw_lcd_fdsr_t *) HW_LCD_FDSR_ADDR(x))
#define HW_LCD_FDSR_RD(x)        (HW_LCD_FDSR(x).U)
#define HW_LCD_FDSR_WR(x, v)     (HW_LCD_FDSR(x).U = (v))
#define HW_LCD_FDSR_SET(x, v)    (BME_OR32(HW_LCD_FDSR_ADDR(x), (uint32_t)(v)))
#define HW_LCD_FDSR_CLR(x, v)    (BME_AND32(HW_LCD_FDSR_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_FDSR_TOG(x, v)    (BME_XOR32(HW_LCD_FDSR_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_FDSR bitfields
 */

/*!
 * @name Register LCD_FDSR, field FDCNT[7:0] (RO)
 *
 * Contains how many "one/high" are sampled inside the fault detect sample
 * window.
 *
 * Values:
 * - 0 - No "one" samples.
 * - 1 - 1 "one" samples.
 */
/*@{*/
#define BP_LCD_FDSR_FDCNT    (0U)          /*!< Bit position for LCD_FDSR_FDCNT. */
#define BM_LCD_FDSR_FDCNT    (0x000000FFU) /*!< Bit mask for LCD_FDSR_FDCNT. */
#define BS_LCD_FDSR_FDCNT    (8U)          /*!< Bit field size in bits for LCD_FDSR_FDCNT. */

/*! @brief Read current value of the LCD_FDSR_FDCNT field. */
#define BR_LCD_FDSR_FDCNT(x) (BME_UBFX32(HW_LCD_FDSR_ADDR(x), BP_LCD_FDSR_FDCNT, BS_LCD_FDSR_FDCNT))
/*@}*/

/*!
 * @name Register LCD_FDSR, field FDCF[15] (W1C)
 *
 * FDCF indicates that the fault detection is completed. Writing 1 to this bit
 * clears it to zero. This bit also acts as an interrupt flag when FDCIEN is set.
 * Software can use either interrupt or polling to check whether one pin fault
 * detection is completed.
 *
 * Values:
 * - 0 - Fault detection is not completed.
 * - 1 - Fault detection is completed.
 */
/*@{*/
#define BP_LCD_FDSR_FDCF     (15U)         /*!< Bit position for LCD_FDSR_FDCF. */
#define BM_LCD_FDSR_FDCF     (0x00008000U) /*!< Bit mask for LCD_FDSR_FDCF. */
#define BS_LCD_FDSR_FDCF     (1U)          /*!< Bit field size in bits for LCD_FDSR_FDCF. */

/*! @brief Read current value of the LCD_FDSR_FDCF field. */
#define BR_LCD_FDSR_FDCF(x)  (BME_UBFX32(HW_LCD_FDSR_ADDR(x), BP_LCD_FDSR_FDCF, BS_LCD_FDSR_FDCF))

/*! @brief Format value for bitfield LCD_FDSR_FDCF. */
#define BF_LCD_FDSR_FDCF(v)  ((uint32_t)((uint32_t)(v) << BP_LCD_FDSR_FDCF) & BM_LCD_FDSR_FDCF)

/*! @brief Set the FDCF field to a new value. */
#define BW_LCD_FDSR_FDCF(x, v) (BME_BFI32(HW_LCD_FDSR_ADDR(x), ((uint32_t)(v) << BP_LCD_FDSR_FDCF), BP_LCD_FDSR_FDCF, 1))
/*@}*/

/*******************************************************************************
 * HW_LCD_PENL - LCD Pin Enable register
 ******************************************************************************/

/*!
 * @brief HW_LCD_PENL - LCD Pin Enable register (RW)
 *
 * Reset value: 0x00000000U
 *
 * When LCDEN = 1,and PAD_SAFE=0 each PEN bit enables the corresponding LCD pin
 * (LCD_Pn) for LCD waveform generation.When LCDEN=0, each PEN bit enabled to
 * corresponding LCD pin (LCD_Pn) to drive a low output. Initialize these registers
 * before enabling the LCD controller. The reset value of this register depends
 * on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_penl
{
    uint32_t U;
    struct _hw_lcd_penl_bitfields
    {
        uint32_t PEN : 32;             /*!< [31:0] LCD Pin Enable */
    } B;
} hw_lcd_penl_t;

/*!
 * @name Constants and macros for entire LCD_PENL register
 */
/*@{*/
#define HW_LCD_PENL_ADDR(x)      ((x) + 0x10U)

#define HW_LCD_PENL(x)           (*(__IO hw_lcd_penl_t *) HW_LCD_PENL_ADDR(x))
#define HW_LCD_PENL_RD(x)        (HW_LCD_PENL(x).U)
#define HW_LCD_PENL_WR(x, v)     (HW_LCD_PENL(x).U = (v))
#define HW_LCD_PENL_SET(x, v)    (BME_OR32(HW_LCD_PENL_ADDR(x), (uint32_t)(v)))
#define HW_LCD_PENL_CLR(x, v)    (BME_AND32(HW_LCD_PENL_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_PENL_TOG(x, v)    (BME_XOR32(HW_LCD_PENL_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_PENL bitfields
 */

/*!
 * @name Register LCD_PENL, field PEN[31:0] (RW)
 *
 * The PEN[63:0] bits enable the LCD_P[63:0] pins for LCD operation. PENL
 * contains PEN[31:0], and PENH contains PEN[63:32]. Each LCD_P[63:0] pin can be
 * configured as a back plane or a front plane based on the corresponding BPEN[ n ] bit
 * in the Back Plane Enable register (BPEN). If LCDEN = 0, these bits enable the
 * pin to drive a low output. Set PEN[63:0] bits before LCDEN is set. When
 * PAD_SAFE=1, these bits have no effect in any condition on the LCD_P[63:0] pins.
 *
 * Values:
 * - 0 - LCD operation disabled on LCD_Pn.
 * - 1 - LCD operation enabled on LCD_Pn.
 */
/*@{*/
#define BP_LCD_PENL_PEN      (0U)          /*!< Bit position for LCD_PENL_PEN. */
#define BM_LCD_PENL_PEN      (0xFFFFFFFFU) /*!< Bit mask for LCD_PENL_PEN. */
#define BS_LCD_PENL_PEN      (32U)         /*!< Bit field size in bits for LCD_PENL_PEN. */

/*! @brief Read current value of the LCD_PENL_PEN field. */
#define BR_LCD_PENL_PEN(x)   (HW_LCD_PENL(x).U)

/*! @brief Format value for bitfield LCD_PENL_PEN. */
#define BF_LCD_PENL_PEN(v)   ((uint32_t)((uint32_t)(v) << BP_LCD_PENL_PEN) & BM_LCD_PENL_PEN)

/*! @brief Set the PEN field to a new value. */
#define BW_LCD_PENL_PEN(x, v) (HW_LCD_PENL_WR(x, v))
/*@}*/
/*******************************************************************************
 * HW_LCD_PENH - LCD Pin Enable register
 ******************************************************************************/

/*!
 * @brief HW_LCD_PENH - LCD Pin Enable register (RW)
 *
 * Reset value: 0x00000000U
 *
 * When LCDEN = 1,and PAD_SAFE=0 each PEN bit enables the corresponding LCD pin
 * (LCD_Pn) for LCD waveform generation.When LCDEN=0, each PEN bit enabled to
 * corresponding LCD pin (LCD_Pn) to drive a low output. Initialize these registers
 * before enabling the LCD controller. The reset value of this register depends
 * on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_penh
{
    uint32_t U;
    struct _hw_lcd_penh_bitfields
    {
        uint32_t PEN : 32;             /*!< [31:0] LCD Pin Enable */
    } B;
} hw_lcd_penh_t;

/*!
 * @name Constants and macros for entire LCD_PENH register
 */
/*@{*/
#define HW_LCD_PENH_ADDR(x)      ((x) + 0x14U)

#define HW_LCD_PENH(x)           (*(__IO hw_lcd_penh_t *) HW_LCD_PENH_ADDR(x))
#define HW_LCD_PENH_RD(x)        (HW_LCD_PENH(x).U)
#define HW_LCD_PENH_WR(x, v)     (HW_LCD_PENH(x).U = (v))
#define HW_LCD_PENH_SET(x, v)    (BME_OR32(HW_LCD_PENH_ADDR(x), (uint32_t)(v)))
#define HW_LCD_PENH_CLR(x, v)    (BME_AND32(HW_LCD_PENH_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_PENH_TOG(x, v)    (BME_XOR32(HW_LCD_PENH_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_PENH bitfields
 */

/*!
 * @name Register LCD_PENH, field PEN[31:0] (RW)
 *
 * The PEN[63:0] bits enable the LCD_P[63:0] pins for LCD operation. PENL
 * contains PEN[31:0], and PENH contains PEN[63:32]. Each LCD_P[63:0] pin can be
 * configured as a back plane or a front plane based on the corresponding BPEN[ n ] bit
 * in the Back Plane Enable register (BPEN). If LCDEN = 0, these bits enable the
 * pin to drive a low output. Set PEN[63:0] bits before LCDEN is set. When
 * PAD_SAFE=1, these bits have no effect in any condition on the LCD_P[63:0] pins.
 *
 * Values:
 * - 0 - LCD operation disabled on LCD_Pn.
 * - 1 - LCD operation enabled on LCD_Pn.
 */
/*@{*/
#define BP_LCD_PENH_PEN      (0U)          /*!< Bit position for LCD_PENH_PEN. */
#define BM_LCD_PENH_PEN      (0xFFFFFFFFU) /*!< Bit mask for LCD_PENH_PEN. */
#define BS_LCD_PENH_PEN      (32U)         /*!< Bit field size in bits for LCD_PENH_PEN. */

/*! @brief Read current value of the LCD_PENH_PEN field. */
#define BR_LCD_PENH_PEN(x)   (HW_LCD_PENH(x).U)

/*! @brief Format value for bitfield LCD_PENH_PEN. */
#define BF_LCD_PENH_PEN(v)   ((uint32_t)((uint32_t)(v) << BP_LCD_PENH_PEN) & BM_LCD_PENH_PEN)

/*! @brief Set the PEN field to a new value. */
#define BW_LCD_PENH_PEN(x, v) (HW_LCD_PENH_WR(x, v))
/*@}*/

/*******************************************************************************
 * HW_LCD_BPENL - LCD Back Plane Enable register
 ******************************************************************************/

/*!
 * @brief HW_LCD_BPENL - LCD Back Plane Enable register (RW)
 *
 * Reset value: 0x00000000U
 *
 * When PEN[n] = 1, the BPEN[63:0] bits configure the corresponding LCD pin to
 * operate as an LCD back plane or an LCD front plane. Most applications set a
 * maximum of eight of these bits. Initialize these registers before enabling the
 * LCD controller. The reset value of this register depends on the reset type: POR
 * - 0x0000_0000
 */
typedef union _hw_lcd_bpenl
{
    uint32_t U;
    struct _hw_lcd_bpenl_bitfields
    {
        uint32_t BPEN : 32;            /*!< [31:0] Back Plane Enable */
    } B;
} hw_lcd_bpenl_t;

/*!
 * @name Constants and macros for entire LCD_BPENL register
 */
/*@{*/
#define HW_LCD_BPENL_ADDR(x)     ((x) + 0x18U)

#define HW_LCD_BPENL(x)          (*(__IO hw_lcd_bpenl_t *) HW_LCD_BPENL_ADDR(x))
#define HW_LCD_BPENL_RD(x)       (HW_LCD_BPENL(x).U)
#define HW_LCD_BPENL_WR(x, v)    (HW_LCD_BPENL(x).U = (v))
#define HW_LCD_BPENL_SET(x, v)   (BME_OR32(HW_LCD_BPENL_ADDR(x), (uint32_t)(v)))
#define HW_LCD_BPENL_CLR(x, v)   (BME_AND32(HW_LCD_BPENL_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_BPENL_TOG(x, v)   (BME_XOR32(HW_LCD_BPENL_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_BPENL bitfields
 */

/*!
 * @name Register LCD_BPENL, field BPEN[31:0] (RW)
 *
 * The BPEN[63:0] bits configure the LCD_P[63:0] pins to operate as an LCD back
 * plane or LCD front plane. BPENL contains BPEN[31:0], and BPENH contains
 * BPEN[63:32]. If LCDEN = 0, these bits have no effect on the state of the I/O pins.
 * It is recommended to set BPEN[63:0] bits before LCDEN is set.
 *
 * Values:
 * - 0 - Front plane operation enabled on LCD_Pn.
 * - 1 - Back plane operation enabled on LCD_Pn.
 */
/*@{*/
#define BP_LCD_BPENL_BPEN    (0U)          /*!< Bit position for LCD_BPENL_BPEN. */
#define BM_LCD_BPENL_BPEN    (0xFFFFFFFFU) /*!< Bit mask for LCD_BPENL_BPEN. */
#define BS_LCD_BPENL_BPEN    (32U)         /*!< Bit field size in bits for LCD_BPENL_BPEN. */

/*! @brief Read current value of the LCD_BPENL_BPEN field. */
#define BR_LCD_BPENL_BPEN(x) (HW_LCD_BPENL(x).U)

/*! @brief Format value for bitfield LCD_BPENL_BPEN. */
#define BF_LCD_BPENL_BPEN(v) ((uint32_t)((uint32_t)(v) << BP_LCD_BPENL_BPEN) & BM_LCD_BPENL_BPEN)

/*! @brief Set the BPEN field to a new value. */
#define BW_LCD_BPENL_BPEN(x, v) (HW_LCD_BPENL_WR(x, v))
/*@}*/
/*******************************************************************************
 * HW_LCD_BPENH - LCD Back Plane Enable register
 ******************************************************************************/

/*!
 * @brief HW_LCD_BPENH - LCD Back Plane Enable register (RW)
 *
 * Reset value: 0x00000000U
 *
 * When PEN[n] = 1, the BPEN[63:0] bits configure the corresponding LCD pin to
 * operate as an LCD back plane or an LCD front plane. Most applications set a
 * maximum of eight of these bits. Initialize these registers before enabling the
 * LCD controller. The reset value of this register depends on the reset type: POR
 * - 0x0000_0000
 */
typedef union _hw_lcd_bpenh
{
    uint32_t U;
    struct _hw_lcd_bpenh_bitfields
    {
        uint32_t BPEN : 32;            /*!< [31:0] Back Plane Enable */
    } B;
} hw_lcd_bpenh_t;

/*!
 * @name Constants and macros for entire LCD_BPENH register
 */
/*@{*/
#define HW_LCD_BPENH_ADDR(x)     ((x) + 0x1CU)

#define HW_LCD_BPENH(x)          (*(__IO hw_lcd_bpenh_t *) HW_LCD_BPENH_ADDR(x))
#define HW_LCD_BPENH_RD(x)       (HW_LCD_BPENH(x).U)
#define HW_LCD_BPENH_WR(x, v)    (HW_LCD_BPENH(x).U = (v))
#define HW_LCD_BPENH_SET(x, v)   (BME_OR32(HW_LCD_BPENH_ADDR(x), (uint32_t)(v)))
#define HW_LCD_BPENH_CLR(x, v)   (BME_AND32(HW_LCD_BPENH_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_BPENH_TOG(x, v)   (BME_XOR32(HW_LCD_BPENH_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_BPENH bitfields
 */

/*!
 * @name Register LCD_BPENH, field BPEN[31:0] (RW)
 *
 * The BPEN[63:0] bits configure the LCD_P[63:0] pins to operate as an LCD back
 * plane or LCD front plane. BPENL contains BPEN[31:0], and BPENH contains
 * BPEN[63:32]. If LCDEN = 0, these bits have no effect on the state of the I/O pins.
 * It is recommended to set BPEN[63:0] bits before LCDEN is set.
 *
 * Values:
 * - 0 - Front plane operation enabled on LCD_Pn.
 * - 1 - Back plane operation enabled on LCD_Pn.
 */
/*@{*/
#define BP_LCD_BPENH_BPEN    (0U)          /*!< Bit position for LCD_BPENH_BPEN. */
#define BM_LCD_BPENH_BPEN    (0xFFFFFFFFU) /*!< Bit mask for LCD_BPENH_BPEN. */
#define BS_LCD_BPENH_BPEN    (32U)         /*!< Bit field size in bits for LCD_BPENH_BPEN. */

/*! @brief Read current value of the LCD_BPENH_BPEN field. */
#define BR_LCD_BPENH_BPEN(x) (HW_LCD_BPENH(x).U)

/*! @brief Format value for bitfield LCD_BPENH_BPEN. */
#define BF_LCD_BPENH_BPEN(v) ((uint32_t)((uint32_t)(v) << BP_LCD_BPENH_BPEN) & BM_LCD_BPENH_BPEN)

/*! @brief Set the BPEN field to a new value. */
#define BW_LCD_BPENH_BPEN(x, v) (HW_LCD_BPENH_WR(x, v))
/*@}*/

/*******************************************************************************
 * HW_LCD_WF3TO0 - LCD Waveform register
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF3TO0 - LCD Waveform register (RW)
 *
 * Reset value: 0x00000000U
 *
 * Each of the WFyTOx registers contains four waveform control (WFn) fields,
 * where x is the n index value of the WFn field in the least significant byte (bits
 * 7-0) and y is the n index value of the WFn field in the most significant byte
 * (bits 31-24). The bits in each WFn field control the front plane segments or
 * back plane phases connected to the LCD_Pn signal. In an LCD controller, each
 * element consists of a front plane segment and a back plane phase. These
 * segments and phases are labeled A through H (x8 multiplexing, 1/8 duty cycle). Each
 * LCD_Pn signal can be connected to one or more segments (in front plane
 * operation) or one or more phases (in back plane operation). An LCD element is turned
 * on when the associated back plane phase is activated and the front plane
 * segment is on. If LCD_Pn is configured for front plane operation, the bits in WFn
 * turn on or off each of the front plane segments connected to LCD_Pn: bit 0
 * controls segment A, bit 1 controls segment B, and so on. If LCD_Pn is configured
 * for back plane operation, the bits in WFn activate or deactivate each of the
 * back plane phases connected to LCD_Pn: bit 0 controls phase A, bit 1 controls
 * phase B, and so on. Software can write to this register with 8-bit, 16-bit, or
 * 32-bit writes. After reset, the WFyTOx register is cleared to 0. The reset value
 * of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_wf3to0
{
    uint32_t U;
    struct _hw_lcd_wf3to0_bitfields
    {
        uint32_t WF0 : 8;              /*!< [7:0]  */
        uint32_t WF1 : 8;              /*!< [15:8]  */
        uint32_t WF2 : 8;              /*!< [23:16]  */
        uint32_t WF3 : 8;              /*!< [31:24]  */
    } B;
} hw_lcd_wf3to0_t;

/*!
 * @name Constants and macros for entire LCD_WF3TO0 register
 */
/*@{*/
#define HW_LCD_WF3TO0_ADDR(x)    ((x) + 0x20U)

#define HW_LCD_WF3TO0(x)         (*(__IO hw_lcd_wf3to0_t *) HW_LCD_WF3TO0_ADDR(x))
#define HW_LCD_WF3TO0_RD(x)      (HW_LCD_WF3TO0(x).U)
#define HW_LCD_WF3TO0_WR(x, v)   (HW_LCD_WF3TO0(x).U = (v))
#define HW_LCD_WF3TO0_SET(x, v)  (BME_OR32(HW_LCD_WF3TO0_ADDR(x), (uint32_t)(v)))
#define HW_LCD_WF3TO0_CLR(x, v)  (BME_AND32(HW_LCD_WF3TO0_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_WF3TO0_TOG(x, v)  (BME_XOR32(HW_LCD_WF3TO0_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF3TO0 bitfields
 */

/*!
 * @name Register LCD_WF3TO0, field WF0[7:0] (RW)
 *
 * Controls segments or phases connected to LCD_P0 as described above for WF3.
 */
/*@{*/
#define BP_LCD_WF3TO0_WF0    (0U)          /*!< Bit position for LCD_WF3TO0_WF0. */
#define BM_LCD_WF3TO0_WF0    (0x000000FFU) /*!< Bit mask for LCD_WF3TO0_WF0. */
#define BS_LCD_WF3TO0_WF0    (8U)          /*!< Bit field size in bits for LCD_WF3TO0_WF0. */

/*! @brief Read current value of the LCD_WF3TO0_WF0 field. */
#define BR_LCD_WF3TO0_WF0(x) (BME_UBFX32(HW_LCD_WF3TO0_ADDR(x), BP_LCD_WF3TO0_WF0, BS_LCD_WF3TO0_WF0))

/*! @brief Format value for bitfield LCD_WF3TO0_WF0. */
#define BF_LCD_WF3TO0_WF0(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF3TO0_WF0) & BM_LCD_WF3TO0_WF0)

/*! @brief Set the WF0 field to a new value. */
#define BW_LCD_WF3TO0_WF0(x, v) (BME_BFI32(HW_LCD_WF3TO0_ADDR(x), ((uint32_t)(v) << BP_LCD_WF3TO0_WF0), BP_LCD_WF3TO0_WF0, 8))
/*@}*/

/*!
 * @name Register LCD_WF3TO0, field WF1[15:8] (RW)
 *
 * Controls segments or phases connected to LCD_P1 as described above for WF3.
 */
/*@{*/
#define BP_LCD_WF3TO0_WF1    (8U)          /*!< Bit position for LCD_WF3TO0_WF1. */
#define BM_LCD_WF3TO0_WF1    (0x0000FF00U) /*!< Bit mask for LCD_WF3TO0_WF1. */
#define BS_LCD_WF3TO0_WF1    (8U)          /*!< Bit field size in bits for LCD_WF3TO0_WF1. */

/*! @brief Read current value of the LCD_WF3TO0_WF1 field. */
#define BR_LCD_WF3TO0_WF1(x) (BME_UBFX32(HW_LCD_WF3TO0_ADDR(x), BP_LCD_WF3TO0_WF1, BS_LCD_WF3TO0_WF1))

/*! @brief Format value for bitfield LCD_WF3TO0_WF1. */
#define BF_LCD_WF3TO0_WF1(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF3TO0_WF1) & BM_LCD_WF3TO0_WF1)

/*! @brief Set the WF1 field to a new value. */
#define BW_LCD_WF3TO0_WF1(x, v) (BME_BFI32(HW_LCD_WF3TO0_ADDR(x), ((uint32_t)(v) << BP_LCD_WF3TO0_WF1), BP_LCD_WF3TO0_WF1, 8))
/*@}*/

/*!
 * @name Register LCD_WF3TO0, field WF2[23:16] (RW)
 *
 * Controls segments or phases connected to LCD_P2 as described above for WF3.
 */
/*@{*/
#define BP_LCD_WF3TO0_WF2    (16U)         /*!< Bit position for LCD_WF3TO0_WF2. */
#define BM_LCD_WF3TO0_WF2    (0x00FF0000U) /*!< Bit mask for LCD_WF3TO0_WF2. */
#define BS_LCD_WF3TO0_WF2    (8U)          /*!< Bit field size in bits for LCD_WF3TO0_WF2. */

/*! @brief Read current value of the LCD_WF3TO0_WF2 field. */
#define BR_LCD_WF3TO0_WF2(x) (BME_UBFX32(HW_LCD_WF3TO0_ADDR(x), BP_LCD_WF3TO0_WF2, BS_LCD_WF3TO0_WF2))

/*! @brief Format value for bitfield LCD_WF3TO0_WF2. */
#define BF_LCD_WF3TO0_WF2(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF3TO0_WF2) & BM_LCD_WF3TO0_WF2)

/*! @brief Set the WF2 field to a new value. */
#define BW_LCD_WF3TO0_WF2(x, v) (BME_BFI32(HW_LCD_WF3TO0_ADDR(x), ((uint32_t)(v) << BP_LCD_WF3TO0_WF2), BP_LCD_WF3TO0_WF2, 8))
/*@}*/

/*!
 * @name Register LCD_WF3TO0, field WF3[31:24] (RW)
 *
 * Segment-on front plane operation - Each bit turns on or off the segments
 * associated with LCD_P3 in the following pattern: HGFEDCBA (most significant bit
 * controls segment H and least significant bit controls segment A). Segment-on
 * back plane operation - Each bit activates or deactivates the phases associated
 * with LCD_P3 in the following pattern: HGFEDCBA (most significant bit controls
 * phase H and least significant bit controls phase A). For each bit: 0 Segment off
 * or phase deactivated 1 Segment on or phase activated
 */
/*@{*/
#define BP_LCD_WF3TO0_WF3    (24U)         /*!< Bit position for LCD_WF3TO0_WF3. */
#define BM_LCD_WF3TO0_WF3    (0xFF000000U) /*!< Bit mask for LCD_WF3TO0_WF3. */
#define BS_LCD_WF3TO0_WF3    (8U)          /*!< Bit field size in bits for LCD_WF3TO0_WF3. */

/*! @brief Read current value of the LCD_WF3TO0_WF3 field. */
#define BR_LCD_WF3TO0_WF3(x) (BME_UBFX32(HW_LCD_WF3TO0_ADDR(x), BP_LCD_WF3TO0_WF3, BS_LCD_WF3TO0_WF3))

/*! @brief Format value for bitfield LCD_WF3TO0_WF3. */
#define BF_LCD_WF3TO0_WF3(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF3TO0_WF3) & BM_LCD_WF3TO0_WF3)

/*! @brief Set the WF3 field to a new value. */
#define BW_LCD_WF3TO0_WF3(x, v) (BME_BFI32(HW_LCD_WF3TO0_ADDR(x), ((uint32_t)(v) << BP_LCD_WF3TO0_WF3), BP_LCD_WF3TO0_WF3, 8))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF7TO4 - LCD Waveform register
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF7TO4 - LCD Waveform register (RW)
 *
 * Reset value: 0x00000000U
 *
 * See the LCD Waveform register (WFC3TO0) for register and field descriptions.
 * The reset value of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_wf7to4
{
    uint32_t U;
    struct _hw_lcd_wf7to4_bitfields
    {
        uint32_t WF4 : 8;              /*!< [7:0]  */
        uint32_t WF5 : 8;              /*!< [15:8]  */
        uint32_t WF6 : 8;              /*!< [23:16]  */
        uint32_t WF7 : 8;              /*!< [31:24]  */
    } B;
} hw_lcd_wf7to4_t;

/*!
 * @name Constants and macros for entire LCD_WF7TO4 register
 */
/*@{*/
#define HW_LCD_WF7TO4_ADDR(x)    ((x) + 0x24U)

#define HW_LCD_WF7TO4(x)         (*(__IO hw_lcd_wf7to4_t *) HW_LCD_WF7TO4_ADDR(x))
#define HW_LCD_WF7TO4_RD(x)      (HW_LCD_WF7TO4(x).U)
#define HW_LCD_WF7TO4_WR(x, v)   (HW_LCD_WF7TO4(x).U = (v))
#define HW_LCD_WF7TO4_SET(x, v)  (BME_OR32(HW_LCD_WF7TO4_ADDR(x), (uint32_t)(v)))
#define HW_LCD_WF7TO4_CLR(x, v)  (BME_AND32(HW_LCD_WF7TO4_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_WF7TO4_TOG(x, v)  (BME_XOR32(HW_LCD_WF7TO4_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF7TO4 bitfields
 */

/*!
 * @name Register LCD_WF7TO4, field WF4[7:0] (RW)
 *
 * Controls segments or phases connected to LCD_P4 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF7TO4_WF4    (0U)          /*!< Bit position for LCD_WF7TO4_WF4. */
#define BM_LCD_WF7TO4_WF4    (0x000000FFU) /*!< Bit mask for LCD_WF7TO4_WF4. */
#define BS_LCD_WF7TO4_WF4    (8U)          /*!< Bit field size in bits for LCD_WF7TO4_WF4. */

/*! @brief Read current value of the LCD_WF7TO4_WF4 field. */
#define BR_LCD_WF7TO4_WF4(x) (BME_UBFX32(HW_LCD_WF7TO4_ADDR(x), BP_LCD_WF7TO4_WF4, BS_LCD_WF7TO4_WF4))

/*! @brief Format value for bitfield LCD_WF7TO4_WF4. */
#define BF_LCD_WF7TO4_WF4(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF7TO4_WF4) & BM_LCD_WF7TO4_WF4)

/*! @brief Set the WF4 field to a new value. */
#define BW_LCD_WF7TO4_WF4(x, v) (BME_BFI32(HW_LCD_WF7TO4_ADDR(x), ((uint32_t)(v) << BP_LCD_WF7TO4_WF4), BP_LCD_WF7TO4_WF4, 8))
/*@}*/

/*!
 * @name Register LCD_WF7TO4, field WF5[15:8] (RW)
 *
 * Controls segments or phases connected to LCD_P5 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF7TO4_WF5    (8U)          /*!< Bit position for LCD_WF7TO4_WF5. */
#define BM_LCD_WF7TO4_WF5    (0x0000FF00U) /*!< Bit mask for LCD_WF7TO4_WF5. */
#define BS_LCD_WF7TO4_WF5    (8U)          /*!< Bit field size in bits for LCD_WF7TO4_WF5. */

/*! @brief Read current value of the LCD_WF7TO4_WF5 field. */
#define BR_LCD_WF7TO4_WF5(x) (BME_UBFX32(HW_LCD_WF7TO4_ADDR(x), BP_LCD_WF7TO4_WF5, BS_LCD_WF7TO4_WF5))

/*! @brief Format value for bitfield LCD_WF7TO4_WF5. */
#define BF_LCD_WF7TO4_WF5(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF7TO4_WF5) & BM_LCD_WF7TO4_WF5)

/*! @brief Set the WF5 field to a new value. */
#define BW_LCD_WF7TO4_WF5(x, v) (BME_BFI32(HW_LCD_WF7TO4_ADDR(x), ((uint32_t)(v) << BP_LCD_WF7TO4_WF5), BP_LCD_WF7TO4_WF5, 8))
/*@}*/

/*!
 * @name Register LCD_WF7TO4, field WF6[23:16] (RW)
 *
 * Controls segments or phases connected to LCD_P6 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF7TO4_WF6    (16U)         /*!< Bit position for LCD_WF7TO4_WF6. */
#define BM_LCD_WF7TO4_WF6    (0x00FF0000U) /*!< Bit mask for LCD_WF7TO4_WF6. */
#define BS_LCD_WF7TO4_WF6    (8U)          /*!< Bit field size in bits for LCD_WF7TO4_WF6. */

/*! @brief Read current value of the LCD_WF7TO4_WF6 field. */
#define BR_LCD_WF7TO4_WF6(x) (BME_UBFX32(HW_LCD_WF7TO4_ADDR(x), BP_LCD_WF7TO4_WF6, BS_LCD_WF7TO4_WF6))

/*! @brief Format value for bitfield LCD_WF7TO4_WF6. */
#define BF_LCD_WF7TO4_WF6(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF7TO4_WF6) & BM_LCD_WF7TO4_WF6)

/*! @brief Set the WF6 field to a new value. */
#define BW_LCD_WF7TO4_WF6(x, v) (BME_BFI32(HW_LCD_WF7TO4_ADDR(x), ((uint32_t)(v) << BP_LCD_WF7TO4_WF6), BP_LCD_WF7TO4_WF6, 8))
/*@}*/

/*!
 * @name Register LCD_WF7TO4, field WF7[31:24] (RW)
 *
 * Controls segments or phases connected to LCD_P7 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF7TO4_WF7    (24U)         /*!< Bit position for LCD_WF7TO4_WF7. */
#define BM_LCD_WF7TO4_WF7    (0xFF000000U) /*!< Bit mask for LCD_WF7TO4_WF7. */
#define BS_LCD_WF7TO4_WF7    (8U)          /*!< Bit field size in bits for LCD_WF7TO4_WF7. */

/*! @brief Read current value of the LCD_WF7TO4_WF7 field. */
#define BR_LCD_WF7TO4_WF7(x) (BME_UBFX32(HW_LCD_WF7TO4_ADDR(x), BP_LCD_WF7TO4_WF7, BS_LCD_WF7TO4_WF7))

/*! @brief Format value for bitfield LCD_WF7TO4_WF7. */
#define BF_LCD_WF7TO4_WF7(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF7TO4_WF7) & BM_LCD_WF7TO4_WF7)

/*! @brief Set the WF7 field to a new value. */
#define BW_LCD_WF7TO4_WF7(x, v) (BME_BFI32(HW_LCD_WF7TO4_ADDR(x), ((uint32_t)(v) << BP_LCD_WF7TO4_WF7), BP_LCD_WF7TO4_WF7, 8))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF11TO8 - LCD Waveform register
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF11TO8 - LCD Waveform register (RW)
 *
 * Reset value: 0x00000000U
 *
 * See the LCD Waveform register (WFC3TO0) for register and field descriptions.
 * The reset value of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_wf11to8
{
    uint32_t U;
    struct _hw_lcd_wf11to8_bitfields
    {
        uint32_t WF8 : 8;              /*!< [7:0]  */
        uint32_t WF9 : 8;              /*!< [15:8]  */
        uint32_t WF10 : 8;             /*!< [23:16]  */
        uint32_t WF11 : 8;             /*!< [31:24]  */
    } B;
} hw_lcd_wf11to8_t;

/*!
 * @name Constants and macros for entire LCD_WF11TO8 register
 */
/*@{*/
#define HW_LCD_WF11TO8_ADDR(x)   ((x) + 0x28U)

#define HW_LCD_WF11TO8(x)        (*(__IO hw_lcd_wf11to8_t *) HW_LCD_WF11TO8_ADDR(x))
#define HW_LCD_WF11TO8_RD(x)     (HW_LCD_WF11TO8(x).U)
#define HW_LCD_WF11TO8_WR(x, v)  (HW_LCD_WF11TO8(x).U = (v))
#define HW_LCD_WF11TO8_SET(x, v) (BME_OR32(HW_LCD_WF11TO8_ADDR(x), (uint32_t)(v)))
#define HW_LCD_WF11TO8_CLR(x, v) (BME_AND32(HW_LCD_WF11TO8_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_WF11TO8_TOG(x, v) (BME_XOR32(HW_LCD_WF11TO8_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF11TO8 bitfields
 */

/*!
 * @name Register LCD_WF11TO8, field WF8[7:0] (RW)
 *
 * Controls segments or phases connected to LCD_P8 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF11TO8_WF8   (0U)          /*!< Bit position for LCD_WF11TO8_WF8. */
#define BM_LCD_WF11TO8_WF8   (0x000000FFU) /*!< Bit mask for LCD_WF11TO8_WF8. */
#define BS_LCD_WF11TO8_WF8   (8U)          /*!< Bit field size in bits for LCD_WF11TO8_WF8. */

/*! @brief Read current value of the LCD_WF11TO8_WF8 field. */
#define BR_LCD_WF11TO8_WF8(x) (BME_UBFX32(HW_LCD_WF11TO8_ADDR(x), BP_LCD_WF11TO8_WF8, BS_LCD_WF11TO8_WF8))

/*! @brief Format value for bitfield LCD_WF11TO8_WF8. */
#define BF_LCD_WF11TO8_WF8(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF11TO8_WF8) & BM_LCD_WF11TO8_WF8)

/*! @brief Set the WF8 field to a new value. */
#define BW_LCD_WF11TO8_WF8(x, v) (BME_BFI32(HW_LCD_WF11TO8_ADDR(x), ((uint32_t)(v) << BP_LCD_WF11TO8_WF8), BP_LCD_WF11TO8_WF8, 8))
/*@}*/

/*!
 * @name Register LCD_WF11TO8, field WF9[15:8] (RW)
 *
 * Controls segments or phases connected to LCD_P9 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF11TO8_WF9   (8U)          /*!< Bit position for LCD_WF11TO8_WF9. */
#define BM_LCD_WF11TO8_WF9   (0x0000FF00U) /*!< Bit mask for LCD_WF11TO8_WF9. */
#define BS_LCD_WF11TO8_WF9   (8U)          /*!< Bit field size in bits for LCD_WF11TO8_WF9. */

/*! @brief Read current value of the LCD_WF11TO8_WF9 field. */
#define BR_LCD_WF11TO8_WF9(x) (BME_UBFX32(HW_LCD_WF11TO8_ADDR(x), BP_LCD_WF11TO8_WF9, BS_LCD_WF11TO8_WF9))

/*! @brief Format value for bitfield LCD_WF11TO8_WF9. */
#define BF_LCD_WF11TO8_WF9(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF11TO8_WF9) & BM_LCD_WF11TO8_WF9)

/*! @brief Set the WF9 field to a new value. */
#define BW_LCD_WF11TO8_WF9(x, v) (BME_BFI32(HW_LCD_WF11TO8_ADDR(x), ((uint32_t)(v) << BP_LCD_WF11TO8_WF9), BP_LCD_WF11TO8_WF9, 8))
/*@}*/

/*!
 * @name Register LCD_WF11TO8, field WF10[23:16] (RW)
 *
 * Controls segments or phases connected to LCD_P10 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF11TO8_WF10  (16U)         /*!< Bit position for LCD_WF11TO8_WF10. */
#define BM_LCD_WF11TO8_WF10  (0x00FF0000U) /*!< Bit mask for LCD_WF11TO8_WF10. */
#define BS_LCD_WF11TO8_WF10  (8U)          /*!< Bit field size in bits for LCD_WF11TO8_WF10. */

/*! @brief Read current value of the LCD_WF11TO8_WF10 field. */
#define BR_LCD_WF11TO8_WF10(x) (BME_UBFX32(HW_LCD_WF11TO8_ADDR(x), BP_LCD_WF11TO8_WF10, BS_LCD_WF11TO8_WF10))

/*! @brief Format value for bitfield LCD_WF11TO8_WF10. */
#define BF_LCD_WF11TO8_WF10(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF11TO8_WF10) & BM_LCD_WF11TO8_WF10)

/*! @brief Set the WF10 field to a new value. */
#define BW_LCD_WF11TO8_WF10(x, v) (BME_BFI32(HW_LCD_WF11TO8_ADDR(x), ((uint32_t)(v) << BP_LCD_WF11TO8_WF10), BP_LCD_WF11TO8_WF10, 8))
/*@}*/

/*!
 * @name Register LCD_WF11TO8, field WF11[31:24] (RW)
 *
 * Controls segments or phases connected to LCD_P11 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF11TO8_WF11  (24U)         /*!< Bit position for LCD_WF11TO8_WF11. */
#define BM_LCD_WF11TO8_WF11  (0xFF000000U) /*!< Bit mask for LCD_WF11TO8_WF11. */
#define BS_LCD_WF11TO8_WF11  (8U)          /*!< Bit field size in bits for LCD_WF11TO8_WF11. */

/*! @brief Read current value of the LCD_WF11TO8_WF11 field. */
#define BR_LCD_WF11TO8_WF11(x) (BME_UBFX32(HW_LCD_WF11TO8_ADDR(x), BP_LCD_WF11TO8_WF11, BS_LCD_WF11TO8_WF11))

/*! @brief Format value for bitfield LCD_WF11TO8_WF11. */
#define BF_LCD_WF11TO8_WF11(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF11TO8_WF11) & BM_LCD_WF11TO8_WF11)

/*! @brief Set the WF11 field to a new value. */
#define BW_LCD_WF11TO8_WF11(x, v) (BME_BFI32(HW_LCD_WF11TO8_ADDR(x), ((uint32_t)(v) << BP_LCD_WF11TO8_WF11), BP_LCD_WF11TO8_WF11, 8))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF15TO12 - LCD Waveform register
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF15TO12 - LCD Waveform register (RW)
 *
 * Reset value: 0x00000000U
 *
 * See the LCD Waveform register (WFC3TO0) for register and field descriptions.
 * The reset value of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_wf15to12
{
    uint32_t U;
    struct _hw_lcd_wf15to12_bitfields
    {
        uint32_t WF12 : 8;             /*!< [7:0]  */
        uint32_t WF13 : 8;             /*!< [15:8]  */
        uint32_t WF14 : 8;             /*!< [23:16]  */
        uint32_t WF15 : 8;             /*!< [31:24]  */
    } B;
} hw_lcd_wf15to12_t;

/*!
 * @name Constants and macros for entire LCD_WF15TO12 register
 */
/*@{*/
#define HW_LCD_WF15TO12_ADDR(x)  ((x) + 0x2CU)

#define HW_LCD_WF15TO12(x)       (*(__IO hw_lcd_wf15to12_t *) HW_LCD_WF15TO12_ADDR(x))
#define HW_LCD_WF15TO12_RD(x)    (HW_LCD_WF15TO12(x).U)
#define HW_LCD_WF15TO12_WR(x, v) (HW_LCD_WF15TO12(x).U = (v))
#define HW_LCD_WF15TO12_SET(x, v) (BME_OR32(HW_LCD_WF15TO12_ADDR(x), (uint32_t)(v)))
#define HW_LCD_WF15TO12_CLR(x, v) (BME_AND32(HW_LCD_WF15TO12_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_WF15TO12_TOG(x, v) (BME_XOR32(HW_LCD_WF15TO12_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF15TO12 bitfields
 */

/*!
 * @name Register LCD_WF15TO12, field WF12[7:0] (RW)
 *
 * Controls segments or phases connected to LCD_P12 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF15TO12_WF12 (0U)          /*!< Bit position for LCD_WF15TO12_WF12. */
#define BM_LCD_WF15TO12_WF12 (0x000000FFU) /*!< Bit mask for LCD_WF15TO12_WF12. */
#define BS_LCD_WF15TO12_WF12 (8U)          /*!< Bit field size in bits for LCD_WF15TO12_WF12. */

/*! @brief Read current value of the LCD_WF15TO12_WF12 field. */
#define BR_LCD_WF15TO12_WF12(x) (BME_UBFX32(HW_LCD_WF15TO12_ADDR(x), BP_LCD_WF15TO12_WF12, BS_LCD_WF15TO12_WF12))

/*! @brief Format value for bitfield LCD_WF15TO12_WF12. */
#define BF_LCD_WF15TO12_WF12(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF15TO12_WF12) & BM_LCD_WF15TO12_WF12)

/*! @brief Set the WF12 field to a new value. */
#define BW_LCD_WF15TO12_WF12(x, v) (BME_BFI32(HW_LCD_WF15TO12_ADDR(x), ((uint32_t)(v) << BP_LCD_WF15TO12_WF12), BP_LCD_WF15TO12_WF12, 8))
/*@}*/

/*!
 * @name Register LCD_WF15TO12, field WF13[15:8] (RW)
 *
 * Controls segments or phases connected to LCD_P13 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF15TO12_WF13 (8U)          /*!< Bit position for LCD_WF15TO12_WF13. */
#define BM_LCD_WF15TO12_WF13 (0x0000FF00U) /*!< Bit mask for LCD_WF15TO12_WF13. */
#define BS_LCD_WF15TO12_WF13 (8U)          /*!< Bit field size in bits for LCD_WF15TO12_WF13. */

/*! @brief Read current value of the LCD_WF15TO12_WF13 field. */
#define BR_LCD_WF15TO12_WF13(x) (BME_UBFX32(HW_LCD_WF15TO12_ADDR(x), BP_LCD_WF15TO12_WF13, BS_LCD_WF15TO12_WF13))

/*! @brief Format value for bitfield LCD_WF15TO12_WF13. */
#define BF_LCD_WF15TO12_WF13(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF15TO12_WF13) & BM_LCD_WF15TO12_WF13)

/*! @brief Set the WF13 field to a new value. */
#define BW_LCD_WF15TO12_WF13(x, v) (BME_BFI32(HW_LCD_WF15TO12_ADDR(x), ((uint32_t)(v) << BP_LCD_WF15TO12_WF13), BP_LCD_WF15TO12_WF13, 8))
/*@}*/

/*!
 * @name Register LCD_WF15TO12, field WF14[23:16] (RW)
 *
 * Controls segments or phases connected to LCD_P14 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF15TO12_WF14 (16U)         /*!< Bit position for LCD_WF15TO12_WF14. */
#define BM_LCD_WF15TO12_WF14 (0x00FF0000U) /*!< Bit mask for LCD_WF15TO12_WF14. */
#define BS_LCD_WF15TO12_WF14 (8U)          /*!< Bit field size in bits for LCD_WF15TO12_WF14. */

/*! @brief Read current value of the LCD_WF15TO12_WF14 field. */
#define BR_LCD_WF15TO12_WF14(x) (BME_UBFX32(HW_LCD_WF15TO12_ADDR(x), BP_LCD_WF15TO12_WF14, BS_LCD_WF15TO12_WF14))

/*! @brief Format value for bitfield LCD_WF15TO12_WF14. */
#define BF_LCD_WF15TO12_WF14(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF15TO12_WF14) & BM_LCD_WF15TO12_WF14)

/*! @brief Set the WF14 field to a new value. */
#define BW_LCD_WF15TO12_WF14(x, v) (BME_BFI32(HW_LCD_WF15TO12_ADDR(x), ((uint32_t)(v) << BP_LCD_WF15TO12_WF14), BP_LCD_WF15TO12_WF14, 8))
/*@}*/

/*!
 * @name Register LCD_WF15TO12, field WF15[31:24] (RW)
 *
 * Controls segments or phases connected to LCD_P15 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF15TO12_WF15 (24U)         /*!< Bit position for LCD_WF15TO12_WF15. */
#define BM_LCD_WF15TO12_WF15 (0xFF000000U) /*!< Bit mask for LCD_WF15TO12_WF15. */
#define BS_LCD_WF15TO12_WF15 (8U)          /*!< Bit field size in bits for LCD_WF15TO12_WF15. */

/*! @brief Read current value of the LCD_WF15TO12_WF15 field. */
#define BR_LCD_WF15TO12_WF15(x) (BME_UBFX32(HW_LCD_WF15TO12_ADDR(x), BP_LCD_WF15TO12_WF15, BS_LCD_WF15TO12_WF15))

/*! @brief Format value for bitfield LCD_WF15TO12_WF15. */
#define BF_LCD_WF15TO12_WF15(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF15TO12_WF15) & BM_LCD_WF15TO12_WF15)

/*! @brief Set the WF15 field to a new value. */
#define BW_LCD_WF15TO12_WF15(x, v) (BME_BFI32(HW_LCD_WF15TO12_ADDR(x), ((uint32_t)(v) << BP_LCD_WF15TO12_WF15), BP_LCD_WF15TO12_WF15, 8))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF19TO16 - LCD Waveform register
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF19TO16 - LCD Waveform register (RW)
 *
 * Reset value: 0x00000000U
 *
 * See the LCD Waveform register (WFC3TO0) for register and field descriptions.
 * The reset value of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_wf19to16
{
    uint32_t U;
    struct _hw_lcd_wf19to16_bitfields
    {
        uint32_t WF16 : 8;             /*!< [7:0]  */
        uint32_t WF17 : 8;             /*!< [15:8]  */
        uint32_t WF18 : 8;             /*!< [23:16]  */
        uint32_t WF19 : 8;             /*!< [31:24]  */
    } B;
} hw_lcd_wf19to16_t;

/*!
 * @name Constants and macros for entire LCD_WF19TO16 register
 */
/*@{*/
#define HW_LCD_WF19TO16_ADDR(x)  ((x) + 0x30U)

#define HW_LCD_WF19TO16(x)       (*(__IO hw_lcd_wf19to16_t *) HW_LCD_WF19TO16_ADDR(x))
#define HW_LCD_WF19TO16_RD(x)    (HW_LCD_WF19TO16(x).U)
#define HW_LCD_WF19TO16_WR(x, v) (HW_LCD_WF19TO16(x).U = (v))
#define HW_LCD_WF19TO16_SET(x, v) (BME_OR32(HW_LCD_WF19TO16_ADDR(x), (uint32_t)(v)))
#define HW_LCD_WF19TO16_CLR(x, v) (BME_AND32(HW_LCD_WF19TO16_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_WF19TO16_TOG(x, v) (BME_XOR32(HW_LCD_WF19TO16_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF19TO16 bitfields
 */

/*!
 * @name Register LCD_WF19TO16, field WF16[7:0] (RW)
 *
 * Controls segments or phases connected to LCD_P16 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF19TO16_WF16 (0U)          /*!< Bit position for LCD_WF19TO16_WF16. */
#define BM_LCD_WF19TO16_WF16 (0x000000FFU) /*!< Bit mask for LCD_WF19TO16_WF16. */
#define BS_LCD_WF19TO16_WF16 (8U)          /*!< Bit field size in bits for LCD_WF19TO16_WF16. */

/*! @brief Read current value of the LCD_WF19TO16_WF16 field. */
#define BR_LCD_WF19TO16_WF16(x) (BME_UBFX32(HW_LCD_WF19TO16_ADDR(x), BP_LCD_WF19TO16_WF16, BS_LCD_WF19TO16_WF16))

/*! @brief Format value for bitfield LCD_WF19TO16_WF16. */
#define BF_LCD_WF19TO16_WF16(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF19TO16_WF16) & BM_LCD_WF19TO16_WF16)

/*! @brief Set the WF16 field to a new value. */
#define BW_LCD_WF19TO16_WF16(x, v) (BME_BFI32(HW_LCD_WF19TO16_ADDR(x), ((uint32_t)(v) << BP_LCD_WF19TO16_WF16), BP_LCD_WF19TO16_WF16, 8))
/*@}*/

/*!
 * @name Register LCD_WF19TO16, field WF17[15:8] (RW)
 *
 * Controls segments or phases connected to LCD_P17 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF19TO16_WF17 (8U)          /*!< Bit position for LCD_WF19TO16_WF17. */
#define BM_LCD_WF19TO16_WF17 (0x0000FF00U) /*!< Bit mask for LCD_WF19TO16_WF17. */
#define BS_LCD_WF19TO16_WF17 (8U)          /*!< Bit field size in bits for LCD_WF19TO16_WF17. */

/*! @brief Read current value of the LCD_WF19TO16_WF17 field. */
#define BR_LCD_WF19TO16_WF17(x) (BME_UBFX32(HW_LCD_WF19TO16_ADDR(x), BP_LCD_WF19TO16_WF17, BS_LCD_WF19TO16_WF17))

/*! @brief Format value for bitfield LCD_WF19TO16_WF17. */
#define BF_LCD_WF19TO16_WF17(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF19TO16_WF17) & BM_LCD_WF19TO16_WF17)

/*! @brief Set the WF17 field to a new value. */
#define BW_LCD_WF19TO16_WF17(x, v) (BME_BFI32(HW_LCD_WF19TO16_ADDR(x), ((uint32_t)(v) << BP_LCD_WF19TO16_WF17), BP_LCD_WF19TO16_WF17, 8))
/*@}*/

/*!
 * @name Register LCD_WF19TO16, field WF18[23:16] (RW)
 *
 * Controls segments or phases connected to LCD_P18 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF19TO16_WF18 (16U)         /*!< Bit position for LCD_WF19TO16_WF18. */
#define BM_LCD_WF19TO16_WF18 (0x00FF0000U) /*!< Bit mask for LCD_WF19TO16_WF18. */
#define BS_LCD_WF19TO16_WF18 (8U)          /*!< Bit field size in bits for LCD_WF19TO16_WF18. */

/*! @brief Read current value of the LCD_WF19TO16_WF18 field. */
#define BR_LCD_WF19TO16_WF18(x) (BME_UBFX32(HW_LCD_WF19TO16_ADDR(x), BP_LCD_WF19TO16_WF18, BS_LCD_WF19TO16_WF18))

/*! @brief Format value for bitfield LCD_WF19TO16_WF18. */
#define BF_LCD_WF19TO16_WF18(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF19TO16_WF18) & BM_LCD_WF19TO16_WF18)

/*! @brief Set the WF18 field to a new value. */
#define BW_LCD_WF19TO16_WF18(x, v) (BME_BFI32(HW_LCD_WF19TO16_ADDR(x), ((uint32_t)(v) << BP_LCD_WF19TO16_WF18), BP_LCD_WF19TO16_WF18, 8))
/*@}*/

/*!
 * @name Register LCD_WF19TO16, field WF19[31:24] (RW)
 *
 * Controls segments or phases connected to LCD_P19 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF19TO16_WF19 (24U)         /*!< Bit position for LCD_WF19TO16_WF19. */
#define BM_LCD_WF19TO16_WF19 (0xFF000000U) /*!< Bit mask for LCD_WF19TO16_WF19. */
#define BS_LCD_WF19TO16_WF19 (8U)          /*!< Bit field size in bits for LCD_WF19TO16_WF19. */

/*! @brief Read current value of the LCD_WF19TO16_WF19 field. */
#define BR_LCD_WF19TO16_WF19(x) (BME_UBFX32(HW_LCD_WF19TO16_ADDR(x), BP_LCD_WF19TO16_WF19, BS_LCD_WF19TO16_WF19))

/*! @brief Format value for bitfield LCD_WF19TO16_WF19. */
#define BF_LCD_WF19TO16_WF19(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF19TO16_WF19) & BM_LCD_WF19TO16_WF19)

/*! @brief Set the WF19 field to a new value. */
#define BW_LCD_WF19TO16_WF19(x, v) (BME_BFI32(HW_LCD_WF19TO16_ADDR(x), ((uint32_t)(v) << BP_LCD_WF19TO16_WF19), BP_LCD_WF19TO16_WF19, 8))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF23TO20 - LCD Waveform register
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF23TO20 - LCD Waveform register (RW)
 *
 * Reset value: 0x00000000U
 *
 * See the LCD Waveform register (WFC3TO0) for register and field descriptions.
 * The reset value of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_wf23to20
{
    uint32_t U;
    struct _hw_lcd_wf23to20_bitfields
    {
        uint32_t WF20 : 8;             /*!< [7:0]  */
        uint32_t WF21 : 8;             /*!< [15:8]  */
        uint32_t WF22 : 8;             /*!< [23:16]  */
        uint32_t WF23 : 8;             /*!< [31:24]  */
    } B;
} hw_lcd_wf23to20_t;

/*!
 * @name Constants and macros for entire LCD_WF23TO20 register
 */
/*@{*/
#define HW_LCD_WF23TO20_ADDR(x)  ((x) + 0x34U)

#define HW_LCD_WF23TO20(x)       (*(__IO hw_lcd_wf23to20_t *) HW_LCD_WF23TO20_ADDR(x))
#define HW_LCD_WF23TO20_RD(x)    (HW_LCD_WF23TO20(x).U)
#define HW_LCD_WF23TO20_WR(x, v) (HW_LCD_WF23TO20(x).U = (v))
#define HW_LCD_WF23TO20_SET(x, v) (BME_OR32(HW_LCD_WF23TO20_ADDR(x), (uint32_t)(v)))
#define HW_LCD_WF23TO20_CLR(x, v) (BME_AND32(HW_LCD_WF23TO20_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_WF23TO20_TOG(x, v) (BME_XOR32(HW_LCD_WF23TO20_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF23TO20 bitfields
 */

/*!
 * @name Register LCD_WF23TO20, field WF20[7:0] (RW)
 *
 * Controls segments or phases connected to LCD_P20 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF23TO20_WF20 (0U)          /*!< Bit position for LCD_WF23TO20_WF20. */
#define BM_LCD_WF23TO20_WF20 (0x000000FFU) /*!< Bit mask for LCD_WF23TO20_WF20. */
#define BS_LCD_WF23TO20_WF20 (8U)          /*!< Bit field size in bits for LCD_WF23TO20_WF20. */

/*! @brief Read current value of the LCD_WF23TO20_WF20 field. */
#define BR_LCD_WF23TO20_WF20(x) (BME_UBFX32(HW_LCD_WF23TO20_ADDR(x), BP_LCD_WF23TO20_WF20, BS_LCD_WF23TO20_WF20))

/*! @brief Format value for bitfield LCD_WF23TO20_WF20. */
#define BF_LCD_WF23TO20_WF20(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF23TO20_WF20) & BM_LCD_WF23TO20_WF20)

/*! @brief Set the WF20 field to a new value. */
#define BW_LCD_WF23TO20_WF20(x, v) (BME_BFI32(HW_LCD_WF23TO20_ADDR(x), ((uint32_t)(v) << BP_LCD_WF23TO20_WF20), BP_LCD_WF23TO20_WF20, 8))
/*@}*/

/*!
 * @name Register LCD_WF23TO20, field WF21[15:8] (RW)
 *
 * Controls segments or phases connected to LCD_P21 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF23TO20_WF21 (8U)          /*!< Bit position for LCD_WF23TO20_WF21. */
#define BM_LCD_WF23TO20_WF21 (0x0000FF00U) /*!< Bit mask for LCD_WF23TO20_WF21. */
#define BS_LCD_WF23TO20_WF21 (8U)          /*!< Bit field size in bits for LCD_WF23TO20_WF21. */

/*! @brief Read current value of the LCD_WF23TO20_WF21 field. */
#define BR_LCD_WF23TO20_WF21(x) (BME_UBFX32(HW_LCD_WF23TO20_ADDR(x), BP_LCD_WF23TO20_WF21, BS_LCD_WF23TO20_WF21))

/*! @brief Format value for bitfield LCD_WF23TO20_WF21. */
#define BF_LCD_WF23TO20_WF21(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF23TO20_WF21) & BM_LCD_WF23TO20_WF21)

/*! @brief Set the WF21 field to a new value. */
#define BW_LCD_WF23TO20_WF21(x, v) (BME_BFI32(HW_LCD_WF23TO20_ADDR(x), ((uint32_t)(v) << BP_LCD_WF23TO20_WF21), BP_LCD_WF23TO20_WF21, 8))
/*@}*/

/*!
 * @name Register LCD_WF23TO20, field WF22[23:16] (RW)
 *
 * Controls segments or phases connected to LCD_P22 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF23TO20_WF22 (16U)         /*!< Bit position for LCD_WF23TO20_WF22. */
#define BM_LCD_WF23TO20_WF22 (0x00FF0000U) /*!< Bit mask for LCD_WF23TO20_WF22. */
#define BS_LCD_WF23TO20_WF22 (8U)          /*!< Bit field size in bits for LCD_WF23TO20_WF22. */

/*! @brief Read current value of the LCD_WF23TO20_WF22 field. */
#define BR_LCD_WF23TO20_WF22(x) (BME_UBFX32(HW_LCD_WF23TO20_ADDR(x), BP_LCD_WF23TO20_WF22, BS_LCD_WF23TO20_WF22))

/*! @brief Format value for bitfield LCD_WF23TO20_WF22. */
#define BF_LCD_WF23TO20_WF22(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF23TO20_WF22) & BM_LCD_WF23TO20_WF22)

/*! @brief Set the WF22 field to a new value. */
#define BW_LCD_WF23TO20_WF22(x, v) (BME_BFI32(HW_LCD_WF23TO20_ADDR(x), ((uint32_t)(v) << BP_LCD_WF23TO20_WF22), BP_LCD_WF23TO20_WF22, 8))
/*@}*/

/*!
 * @name Register LCD_WF23TO20, field WF23[31:24] (RW)
 *
 * Controls segments or phases connected to LCD_P23 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF23TO20_WF23 (24U)         /*!< Bit position for LCD_WF23TO20_WF23. */
#define BM_LCD_WF23TO20_WF23 (0xFF000000U) /*!< Bit mask for LCD_WF23TO20_WF23. */
#define BS_LCD_WF23TO20_WF23 (8U)          /*!< Bit field size in bits for LCD_WF23TO20_WF23. */

/*! @brief Read current value of the LCD_WF23TO20_WF23 field. */
#define BR_LCD_WF23TO20_WF23(x) (BME_UBFX32(HW_LCD_WF23TO20_ADDR(x), BP_LCD_WF23TO20_WF23, BS_LCD_WF23TO20_WF23))

/*! @brief Format value for bitfield LCD_WF23TO20_WF23. */
#define BF_LCD_WF23TO20_WF23(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF23TO20_WF23) & BM_LCD_WF23TO20_WF23)

/*! @brief Set the WF23 field to a new value. */
#define BW_LCD_WF23TO20_WF23(x, v) (BME_BFI32(HW_LCD_WF23TO20_ADDR(x), ((uint32_t)(v) << BP_LCD_WF23TO20_WF23), BP_LCD_WF23TO20_WF23, 8))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF27TO24 - LCD Waveform register
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF27TO24 - LCD Waveform register (RW)
 *
 * Reset value: 0x00000000U
 *
 * See the LCD Waveform register (WFC3TO0) for register and field descriptions.
 * The reset value of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_wf27to24
{
    uint32_t U;
    struct _hw_lcd_wf27to24_bitfields
    {
        uint32_t WF24 : 8;             /*!< [7:0]  */
        uint32_t WF25 : 8;             /*!< [15:8]  */
        uint32_t WF26 : 8;             /*!< [23:16]  */
        uint32_t WF27 : 8;             /*!< [31:24]  */
    } B;
} hw_lcd_wf27to24_t;

/*!
 * @name Constants and macros for entire LCD_WF27TO24 register
 */
/*@{*/
#define HW_LCD_WF27TO24_ADDR(x)  ((x) + 0x38U)

#define HW_LCD_WF27TO24(x)       (*(__IO hw_lcd_wf27to24_t *) HW_LCD_WF27TO24_ADDR(x))
#define HW_LCD_WF27TO24_RD(x)    (HW_LCD_WF27TO24(x).U)
#define HW_LCD_WF27TO24_WR(x, v) (HW_LCD_WF27TO24(x).U = (v))
#define HW_LCD_WF27TO24_SET(x, v) (BME_OR32(HW_LCD_WF27TO24_ADDR(x), (uint32_t)(v)))
#define HW_LCD_WF27TO24_CLR(x, v) (BME_AND32(HW_LCD_WF27TO24_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_WF27TO24_TOG(x, v) (BME_XOR32(HW_LCD_WF27TO24_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF27TO24 bitfields
 */

/*!
 * @name Register LCD_WF27TO24, field WF24[7:0] (RW)
 *
 * Controls segments or phases connected to LCD_P24 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF27TO24_WF24 (0U)          /*!< Bit position for LCD_WF27TO24_WF24. */
#define BM_LCD_WF27TO24_WF24 (0x000000FFU) /*!< Bit mask for LCD_WF27TO24_WF24. */
#define BS_LCD_WF27TO24_WF24 (8U)          /*!< Bit field size in bits for LCD_WF27TO24_WF24. */

/*! @brief Read current value of the LCD_WF27TO24_WF24 field. */
#define BR_LCD_WF27TO24_WF24(x) (BME_UBFX32(HW_LCD_WF27TO24_ADDR(x), BP_LCD_WF27TO24_WF24, BS_LCD_WF27TO24_WF24))

/*! @brief Format value for bitfield LCD_WF27TO24_WF24. */
#define BF_LCD_WF27TO24_WF24(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF27TO24_WF24) & BM_LCD_WF27TO24_WF24)

/*! @brief Set the WF24 field to a new value. */
#define BW_LCD_WF27TO24_WF24(x, v) (BME_BFI32(HW_LCD_WF27TO24_ADDR(x), ((uint32_t)(v) << BP_LCD_WF27TO24_WF24), BP_LCD_WF27TO24_WF24, 8))
/*@}*/

/*!
 * @name Register LCD_WF27TO24, field WF25[15:8] (RW)
 *
 * Controls segments or phases connected to LCD_P25 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF27TO24_WF25 (8U)          /*!< Bit position for LCD_WF27TO24_WF25. */
#define BM_LCD_WF27TO24_WF25 (0x0000FF00U) /*!< Bit mask for LCD_WF27TO24_WF25. */
#define BS_LCD_WF27TO24_WF25 (8U)          /*!< Bit field size in bits for LCD_WF27TO24_WF25. */

/*! @brief Read current value of the LCD_WF27TO24_WF25 field. */
#define BR_LCD_WF27TO24_WF25(x) (BME_UBFX32(HW_LCD_WF27TO24_ADDR(x), BP_LCD_WF27TO24_WF25, BS_LCD_WF27TO24_WF25))

/*! @brief Format value for bitfield LCD_WF27TO24_WF25. */
#define BF_LCD_WF27TO24_WF25(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF27TO24_WF25) & BM_LCD_WF27TO24_WF25)

/*! @brief Set the WF25 field to a new value. */
#define BW_LCD_WF27TO24_WF25(x, v) (BME_BFI32(HW_LCD_WF27TO24_ADDR(x), ((uint32_t)(v) << BP_LCD_WF27TO24_WF25), BP_LCD_WF27TO24_WF25, 8))
/*@}*/

/*!
 * @name Register LCD_WF27TO24, field WF26[23:16] (RW)
 *
 * Controls segments or phases connected to LCD_P26 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF27TO24_WF26 (16U)         /*!< Bit position for LCD_WF27TO24_WF26. */
#define BM_LCD_WF27TO24_WF26 (0x00FF0000U) /*!< Bit mask for LCD_WF27TO24_WF26. */
#define BS_LCD_WF27TO24_WF26 (8U)          /*!< Bit field size in bits for LCD_WF27TO24_WF26. */

/*! @brief Read current value of the LCD_WF27TO24_WF26 field. */
#define BR_LCD_WF27TO24_WF26(x) (BME_UBFX32(HW_LCD_WF27TO24_ADDR(x), BP_LCD_WF27TO24_WF26, BS_LCD_WF27TO24_WF26))

/*! @brief Format value for bitfield LCD_WF27TO24_WF26. */
#define BF_LCD_WF27TO24_WF26(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF27TO24_WF26) & BM_LCD_WF27TO24_WF26)

/*! @brief Set the WF26 field to a new value. */
#define BW_LCD_WF27TO24_WF26(x, v) (BME_BFI32(HW_LCD_WF27TO24_ADDR(x), ((uint32_t)(v) << BP_LCD_WF27TO24_WF26), BP_LCD_WF27TO24_WF26, 8))
/*@}*/

/*!
 * @name Register LCD_WF27TO24, field WF27[31:24] (RW)
 *
 * Controls segments or phases connected to LCD_P27 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF27TO24_WF27 (24U)         /*!< Bit position for LCD_WF27TO24_WF27. */
#define BM_LCD_WF27TO24_WF27 (0xFF000000U) /*!< Bit mask for LCD_WF27TO24_WF27. */
#define BS_LCD_WF27TO24_WF27 (8U)          /*!< Bit field size in bits for LCD_WF27TO24_WF27. */

/*! @brief Read current value of the LCD_WF27TO24_WF27 field. */
#define BR_LCD_WF27TO24_WF27(x) (BME_UBFX32(HW_LCD_WF27TO24_ADDR(x), BP_LCD_WF27TO24_WF27, BS_LCD_WF27TO24_WF27))

/*! @brief Format value for bitfield LCD_WF27TO24_WF27. */
#define BF_LCD_WF27TO24_WF27(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF27TO24_WF27) & BM_LCD_WF27TO24_WF27)

/*! @brief Set the WF27 field to a new value. */
#define BW_LCD_WF27TO24_WF27(x, v) (BME_BFI32(HW_LCD_WF27TO24_ADDR(x), ((uint32_t)(v) << BP_LCD_WF27TO24_WF27), BP_LCD_WF27TO24_WF27, 8))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF31TO28 - LCD Waveform register
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF31TO28 - LCD Waveform register (RW)
 *
 * Reset value: 0x00000000U
 *
 * See the LCD Waveform register (WFC3TO0) for register and field descriptions.
 * The reset value of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_wf31to28
{
    uint32_t U;
    struct _hw_lcd_wf31to28_bitfields
    {
        uint32_t WF28 : 8;             /*!< [7:0]  */
        uint32_t WF29 : 8;             /*!< [15:8]  */
        uint32_t WF30 : 8;             /*!< [23:16]  */
        uint32_t WF31 : 8;             /*!< [31:24]  */
    } B;
} hw_lcd_wf31to28_t;

/*!
 * @name Constants and macros for entire LCD_WF31TO28 register
 */
/*@{*/
#define HW_LCD_WF31TO28_ADDR(x)  ((x) + 0x3CU)

#define HW_LCD_WF31TO28(x)       (*(__IO hw_lcd_wf31to28_t *) HW_LCD_WF31TO28_ADDR(x))
#define HW_LCD_WF31TO28_RD(x)    (HW_LCD_WF31TO28(x).U)
#define HW_LCD_WF31TO28_WR(x, v) (HW_LCD_WF31TO28(x).U = (v))
#define HW_LCD_WF31TO28_SET(x, v) (BME_OR32(HW_LCD_WF31TO28_ADDR(x), (uint32_t)(v)))
#define HW_LCD_WF31TO28_CLR(x, v) (BME_AND32(HW_LCD_WF31TO28_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_WF31TO28_TOG(x, v) (BME_XOR32(HW_LCD_WF31TO28_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF31TO28 bitfields
 */

/*!
 * @name Register LCD_WF31TO28, field WF28[7:0] (RW)
 *
 * Controls segments or phases connected to LCD_P28 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF31TO28_WF28 (0U)          /*!< Bit position for LCD_WF31TO28_WF28. */
#define BM_LCD_WF31TO28_WF28 (0x000000FFU) /*!< Bit mask for LCD_WF31TO28_WF28. */
#define BS_LCD_WF31TO28_WF28 (8U)          /*!< Bit field size in bits for LCD_WF31TO28_WF28. */

/*! @brief Read current value of the LCD_WF31TO28_WF28 field. */
#define BR_LCD_WF31TO28_WF28(x) (BME_UBFX32(HW_LCD_WF31TO28_ADDR(x), BP_LCD_WF31TO28_WF28, BS_LCD_WF31TO28_WF28))

/*! @brief Format value for bitfield LCD_WF31TO28_WF28. */
#define BF_LCD_WF31TO28_WF28(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF31TO28_WF28) & BM_LCD_WF31TO28_WF28)

/*! @brief Set the WF28 field to a new value. */
#define BW_LCD_WF31TO28_WF28(x, v) (BME_BFI32(HW_LCD_WF31TO28_ADDR(x), ((uint32_t)(v) << BP_LCD_WF31TO28_WF28), BP_LCD_WF31TO28_WF28, 8))
/*@}*/

/*!
 * @name Register LCD_WF31TO28, field WF29[15:8] (RW)
 *
 * Controls segments or phases connected to LCD_P29 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF31TO28_WF29 (8U)          /*!< Bit position for LCD_WF31TO28_WF29. */
#define BM_LCD_WF31TO28_WF29 (0x0000FF00U) /*!< Bit mask for LCD_WF31TO28_WF29. */
#define BS_LCD_WF31TO28_WF29 (8U)          /*!< Bit field size in bits for LCD_WF31TO28_WF29. */

/*! @brief Read current value of the LCD_WF31TO28_WF29 field. */
#define BR_LCD_WF31TO28_WF29(x) (BME_UBFX32(HW_LCD_WF31TO28_ADDR(x), BP_LCD_WF31TO28_WF29, BS_LCD_WF31TO28_WF29))

/*! @brief Format value for bitfield LCD_WF31TO28_WF29. */
#define BF_LCD_WF31TO28_WF29(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF31TO28_WF29) & BM_LCD_WF31TO28_WF29)

/*! @brief Set the WF29 field to a new value. */
#define BW_LCD_WF31TO28_WF29(x, v) (BME_BFI32(HW_LCD_WF31TO28_ADDR(x), ((uint32_t)(v) << BP_LCD_WF31TO28_WF29), BP_LCD_WF31TO28_WF29, 8))
/*@}*/

/*!
 * @name Register LCD_WF31TO28, field WF30[23:16] (RW)
 *
 * Controls segments or phases connected to LCD_P30 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF31TO28_WF30 (16U)         /*!< Bit position for LCD_WF31TO28_WF30. */
#define BM_LCD_WF31TO28_WF30 (0x00FF0000U) /*!< Bit mask for LCD_WF31TO28_WF30. */
#define BS_LCD_WF31TO28_WF30 (8U)          /*!< Bit field size in bits for LCD_WF31TO28_WF30. */

/*! @brief Read current value of the LCD_WF31TO28_WF30 field. */
#define BR_LCD_WF31TO28_WF30(x) (BME_UBFX32(HW_LCD_WF31TO28_ADDR(x), BP_LCD_WF31TO28_WF30, BS_LCD_WF31TO28_WF30))

/*! @brief Format value for bitfield LCD_WF31TO28_WF30. */
#define BF_LCD_WF31TO28_WF30(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF31TO28_WF30) & BM_LCD_WF31TO28_WF30)

/*! @brief Set the WF30 field to a new value. */
#define BW_LCD_WF31TO28_WF30(x, v) (BME_BFI32(HW_LCD_WF31TO28_ADDR(x), ((uint32_t)(v) << BP_LCD_WF31TO28_WF30), BP_LCD_WF31TO28_WF30, 8))
/*@}*/

/*!
 * @name Register LCD_WF31TO28, field WF31[31:24] (RW)
 *
 * Controls segments or phases connected to LCD_P31 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF31TO28_WF31 (24U)         /*!< Bit position for LCD_WF31TO28_WF31. */
#define BM_LCD_WF31TO28_WF31 (0xFF000000U) /*!< Bit mask for LCD_WF31TO28_WF31. */
#define BS_LCD_WF31TO28_WF31 (8U)          /*!< Bit field size in bits for LCD_WF31TO28_WF31. */

/*! @brief Read current value of the LCD_WF31TO28_WF31 field. */
#define BR_LCD_WF31TO28_WF31(x) (BME_UBFX32(HW_LCD_WF31TO28_ADDR(x), BP_LCD_WF31TO28_WF31, BS_LCD_WF31TO28_WF31))

/*! @brief Format value for bitfield LCD_WF31TO28_WF31. */
#define BF_LCD_WF31TO28_WF31(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF31TO28_WF31) & BM_LCD_WF31TO28_WF31)

/*! @brief Set the WF31 field to a new value. */
#define BW_LCD_WF31TO28_WF31(x, v) (BME_BFI32(HW_LCD_WF31TO28_ADDR(x), ((uint32_t)(v) << BP_LCD_WF31TO28_WF31), BP_LCD_WF31TO28_WF31, 8))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF35TO32 - LCD Waveform register
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF35TO32 - LCD Waveform register (RW)
 *
 * Reset value: 0x00000000U
 *
 * See the LCD Waveform register (WFC3TO0) for register and field descriptions.
 * The reset value of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_wf35to32
{
    uint32_t U;
    struct _hw_lcd_wf35to32_bitfields
    {
        uint32_t WF32 : 8;             /*!< [7:0]  */
        uint32_t WF33 : 8;             /*!< [15:8]  */
        uint32_t WF34 : 8;             /*!< [23:16]  */
        uint32_t WF35 : 8;             /*!< [31:24]  */
    } B;
} hw_lcd_wf35to32_t;

/*!
 * @name Constants and macros for entire LCD_WF35TO32 register
 */
/*@{*/
#define HW_LCD_WF35TO32_ADDR(x)  ((x) + 0x40U)

#define HW_LCD_WF35TO32(x)       (*(__IO hw_lcd_wf35to32_t *) HW_LCD_WF35TO32_ADDR(x))
#define HW_LCD_WF35TO32_RD(x)    (HW_LCD_WF35TO32(x).U)
#define HW_LCD_WF35TO32_WR(x, v) (HW_LCD_WF35TO32(x).U = (v))
#define HW_LCD_WF35TO32_SET(x, v) (BME_OR32(HW_LCD_WF35TO32_ADDR(x), (uint32_t)(v)))
#define HW_LCD_WF35TO32_CLR(x, v) (BME_AND32(HW_LCD_WF35TO32_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_WF35TO32_TOG(x, v) (BME_XOR32(HW_LCD_WF35TO32_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF35TO32 bitfields
 */

/*!
 * @name Register LCD_WF35TO32, field WF32[7:0] (RW)
 *
 * Controls segments or phases connected to LCD_P32 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF35TO32_WF32 (0U)          /*!< Bit position for LCD_WF35TO32_WF32. */
#define BM_LCD_WF35TO32_WF32 (0x000000FFU) /*!< Bit mask for LCD_WF35TO32_WF32. */
#define BS_LCD_WF35TO32_WF32 (8U)          /*!< Bit field size in bits for LCD_WF35TO32_WF32. */

/*! @brief Read current value of the LCD_WF35TO32_WF32 field. */
#define BR_LCD_WF35TO32_WF32(x) (BME_UBFX32(HW_LCD_WF35TO32_ADDR(x), BP_LCD_WF35TO32_WF32, BS_LCD_WF35TO32_WF32))

/*! @brief Format value for bitfield LCD_WF35TO32_WF32. */
#define BF_LCD_WF35TO32_WF32(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF35TO32_WF32) & BM_LCD_WF35TO32_WF32)

/*! @brief Set the WF32 field to a new value. */
#define BW_LCD_WF35TO32_WF32(x, v) (BME_BFI32(HW_LCD_WF35TO32_ADDR(x), ((uint32_t)(v) << BP_LCD_WF35TO32_WF32), BP_LCD_WF35TO32_WF32, 8))
/*@}*/

/*!
 * @name Register LCD_WF35TO32, field WF33[15:8] (RW)
 *
 * Controls segments or phases connected to LCD_P33 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF35TO32_WF33 (8U)          /*!< Bit position for LCD_WF35TO32_WF33. */
#define BM_LCD_WF35TO32_WF33 (0x0000FF00U) /*!< Bit mask for LCD_WF35TO32_WF33. */
#define BS_LCD_WF35TO32_WF33 (8U)          /*!< Bit field size in bits for LCD_WF35TO32_WF33. */

/*! @brief Read current value of the LCD_WF35TO32_WF33 field. */
#define BR_LCD_WF35TO32_WF33(x) (BME_UBFX32(HW_LCD_WF35TO32_ADDR(x), BP_LCD_WF35TO32_WF33, BS_LCD_WF35TO32_WF33))

/*! @brief Format value for bitfield LCD_WF35TO32_WF33. */
#define BF_LCD_WF35TO32_WF33(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF35TO32_WF33) & BM_LCD_WF35TO32_WF33)

/*! @brief Set the WF33 field to a new value. */
#define BW_LCD_WF35TO32_WF33(x, v) (BME_BFI32(HW_LCD_WF35TO32_ADDR(x), ((uint32_t)(v) << BP_LCD_WF35TO32_WF33), BP_LCD_WF35TO32_WF33, 8))
/*@}*/

/*!
 * @name Register LCD_WF35TO32, field WF34[23:16] (RW)
 *
 * Controls segments or phases connected to LCD_P34 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF35TO32_WF34 (16U)         /*!< Bit position for LCD_WF35TO32_WF34. */
#define BM_LCD_WF35TO32_WF34 (0x00FF0000U) /*!< Bit mask for LCD_WF35TO32_WF34. */
#define BS_LCD_WF35TO32_WF34 (8U)          /*!< Bit field size in bits for LCD_WF35TO32_WF34. */

/*! @brief Read current value of the LCD_WF35TO32_WF34 field. */
#define BR_LCD_WF35TO32_WF34(x) (BME_UBFX32(HW_LCD_WF35TO32_ADDR(x), BP_LCD_WF35TO32_WF34, BS_LCD_WF35TO32_WF34))

/*! @brief Format value for bitfield LCD_WF35TO32_WF34. */
#define BF_LCD_WF35TO32_WF34(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF35TO32_WF34) & BM_LCD_WF35TO32_WF34)

/*! @brief Set the WF34 field to a new value. */
#define BW_LCD_WF35TO32_WF34(x, v) (BME_BFI32(HW_LCD_WF35TO32_ADDR(x), ((uint32_t)(v) << BP_LCD_WF35TO32_WF34), BP_LCD_WF35TO32_WF34, 8))
/*@}*/

/*!
 * @name Register LCD_WF35TO32, field WF35[31:24] (RW)
 *
 * Controls segments or phases connected to LCD_P35 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF35TO32_WF35 (24U)         /*!< Bit position for LCD_WF35TO32_WF35. */
#define BM_LCD_WF35TO32_WF35 (0xFF000000U) /*!< Bit mask for LCD_WF35TO32_WF35. */
#define BS_LCD_WF35TO32_WF35 (8U)          /*!< Bit field size in bits for LCD_WF35TO32_WF35. */

/*! @brief Read current value of the LCD_WF35TO32_WF35 field. */
#define BR_LCD_WF35TO32_WF35(x) (BME_UBFX32(HW_LCD_WF35TO32_ADDR(x), BP_LCD_WF35TO32_WF35, BS_LCD_WF35TO32_WF35))

/*! @brief Format value for bitfield LCD_WF35TO32_WF35. */
#define BF_LCD_WF35TO32_WF35(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF35TO32_WF35) & BM_LCD_WF35TO32_WF35)

/*! @brief Set the WF35 field to a new value. */
#define BW_LCD_WF35TO32_WF35(x, v) (BME_BFI32(HW_LCD_WF35TO32_ADDR(x), ((uint32_t)(v) << BP_LCD_WF35TO32_WF35), BP_LCD_WF35TO32_WF35, 8))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF39TO36 - LCD Waveform register
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF39TO36 - LCD Waveform register (RW)
 *
 * Reset value: 0x00000000U
 *
 * See the LCD Waveform register (WFC3TO0) for register and field descriptions.
 * The reset value of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_wf39to36
{
    uint32_t U;
    struct _hw_lcd_wf39to36_bitfields
    {
        uint32_t WF36 : 8;             /*!< [7:0]  */
        uint32_t WF37 : 8;             /*!< [15:8]  */
        uint32_t WF38 : 8;             /*!< [23:16]  */
        uint32_t WF39 : 8;             /*!< [31:24]  */
    } B;
} hw_lcd_wf39to36_t;

/*!
 * @name Constants and macros for entire LCD_WF39TO36 register
 */
/*@{*/
#define HW_LCD_WF39TO36_ADDR(x)  ((x) + 0x44U)

#define HW_LCD_WF39TO36(x)       (*(__IO hw_lcd_wf39to36_t *) HW_LCD_WF39TO36_ADDR(x))
#define HW_LCD_WF39TO36_RD(x)    (HW_LCD_WF39TO36(x).U)
#define HW_LCD_WF39TO36_WR(x, v) (HW_LCD_WF39TO36(x).U = (v))
#define HW_LCD_WF39TO36_SET(x, v) (BME_OR32(HW_LCD_WF39TO36_ADDR(x), (uint32_t)(v)))
#define HW_LCD_WF39TO36_CLR(x, v) (BME_AND32(HW_LCD_WF39TO36_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_WF39TO36_TOG(x, v) (BME_XOR32(HW_LCD_WF39TO36_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF39TO36 bitfields
 */

/*!
 * @name Register LCD_WF39TO36, field WF36[7:0] (RW)
 *
 * Controls segments or phases connected to LCD_P36 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF39TO36_WF36 (0U)          /*!< Bit position for LCD_WF39TO36_WF36. */
#define BM_LCD_WF39TO36_WF36 (0x000000FFU) /*!< Bit mask for LCD_WF39TO36_WF36. */
#define BS_LCD_WF39TO36_WF36 (8U)          /*!< Bit field size in bits for LCD_WF39TO36_WF36. */

/*! @brief Read current value of the LCD_WF39TO36_WF36 field. */
#define BR_LCD_WF39TO36_WF36(x) (BME_UBFX32(HW_LCD_WF39TO36_ADDR(x), BP_LCD_WF39TO36_WF36, BS_LCD_WF39TO36_WF36))

/*! @brief Format value for bitfield LCD_WF39TO36_WF36. */
#define BF_LCD_WF39TO36_WF36(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF39TO36_WF36) & BM_LCD_WF39TO36_WF36)

/*! @brief Set the WF36 field to a new value. */
#define BW_LCD_WF39TO36_WF36(x, v) (BME_BFI32(HW_LCD_WF39TO36_ADDR(x), ((uint32_t)(v) << BP_LCD_WF39TO36_WF36), BP_LCD_WF39TO36_WF36, 8))
/*@}*/

/*!
 * @name Register LCD_WF39TO36, field WF37[15:8] (RW)
 *
 * Controls segments or phases connected to LCD_P37 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF39TO36_WF37 (8U)          /*!< Bit position for LCD_WF39TO36_WF37. */
#define BM_LCD_WF39TO36_WF37 (0x0000FF00U) /*!< Bit mask for LCD_WF39TO36_WF37. */
#define BS_LCD_WF39TO36_WF37 (8U)          /*!< Bit field size in bits for LCD_WF39TO36_WF37. */

/*! @brief Read current value of the LCD_WF39TO36_WF37 field. */
#define BR_LCD_WF39TO36_WF37(x) (BME_UBFX32(HW_LCD_WF39TO36_ADDR(x), BP_LCD_WF39TO36_WF37, BS_LCD_WF39TO36_WF37))

/*! @brief Format value for bitfield LCD_WF39TO36_WF37. */
#define BF_LCD_WF39TO36_WF37(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF39TO36_WF37) & BM_LCD_WF39TO36_WF37)

/*! @brief Set the WF37 field to a new value. */
#define BW_LCD_WF39TO36_WF37(x, v) (BME_BFI32(HW_LCD_WF39TO36_ADDR(x), ((uint32_t)(v) << BP_LCD_WF39TO36_WF37), BP_LCD_WF39TO36_WF37, 8))
/*@}*/

/*!
 * @name Register LCD_WF39TO36, field WF38[23:16] (RW)
 *
 * Controls segments or phases connected to LCD_P38 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF39TO36_WF38 (16U)         /*!< Bit position for LCD_WF39TO36_WF38. */
#define BM_LCD_WF39TO36_WF38 (0x00FF0000U) /*!< Bit mask for LCD_WF39TO36_WF38. */
#define BS_LCD_WF39TO36_WF38 (8U)          /*!< Bit field size in bits for LCD_WF39TO36_WF38. */

/*! @brief Read current value of the LCD_WF39TO36_WF38 field. */
#define BR_LCD_WF39TO36_WF38(x) (BME_UBFX32(HW_LCD_WF39TO36_ADDR(x), BP_LCD_WF39TO36_WF38, BS_LCD_WF39TO36_WF38))

/*! @brief Format value for bitfield LCD_WF39TO36_WF38. */
#define BF_LCD_WF39TO36_WF38(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF39TO36_WF38) & BM_LCD_WF39TO36_WF38)

/*! @brief Set the WF38 field to a new value. */
#define BW_LCD_WF39TO36_WF38(x, v) (BME_BFI32(HW_LCD_WF39TO36_ADDR(x), ((uint32_t)(v) << BP_LCD_WF39TO36_WF38), BP_LCD_WF39TO36_WF38, 8))
/*@}*/

/*!
 * @name Register LCD_WF39TO36, field WF39[31:24] (RW)
 *
 * Controls segments or phases connected to LCD_P39 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF39TO36_WF39 (24U)         /*!< Bit position for LCD_WF39TO36_WF39. */
#define BM_LCD_WF39TO36_WF39 (0xFF000000U) /*!< Bit mask for LCD_WF39TO36_WF39. */
#define BS_LCD_WF39TO36_WF39 (8U)          /*!< Bit field size in bits for LCD_WF39TO36_WF39. */

/*! @brief Read current value of the LCD_WF39TO36_WF39 field. */
#define BR_LCD_WF39TO36_WF39(x) (BME_UBFX32(HW_LCD_WF39TO36_ADDR(x), BP_LCD_WF39TO36_WF39, BS_LCD_WF39TO36_WF39))

/*! @brief Format value for bitfield LCD_WF39TO36_WF39. */
#define BF_LCD_WF39TO36_WF39(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF39TO36_WF39) & BM_LCD_WF39TO36_WF39)

/*! @brief Set the WF39 field to a new value. */
#define BW_LCD_WF39TO36_WF39(x, v) (BME_BFI32(HW_LCD_WF39TO36_ADDR(x), ((uint32_t)(v) << BP_LCD_WF39TO36_WF39), BP_LCD_WF39TO36_WF39, 8))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF43TO40 - LCD Waveform register
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF43TO40 - LCD Waveform register (RW)
 *
 * Reset value: 0x00000000U
 *
 * See the LCD Waveform register (WFC3TO0) for register and field descriptions.
 * The reset value of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_wf43to40
{
    uint32_t U;
    struct _hw_lcd_wf43to40_bitfields
    {
        uint32_t WF40 : 8;             /*!< [7:0]  */
        uint32_t WF41 : 8;             /*!< [15:8]  */
        uint32_t WF42 : 8;             /*!< [23:16]  */
        uint32_t WF43 : 8;             /*!< [31:24]  */
    } B;
} hw_lcd_wf43to40_t;

/*!
 * @name Constants and macros for entire LCD_WF43TO40 register
 */
/*@{*/
#define HW_LCD_WF43TO40_ADDR(x)  ((x) + 0x48U)

#define HW_LCD_WF43TO40(x)       (*(__IO hw_lcd_wf43to40_t *) HW_LCD_WF43TO40_ADDR(x))
#define HW_LCD_WF43TO40_RD(x)    (HW_LCD_WF43TO40(x).U)
#define HW_LCD_WF43TO40_WR(x, v) (HW_LCD_WF43TO40(x).U = (v))
#define HW_LCD_WF43TO40_SET(x, v) (BME_OR32(HW_LCD_WF43TO40_ADDR(x), (uint32_t)(v)))
#define HW_LCD_WF43TO40_CLR(x, v) (BME_AND32(HW_LCD_WF43TO40_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_WF43TO40_TOG(x, v) (BME_XOR32(HW_LCD_WF43TO40_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF43TO40 bitfields
 */

/*!
 * @name Register LCD_WF43TO40, field WF40[7:0] (RW)
 *
 * Controls segments or phases connected to LCD_P40 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF43TO40_WF40 (0U)          /*!< Bit position for LCD_WF43TO40_WF40. */
#define BM_LCD_WF43TO40_WF40 (0x000000FFU) /*!< Bit mask for LCD_WF43TO40_WF40. */
#define BS_LCD_WF43TO40_WF40 (8U)          /*!< Bit field size in bits for LCD_WF43TO40_WF40. */

/*! @brief Read current value of the LCD_WF43TO40_WF40 field. */
#define BR_LCD_WF43TO40_WF40(x) (BME_UBFX32(HW_LCD_WF43TO40_ADDR(x), BP_LCD_WF43TO40_WF40, BS_LCD_WF43TO40_WF40))

/*! @brief Format value for bitfield LCD_WF43TO40_WF40. */
#define BF_LCD_WF43TO40_WF40(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF43TO40_WF40) & BM_LCD_WF43TO40_WF40)

/*! @brief Set the WF40 field to a new value. */
#define BW_LCD_WF43TO40_WF40(x, v) (BME_BFI32(HW_LCD_WF43TO40_ADDR(x), ((uint32_t)(v) << BP_LCD_WF43TO40_WF40), BP_LCD_WF43TO40_WF40, 8))
/*@}*/

/*!
 * @name Register LCD_WF43TO40, field WF41[15:8] (RW)
 *
 * Controls segments or phases connected to LCD_P41 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF43TO40_WF41 (8U)          /*!< Bit position for LCD_WF43TO40_WF41. */
#define BM_LCD_WF43TO40_WF41 (0x0000FF00U) /*!< Bit mask for LCD_WF43TO40_WF41. */
#define BS_LCD_WF43TO40_WF41 (8U)          /*!< Bit field size in bits for LCD_WF43TO40_WF41. */

/*! @brief Read current value of the LCD_WF43TO40_WF41 field. */
#define BR_LCD_WF43TO40_WF41(x) (BME_UBFX32(HW_LCD_WF43TO40_ADDR(x), BP_LCD_WF43TO40_WF41, BS_LCD_WF43TO40_WF41))

/*! @brief Format value for bitfield LCD_WF43TO40_WF41. */
#define BF_LCD_WF43TO40_WF41(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF43TO40_WF41) & BM_LCD_WF43TO40_WF41)

/*! @brief Set the WF41 field to a new value. */
#define BW_LCD_WF43TO40_WF41(x, v) (BME_BFI32(HW_LCD_WF43TO40_ADDR(x), ((uint32_t)(v) << BP_LCD_WF43TO40_WF41), BP_LCD_WF43TO40_WF41, 8))
/*@}*/

/*!
 * @name Register LCD_WF43TO40, field WF42[23:16] (RW)
 *
 * Controls segments or phases connected to LCD_P42 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF43TO40_WF42 (16U)         /*!< Bit position for LCD_WF43TO40_WF42. */
#define BM_LCD_WF43TO40_WF42 (0x00FF0000U) /*!< Bit mask for LCD_WF43TO40_WF42. */
#define BS_LCD_WF43TO40_WF42 (8U)          /*!< Bit field size in bits for LCD_WF43TO40_WF42. */

/*! @brief Read current value of the LCD_WF43TO40_WF42 field. */
#define BR_LCD_WF43TO40_WF42(x) (BME_UBFX32(HW_LCD_WF43TO40_ADDR(x), BP_LCD_WF43TO40_WF42, BS_LCD_WF43TO40_WF42))

/*! @brief Format value for bitfield LCD_WF43TO40_WF42. */
#define BF_LCD_WF43TO40_WF42(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF43TO40_WF42) & BM_LCD_WF43TO40_WF42)

/*! @brief Set the WF42 field to a new value. */
#define BW_LCD_WF43TO40_WF42(x, v) (BME_BFI32(HW_LCD_WF43TO40_ADDR(x), ((uint32_t)(v) << BP_LCD_WF43TO40_WF42), BP_LCD_WF43TO40_WF42, 8))
/*@}*/

/*!
 * @name Register LCD_WF43TO40, field WF43[31:24] (RW)
 *
 * Controls segments or phases connected to LCD_P43 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF43TO40_WF43 (24U)         /*!< Bit position for LCD_WF43TO40_WF43. */
#define BM_LCD_WF43TO40_WF43 (0xFF000000U) /*!< Bit mask for LCD_WF43TO40_WF43. */
#define BS_LCD_WF43TO40_WF43 (8U)          /*!< Bit field size in bits for LCD_WF43TO40_WF43. */

/*! @brief Read current value of the LCD_WF43TO40_WF43 field. */
#define BR_LCD_WF43TO40_WF43(x) (BME_UBFX32(HW_LCD_WF43TO40_ADDR(x), BP_LCD_WF43TO40_WF43, BS_LCD_WF43TO40_WF43))

/*! @brief Format value for bitfield LCD_WF43TO40_WF43. */
#define BF_LCD_WF43TO40_WF43(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF43TO40_WF43) & BM_LCD_WF43TO40_WF43)

/*! @brief Set the WF43 field to a new value. */
#define BW_LCD_WF43TO40_WF43(x, v) (BME_BFI32(HW_LCD_WF43TO40_ADDR(x), ((uint32_t)(v) << BP_LCD_WF43TO40_WF43), BP_LCD_WF43TO40_WF43, 8))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF47TO44 - LCD Waveform register
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF47TO44 - LCD Waveform register (RW)
 *
 * Reset value: 0x00000000U
 *
 * See the LCD Waveform register (WFC3TO0) for register and field descriptions.
 * The reset value of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_wf47to44
{
    uint32_t U;
    struct _hw_lcd_wf47to44_bitfields
    {
        uint32_t WF44 : 8;             /*!< [7:0]  */
        uint32_t WF45 : 8;             /*!< [15:8]  */
        uint32_t WF46 : 8;             /*!< [23:16]  */
        uint32_t WF47 : 8;             /*!< [31:24]  */
    } B;
} hw_lcd_wf47to44_t;

/*!
 * @name Constants and macros for entire LCD_WF47TO44 register
 */
/*@{*/
#define HW_LCD_WF47TO44_ADDR(x)  ((x) + 0x4CU)

#define HW_LCD_WF47TO44(x)       (*(__IO hw_lcd_wf47to44_t *) HW_LCD_WF47TO44_ADDR(x))
#define HW_LCD_WF47TO44_RD(x)    (HW_LCD_WF47TO44(x).U)
#define HW_LCD_WF47TO44_WR(x, v) (HW_LCD_WF47TO44(x).U = (v))
#define HW_LCD_WF47TO44_SET(x, v) (BME_OR32(HW_LCD_WF47TO44_ADDR(x), (uint32_t)(v)))
#define HW_LCD_WF47TO44_CLR(x, v) (BME_AND32(HW_LCD_WF47TO44_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_WF47TO44_TOG(x, v) (BME_XOR32(HW_LCD_WF47TO44_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF47TO44 bitfields
 */

/*!
 * @name Register LCD_WF47TO44, field WF44[7:0] (RW)
 *
 * Controls segments or phases connected to LCD_P44 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF47TO44_WF44 (0U)          /*!< Bit position for LCD_WF47TO44_WF44. */
#define BM_LCD_WF47TO44_WF44 (0x000000FFU) /*!< Bit mask for LCD_WF47TO44_WF44. */
#define BS_LCD_WF47TO44_WF44 (8U)          /*!< Bit field size in bits for LCD_WF47TO44_WF44. */

/*! @brief Read current value of the LCD_WF47TO44_WF44 field. */
#define BR_LCD_WF47TO44_WF44(x) (BME_UBFX32(HW_LCD_WF47TO44_ADDR(x), BP_LCD_WF47TO44_WF44, BS_LCD_WF47TO44_WF44))

/*! @brief Format value for bitfield LCD_WF47TO44_WF44. */
#define BF_LCD_WF47TO44_WF44(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF47TO44_WF44) & BM_LCD_WF47TO44_WF44)

/*! @brief Set the WF44 field to a new value. */
#define BW_LCD_WF47TO44_WF44(x, v) (BME_BFI32(HW_LCD_WF47TO44_ADDR(x), ((uint32_t)(v) << BP_LCD_WF47TO44_WF44), BP_LCD_WF47TO44_WF44, 8))
/*@}*/

/*!
 * @name Register LCD_WF47TO44, field WF45[15:8] (RW)
 *
 * Controls segments or phases connected to LCD_P45 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF47TO44_WF45 (8U)          /*!< Bit position for LCD_WF47TO44_WF45. */
#define BM_LCD_WF47TO44_WF45 (0x0000FF00U) /*!< Bit mask for LCD_WF47TO44_WF45. */
#define BS_LCD_WF47TO44_WF45 (8U)          /*!< Bit field size in bits for LCD_WF47TO44_WF45. */

/*! @brief Read current value of the LCD_WF47TO44_WF45 field. */
#define BR_LCD_WF47TO44_WF45(x) (BME_UBFX32(HW_LCD_WF47TO44_ADDR(x), BP_LCD_WF47TO44_WF45, BS_LCD_WF47TO44_WF45))

/*! @brief Format value for bitfield LCD_WF47TO44_WF45. */
#define BF_LCD_WF47TO44_WF45(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF47TO44_WF45) & BM_LCD_WF47TO44_WF45)

/*! @brief Set the WF45 field to a new value. */
#define BW_LCD_WF47TO44_WF45(x, v) (BME_BFI32(HW_LCD_WF47TO44_ADDR(x), ((uint32_t)(v) << BP_LCD_WF47TO44_WF45), BP_LCD_WF47TO44_WF45, 8))
/*@}*/

/*!
 * @name Register LCD_WF47TO44, field WF46[23:16] (RW)
 *
 * Controls segments or phases connected to LCD_P46 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF47TO44_WF46 (16U)         /*!< Bit position for LCD_WF47TO44_WF46. */
#define BM_LCD_WF47TO44_WF46 (0x00FF0000U) /*!< Bit mask for LCD_WF47TO44_WF46. */
#define BS_LCD_WF47TO44_WF46 (8U)          /*!< Bit field size in bits for LCD_WF47TO44_WF46. */

/*! @brief Read current value of the LCD_WF47TO44_WF46 field. */
#define BR_LCD_WF47TO44_WF46(x) (BME_UBFX32(HW_LCD_WF47TO44_ADDR(x), BP_LCD_WF47TO44_WF46, BS_LCD_WF47TO44_WF46))

/*! @brief Format value for bitfield LCD_WF47TO44_WF46. */
#define BF_LCD_WF47TO44_WF46(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF47TO44_WF46) & BM_LCD_WF47TO44_WF46)

/*! @brief Set the WF46 field to a new value. */
#define BW_LCD_WF47TO44_WF46(x, v) (BME_BFI32(HW_LCD_WF47TO44_ADDR(x), ((uint32_t)(v) << BP_LCD_WF47TO44_WF46), BP_LCD_WF47TO44_WF46, 8))
/*@}*/

/*!
 * @name Register LCD_WF47TO44, field WF47[31:24] (RW)
 *
 * Controls segments or phases connected to LCD_P47 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF47TO44_WF47 (24U)         /*!< Bit position for LCD_WF47TO44_WF47. */
#define BM_LCD_WF47TO44_WF47 (0xFF000000U) /*!< Bit mask for LCD_WF47TO44_WF47. */
#define BS_LCD_WF47TO44_WF47 (8U)          /*!< Bit field size in bits for LCD_WF47TO44_WF47. */

/*! @brief Read current value of the LCD_WF47TO44_WF47 field. */
#define BR_LCD_WF47TO44_WF47(x) (BME_UBFX32(HW_LCD_WF47TO44_ADDR(x), BP_LCD_WF47TO44_WF47, BS_LCD_WF47TO44_WF47))

/*! @brief Format value for bitfield LCD_WF47TO44_WF47. */
#define BF_LCD_WF47TO44_WF47(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF47TO44_WF47) & BM_LCD_WF47TO44_WF47)

/*! @brief Set the WF47 field to a new value. */
#define BW_LCD_WF47TO44_WF47(x, v) (BME_BFI32(HW_LCD_WF47TO44_ADDR(x), ((uint32_t)(v) << BP_LCD_WF47TO44_WF47), BP_LCD_WF47TO44_WF47, 8))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF51TO48 - LCD Waveform register
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF51TO48 - LCD Waveform register (RW)
 *
 * Reset value: 0x00000000U
 *
 * See the LCD Waveform register (WFC3TO0) for register and field descriptions.
 * The reset value of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_wf51to48
{
    uint32_t U;
    struct _hw_lcd_wf51to48_bitfields
    {
        uint32_t WF48 : 8;             /*!< [7:0]  */
        uint32_t WF49 : 8;             /*!< [15:8]  */
        uint32_t WF50 : 8;             /*!< [23:16]  */
        uint32_t WF51 : 8;             /*!< [31:24]  */
    } B;
} hw_lcd_wf51to48_t;

/*!
 * @name Constants and macros for entire LCD_WF51TO48 register
 */
/*@{*/
#define HW_LCD_WF51TO48_ADDR(x)  ((x) + 0x50U)

#define HW_LCD_WF51TO48(x)       (*(__IO hw_lcd_wf51to48_t *) HW_LCD_WF51TO48_ADDR(x))
#define HW_LCD_WF51TO48_RD(x)    (HW_LCD_WF51TO48(x).U)
#define HW_LCD_WF51TO48_WR(x, v) (HW_LCD_WF51TO48(x).U = (v))
#define HW_LCD_WF51TO48_SET(x, v) (BME_OR32(HW_LCD_WF51TO48_ADDR(x), (uint32_t)(v)))
#define HW_LCD_WF51TO48_CLR(x, v) (BME_AND32(HW_LCD_WF51TO48_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_WF51TO48_TOG(x, v) (BME_XOR32(HW_LCD_WF51TO48_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF51TO48 bitfields
 */

/*!
 * @name Register LCD_WF51TO48, field WF48[7:0] (RW)
 *
 * Controls segments or phases connected to LCD_P48 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF51TO48_WF48 (0U)          /*!< Bit position for LCD_WF51TO48_WF48. */
#define BM_LCD_WF51TO48_WF48 (0x000000FFU) /*!< Bit mask for LCD_WF51TO48_WF48. */
#define BS_LCD_WF51TO48_WF48 (8U)          /*!< Bit field size in bits for LCD_WF51TO48_WF48. */

/*! @brief Read current value of the LCD_WF51TO48_WF48 field. */
#define BR_LCD_WF51TO48_WF48(x) (BME_UBFX32(HW_LCD_WF51TO48_ADDR(x), BP_LCD_WF51TO48_WF48, BS_LCD_WF51TO48_WF48))

/*! @brief Format value for bitfield LCD_WF51TO48_WF48. */
#define BF_LCD_WF51TO48_WF48(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF51TO48_WF48) & BM_LCD_WF51TO48_WF48)

/*! @brief Set the WF48 field to a new value. */
#define BW_LCD_WF51TO48_WF48(x, v) (BME_BFI32(HW_LCD_WF51TO48_ADDR(x), ((uint32_t)(v) << BP_LCD_WF51TO48_WF48), BP_LCD_WF51TO48_WF48, 8))
/*@}*/

/*!
 * @name Register LCD_WF51TO48, field WF49[15:8] (RW)
 *
 * Controls segments or phases connected to LCD_P49 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF51TO48_WF49 (8U)          /*!< Bit position for LCD_WF51TO48_WF49. */
#define BM_LCD_WF51TO48_WF49 (0x0000FF00U) /*!< Bit mask for LCD_WF51TO48_WF49. */
#define BS_LCD_WF51TO48_WF49 (8U)          /*!< Bit field size in bits for LCD_WF51TO48_WF49. */

/*! @brief Read current value of the LCD_WF51TO48_WF49 field. */
#define BR_LCD_WF51TO48_WF49(x) (BME_UBFX32(HW_LCD_WF51TO48_ADDR(x), BP_LCD_WF51TO48_WF49, BS_LCD_WF51TO48_WF49))

/*! @brief Format value for bitfield LCD_WF51TO48_WF49. */
#define BF_LCD_WF51TO48_WF49(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF51TO48_WF49) & BM_LCD_WF51TO48_WF49)

/*! @brief Set the WF49 field to a new value. */
#define BW_LCD_WF51TO48_WF49(x, v) (BME_BFI32(HW_LCD_WF51TO48_ADDR(x), ((uint32_t)(v) << BP_LCD_WF51TO48_WF49), BP_LCD_WF51TO48_WF49, 8))
/*@}*/

/*!
 * @name Register LCD_WF51TO48, field WF50[23:16] (RW)
 *
 * Controls segments or phases connected to LCD_P50 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF51TO48_WF50 (16U)         /*!< Bit position for LCD_WF51TO48_WF50. */
#define BM_LCD_WF51TO48_WF50 (0x00FF0000U) /*!< Bit mask for LCD_WF51TO48_WF50. */
#define BS_LCD_WF51TO48_WF50 (8U)          /*!< Bit field size in bits for LCD_WF51TO48_WF50. */

/*! @brief Read current value of the LCD_WF51TO48_WF50 field. */
#define BR_LCD_WF51TO48_WF50(x) (BME_UBFX32(HW_LCD_WF51TO48_ADDR(x), BP_LCD_WF51TO48_WF50, BS_LCD_WF51TO48_WF50))

/*! @brief Format value for bitfield LCD_WF51TO48_WF50. */
#define BF_LCD_WF51TO48_WF50(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF51TO48_WF50) & BM_LCD_WF51TO48_WF50)

/*! @brief Set the WF50 field to a new value. */
#define BW_LCD_WF51TO48_WF50(x, v) (BME_BFI32(HW_LCD_WF51TO48_ADDR(x), ((uint32_t)(v) << BP_LCD_WF51TO48_WF50), BP_LCD_WF51TO48_WF50, 8))
/*@}*/

/*!
 * @name Register LCD_WF51TO48, field WF51[31:24] (RW)
 *
 * Controls segments or phases connected to LCD_P51 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF51TO48_WF51 (24U)         /*!< Bit position for LCD_WF51TO48_WF51. */
#define BM_LCD_WF51TO48_WF51 (0xFF000000U) /*!< Bit mask for LCD_WF51TO48_WF51. */
#define BS_LCD_WF51TO48_WF51 (8U)          /*!< Bit field size in bits for LCD_WF51TO48_WF51. */

/*! @brief Read current value of the LCD_WF51TO48_WF51 field. */
#define BR_LCD_WF51TO48_WF51(x) (BME_UBFX32(HW_LCD_WF51TO48_ADDR(x), BP_LCD_WF51TO48_WF51, BS_LCD_WF51TO48_WF51))

/*! @brief Format value for bitfield LCD_WF51TO48_WF51. */
#define BF_LCD_WF51TO48_WF51(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF51TO48_WF51) & BM_LCD_WF51TO48_WF51)

/*! @brief Set the WF51 field to a new value. */
#define BW_LCD_WF51TO48_WF51(x, v) (BME_BFI32(HW_LCD_WF51TO48_ADDR(x), ((uint32_t)(v) << BP_LCD_WF51TO48_WF51), BP_LCD_WF51TO48_WF51, 8))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF55TO52 - LCD Waveform register
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF55TO52 - LCD Waveform register (RW)
 *
 * Reset value: 0x00000000U
 *
 * See the LCD Waveform register (WFC3TO0) for register and field descriptions.
 * The reset value of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_wf55to52
{
    uint32_t U;
    struct _hw_lcd_wf55to52_bitfields
    {
        uint32_t WF52 : 8;             /*!< [7:0]  */
        uint32_t WF53 : 8;             /*!< [15:8]  */
        uint32_t WF54 : 8;             /*!< [23:16]  */
        uint32_t WF55 : 8;             /*!< [31:24]  */
    } B;
} hw_lcd_wf55to52_t;

/*!
 * @name Constants and macros for entire LCD_WF55TO52 register
 */
/*@{*/
#define HW_LCD_WF55TO52_ADDR(x)  ((x) + 0x54U)

#define HW_LCD_WF55TO52(x)       (*(__IO hw_lcd_wf55to52_t *) HW_LCD_WF55TO52_ADDR(x))
#define HW_LCD_WF55TO52_RD(x)    (HW_LCD_WF55TO52(x).U)
#define HW_LCD_WF55TO52_WR(x, v) (HW_LCD_WF55TO52(x).U = (v))
#define HW_LCD_WF55TO52_SET(x, v) (BME_OR32(HW_LCD_WF55TO52_ADDR(x), (uint32_t)(v)))
#define HW_LCD_WF55TO52_CLR(x, v) (BME_AND32(HW_LCD_WF55TO52_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_WF55TO52_TOG(x, v) (BME_XOR32(HW_LCD_WF55TO52_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF55TO52 bitfields
 */

/*!
 * @name Register LCD_WF55TO52, field WF52[7:0] (RW)
 *
 * Controls segments or phases connected to LCD_P52 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF55TO52_WF52 (0U)          /*!< Bit position for LCD_WF55TO52_WF52. */
#define BM_LCD_WF55TO52_WF52 (0x000000FFU) /*!< Bit mask for LCD_WF55TO52_WF52. */
#define BS_LCD_WF55TO52_WF52 (8U)          /*!< Bit field size in bits for LCD_WF55TO52_WF52. */

/*! @brief Read current value of the LCD_WF55TO52_WF52 field. */
#define BR_LCD_WF55TO52_WF52(x) (BME_UBFX32(HW_LCD_WF55TO52_ADDR(x), BP_LCD_WF55TO52_WF52, BS_LCD_WF55TO52_WF52))

/*! @brief Format value for bitfield LCD_WF55TO52_WF52. */
#define BF_LCD_WF55TO52_WF52(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF55TO52_WF52) & BM_LCD_WF55TO52_WF52)

/*! @brief Set the WF52 field to a new value. */
#define BW_LCD_WF55TO52_WF52(x, v) (BME_BFI32(HW_LCD_WF55TO52_ADDR(x), ((uint32_t)(v) << BP_LCD_WF55TO52_WF52), BP_LCD_WF55TO52_WF52, 8))
/*@}*/

/*!
 * @name Register LCD_WF55TO52, field WF53[15:8] (RW)
 *
 * Controls segments or phases connected to LCD_P53 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF55TO52_WF53 (8U)          /*!< Bit position for LCD_WF55TO52_WF53. */
#define BM_LCD_WF55TO52_WF53 (0x0000FF00U) /*!< Bit mask for LCD_WF55TO52_WF53. */
#define BS_LCD_WF55TO52_WF53 (8U)          /*!< Bit field size in bits for LCD_WF55TO52_WF53. */

/*! @brief Read current value of the LCD_WF55TO52_WF53 field. */
#define BR_LCD_WF55TO52_WF53(x) (BME_UBFX32(HW_LCD_WF55TO52_ADDR(x), BP_LCD_WF55TO52_WF53, BS_LCD_WF55TO52_WF53))

/*! @brief Format value for bitfield LCD_WF55TO52_WF53. */
#define BF_LCD_WF55TO52_WF53(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF55TO52_WF53) & BM_LCD_WF55TO52_WF53)

/*! @brief Set the WF53 field to a new value. */
#define BW_LCD_WF55TO52_WF53(x, v) (BME_BFI32(HW_LCD_WF55TO52_ADDR(x), ((uint32_t)(v) << BP_LCD_WF55TO52_WF53), BP_LCD_WF55TO52_WF53, 8))
/*@}*/

/*!
 * @name Register LCD_WF55TO52, field WF54[23:16] (RW)
 *
 * Controls segments or phases connected to LCD_P54 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF55TO52_WF54 (16U)         /*!< Bit position for LCD_WF55TO52_WF54. */
#define BM_LCD_WF55TO52_WF54 (0x00FF0000U) /*!< Bit mask for LCD_WF55TO52_WF54. */
#define BS_LCD_WF55TO52_WF54 (8U)          /*!< Bit field size in bits for LCD_WF55TO52_WF54. */

/*! @brief Read current value of the LCD_WF55TO52_WF54 field. */
#define BR_LCD_WF55TO52_WF54(x) (BME_UBFX32(HW_LCD_WF55TO52_ADDR(x), BP_LCD_WF55TO52_WF54, BS_LCD_WF55TO52_WF54))

/*! @brief Format value for bitfield LCD_WF55TO52_WF54. */
#define BF_LCD_WF55TO52_WF54(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF55TO52_WF54) & BM_LCD_WF55TO52_WF54)

/*! @brief Set the WF54 field to a new value. */
#define BW_LCD_WF55TO52_WF54(x, v) (BME_BFI32(HW_LCD_WF55TO52_ADDR(x), ((uint32_t)(v) << BP_LCD_WF55TO52_WF54), BP_LCD_WF55TO52_WF54, 8))
/*@}*/

/*!
 * @name Register LCD_WF55TO52, field WF55[31:24] (RW)
 *
 * Controls segments or phases connected to LCD_P55 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF55TO52_WF55 (24U)         /*!< Bit position for LCD_WF55TO52_WF55. */
#define BM_LCD_WF55TO52_WF55 (0xFF000000U) /*!< Bit mask for LCD_WF55TO52_WF55. */
#define BS_LCD_WF55TO52_WF55 (8U)          /*!< Bit field size in bits for LCD_WF55TO52_WF55. */

/*! @brief Read current value of the LCD_WF55TO52_WF55 field. */
#define BR_LCD_WF55TO52_WF55(x) (BME_UBFX32(HW_LCD_WF55TO52_ADDR(x), BP_LCD_WF55TO52_WF55, BS_LCD_WF55TO52_WF55))

/*! @brief Format value for bitfield LCD_WF55TO52_WF55. */
#define BF_LCD_WF55TO52_WF55(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF55TO52_WF55) & BM_LCD_WF55TO52_WF55)

/*! @brief Set the WF55 field to a new value. */
#define BW_LCD_WF55TO52_WF55(x, v) (BME_BFI32(HW_LCD_WF55TO52_ADDR(x), ((uint32_t)(v) << BP_LCD_WF55TO52_WF55), BP_LCD_WF55TO52_WF55, 8))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF59TO56 - LCD Waveform register
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF59TO56 - LCD Waveform register (RW)
 *
 * Reset value: 0x00000000U
 *
 * See the LCD Waveform register (WFC3TO0) for register and field descriptions.
 * The reset value of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_wf59to56
{
    uint32_t U;
    struct _hw_lcd_wf59to56_bitfields
    {
        uint32_t WF56 : 8;             /*!< [7:0]  */
        uint32_t WF57 : 8;             /*!< [15:8]  */
        uint32_t WF58 : 8;             /*!< [23:16]  */
        uint32_t WF59 : 8;             /*!< [31:24]  */
    } B;
} hw_lcd_wf59to56_t;

/*!
 * @name Constants and macros for entire LCD_WF59TO56 register
 */
/*@{*/
#define HW_LCD_WF59TO56_ADDR(x)  ((x) + 0x58U)

#define HW_LCD_WF59TO56(x)       (*(__IO hw_lcd_wf59to56_t *) HW_LCD_WF59TO56_ADDR(x))
#define HW_LCD_WF59TO56_RD(x)    (HW_LCD_WF59TO56(x).U)
#define HW_LCD_WF59TO56_WR(x, v) (HW_LCD_WF59TO56(x).U = (v))
#define HW_LCD_WF59TO56_SET(x, v) (BME_OR32(HW_LCD_WF59TO56_ADDR(x), (uint32_t)(v)))
#define HW_LCD_WF59TO56_CLR(x, v) (BME_AND32(HW_LCD_WF59TO56_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_WF59TO56_TOG(x, v) (BME_XOR32(HW_LCD_WF59TO56_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF59TO56 bitfields
 */

/*!
 * @name Register LCD_WF59TO56, field WF56[7:0] (RW)
 *
 * Controls segments or phases connected to LCD_P56 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF59TO56_WF56 (0U)          /*!< Bit position for LCD_WF59TO56_WF56. */
#define BM_LCD_WF59TO56_WF56 (0x000000FFU) /*!< Bit mask for LCD_WF59TO56_WF56. */
#define BS_LCD_WF59TO56_WF56 (8U)          /*!< Bit field size in bits for LCD_WF59TO56_WF56. */

/*! @brief Read current value of the LCD_WF59TO56_WF56 field. */
#define BR_LCD_WF59TO56_WF56(x) (BME_UBFX32(HW_LCD_WF59TO56_ADDR(x), BP_LCD_WF59TO56_WF56, BS_LCD_WF59TO56_WF56))

/*! @brief Format value for bitfield LCD_WF59TO56_WF56. */
#define BF_LCD_WF59TO56_WF56(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF59TO56_WF56) & BM_LCD_WF59TO56_WF56)

/*! @brief Set the WF56 field to a new value. */
#define BW_LCD_WF59TO56_WF56(x, v) (BME_BFI32(HW_LCD_WF59TO56_ADDR(x), ((uint32_t)(v) << BP_LCD_WF59TO56_WF56), BP_LCD_WF59TO56_WF56, 8))
/*@}*/

/*!
 * @name Register LCD_WF59TO56, field WF57[15:8] (RW)
 *
 * Controls segments or phases connected to LCD_P57 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF59TO56_WF57 (8U)          /*!< Bit position for LCD_WF59TO56_WF57. */
#define BM_LCD_WF59TO56_WF57 (0x0000FF00U) /*!< Bit mask for LCD_WF59TO56_WF57. */
#define BS_LCD_WF59TO56_WF57 (8U)          /*!< Bit field size in bits for LCD_WF59TO56_WF57. */

/*! @brief Read current value of the LCD_WF59TO56_WF57 field. */
#define BR_LCD_WF59TO56_WF57(x) (BME_UBFX32(HW_LCD_WF59TO56_ADDR(x), BP_LCD_WF59TO56_WF57, BS_LCD_WF59TO56_WF57))

/*! @brief Format value for bitfield LCD_WF59TO56_WF57. */
#define BF_LCD_WF59TO56_WF57(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF59TO56_WF57) & BM_LCD_WF59TO56_WF57)

/*! @brief Set the WF57 field to a new value. */
#define BW_LCD_WF59TO56_WF57(x, v) (BME_BFI32(HW_LCD_WF59TO56_ADDR(x), ((uint32_t)(v) << BP_LCD_WF59TO56_WF57), BP_LCD_WF59TO56_WF57, 8))
/*@}*/

/*!
 * @name Register LCD_WF59TO56, field WF58[23:16] (RW)
 *
 * Controls segments or phases connected to LCD_P58 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF59TO56_WF58 (16U)         /*!< Bit position for LCD_WF59TO56_WF58. */
#define BM_LCD_WF59TO56_WF58 (0x00FF0000U) /*!< Bit mask for LCD_WF59TO56_WF58. */
#define BS_LCD_WF59TO56_WF58 (8U)          /*!< Bit field size in bits for LCD_WF59TO56_WF58. */

/*! @brief Read current value of the LCD_WF59TO56_WF58 field. */
#define BR_LCD_WF59TO56_WF58(x) (BME_UBFX32(HW_LCD_WF59TO56_ADDR(x), BP_LCD_WF59TO56_WF58, BS_LCD_WF59TO56_WF58))

/*! @brief Format value for bitfield LCD_WF59TO56_WF58. */
#define BF_LCD_WF59TO56_WF58(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF59TO56_WF58) & BM_LCD_WF59TO56_WF58)

/*! @brief Set the WF58 field to a new value. */
#define BW_LCD_WF59TO56_WF58(x, v) (BME_BFI32(HW_LCD_WF59TO56_ADDR(x), ((uint32_t)(v) << BP_LCD_WF59TO56_WF58), BP_LCD_WF59TO56_WF58, 8))
/*@}*/

/*!
 * @name Register LCD_WF59TO56, field WF59[31:24] (RW)
 *
 * Controls segments or phases connected to LCD_P59 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF59TO56_WF59 (24U)         /*!< Bit position for LCD_WF59TO56_WF59. */
#define BM_LCD_WF59TO56_WF59 (0xFF000000U) /*!< Bit mask for LCD_WF59TO56_WF59. */
#define BS_LCD_WF59TO56_WF59 (8U)          /*!< Bit field size in bits for LCD_WF59TO56_WF59. */

/*! @brief Read current value of the LCD_WF59TO56_WF59 field. */
#define BR_LCD_WF59TO56_WF59(x) (BME_UBFX32(HW_LCD_WF59TO56_ADDR(x), BP_LCD_WF59TO56_WF59, BS_LCD_WF59TO56_WF59))

/*! @brief Format value for bitfield LCD_WF59TO56_WF59. */
#define BF_LCD_WF59TO56_WF59(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF59TO56_WF59) & BM_LCD_WF59TO56_WF59)

/*! @brief Set the WF59 field to a new value. */
#define BW_LCD_WF59TO56_WF59(x, v) (BME_BFI32(HW_LCD_WF59TO56_ADDR(x), ((uint32_t)(v) << BP_LCD_WF59TO56_WF59), BP_LCD_WF59TO56_WF59, 8))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF63TO60 - LCD Waveform register
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF63TO60 - LCD Waveform register (RW)
 *
 * Reset value: 0x00000000U
 *
 * See the LCD Waveform register (WFC3TO0) for register and field descriptions.
 * The reset value of this register depends on the reset type: POR - 0x0000_0000
 */
typedef union _hw_lcd_wf63to60
{
    uint32_t U;
    struct _hw_lcd_wf63to60_bitfields
    {
        uint32_t WF60 : 8;             /*!< [7:0]  */
        uint32_t WF61 : 8;             /*!< [15:8]  */
        uint32_t WF62 : 8;             /*!< [23:16]  */
        uint32_t WF63 : 8;             /*!< [31:24]  */
    } B;
} hw_lcd_wf63to60_t;

/*!
 * @name Constants and macros for entire LCD_WF63TO60 register
 */
/*@{*/
#define HW_LCD_WF63TO60_ADDR(x)  ((x) + 0x5CU)

#define HW_LCD_WF63TO60(x)       (*(__IO hw_lcd_wf63to60_t *) HW_LCD_WF63TO60_ADDR(x))
#define HW_LCD_WF63TO60_RD(x)    (HW_LCD_WF63TO60(x).U)
#define HW_LCD_WF63TO60_WR(x, v) (HW_LCD_WF63TO60(x).U = (v))
#define HW_LCD_WF63TO60_SET(x, v) (BME_OR32(HW_LCD_WF63TO60_ADDR(x), (uint32_t)(v)))
#define HW_LCD_WF63TO60_CLR(x, v) (BME_AND32(HW_LCD_WF63TO60_ADDR(x), (uint32_t)(~(v))))
#define HW_LCD_WF63TO60_TOG(x, v) (BME_XOR32(HW_LCD_WF63TO60_ADDR(x), (uint32_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF63TO60 bitfields
 */

/*!
 * @name Register LCD_WF63TO60, field WF60[7:0] (RW)
 *
 * Controls segments or phases connected to LCD_P60 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF63TO60_WF60 (0U)          /*!< Bit position for LCD_WF63TO60_WF60. */
#define BM_LCD_WF63TO60_WF60 (0x000000FFU) /*!< Bit mask for LCD_WF63TO60_WF60. */
#define BS_LCD_WF63TO60_WF60 (8U)          /*!< Bit field size in bits for LCD_WF63TO60_WF60. */

/*! @brief Read current value of the LCD_WF63TO60_WF60 field. */
#define BR_LCD_WF63TO60_WF60(x) (BME_UBFX32(HW_LCD_WF63TO60_ADDR(x), BP_LCD_WF63TO60_WF60, BS_LCD_WF63TO60_WF60))

/*! @brief Format value for bitfield LCD_WF63TO60_WF60. */
#define BF_LCD_WF63TO60_WF60(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF63TO60_WF60) & BM_LCD_WF63TO60_WF60)

/*! @brief Set the WF60 field to a new value. */
#define BW_LCD_WF63TO60_WF60(x, v) (BME_BFI32(HW_LCD_WF63TO60_ADDR(x), ((uint32_t)(v) << BP_LCD_WF63TO60_WF60), BP_LCD_WF63TO60_WF60, 8))
/*@}*/

/*!
 * @name Register LCD_WF63TO60, field WF61[15:8] (RW)
 *
 * Controls segments or phases connected to LCD_P61 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF63TO60_WF61 (8U)          /*!< Bit position for LCD_WF63TO60_WF61. */
#define BM_LCD_WF63TO60_WF61 (0x0000FF00U) /*!< Bit mask for LCD_WF63TO60_WF61. */
#define BS_LCD_WF63TO60_WF61 (8U)          /*!< Bit field size in bits for LCD_WF63TO60_WF61. */

/*! @brief Read current value of the LCD_WF63TO60_WF61 field. */
#define BR_LCD_WF63TO60_WF61(x) (BME_UBFX32(HW_LCD_WF63TO60_ADDR(x), BP_LCD_WF63TO60_WF61, BS_LCD_WF63TO60_WF61))

/*! @brief Format value for bitfield LCD_WF63TO60_WF61. */
#define BF_LCD_WF63TO60_WF61(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF63TO60_WF61) & BM_LCD_WF63TO60_WF61)

/*! @brief Set the WF61 field to a new value. */
#define BW_LCD_WF63TO60_WF61(x, v) (BME_BFI32(HW_LCD_WF63TO60_ADDR(x), ((uint32_t)(v) << BP_LCD_WF63TO60_WF61), BP_LCD_WF63TO60_WF61, 8))
/*@}*/

/*!
 * @name Register LCD_WF63TO60, field WF62[23:16] (RW)
 *
 * Controls segments or phases connected to LCD_P62 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF63TO60_WF62 (16U)         /*!< Bit position for LCD_WF63TO60_WF62. */
#define BM_LCD_WF63TO60_WF62 (0x00FF0000U) /*!< Bit mask for LCD_WF63TO60_WF62. */
#define BS_LCD_WF63TO60_WF62 (8U)          /*!< Bit field size in bits for LCD_WF63TO60_WF62. */

/*! @brief Read current value of the LCD_WF63TO60_WF62 field. */
#define BR_LCD_WF63TO60_WF62(x) (BME_UBFX32(HW_LCD_WF63TO60_ADDR(x), BP_LCD_WF63TO60_WF62, BS_LCD_WF63TO60_WF62))

/*! @brief Format value for bitfield LCD_WF63TO60_WF62. */
#define BF_LCD_WF63TO60_WF62(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF63TO60_WF62) & BM_LCD_WF63TO60_WF62)

/*! @brief Set the WF62 field to a new value. */
#define BW_LCD_WF63TO60_WF62(x, v) (BME_BFI32(HW_LCD_WF63TO60_ADDR(x), ((uint32_t)(v) << BP_LCD_WF63TO60_WF62), BP_LCD_WF63TO60_WF62, 8))
/*@}*/

/*!
 * @name Register LCD_WF63TO60, field WF63[31:24] (RW)
 *
 * Controls segments or phases connected to LCD_P63 as described above for
 * WF3TO0[WF3].
 */
/*@{*/
#define BP_LCD_WF63TO60_WF63 (24U)         /*!< Bit position for LCD_WF63TO60_WF63. */
#define BM_LCD_WF63TO60_WF63 (0xFF000000U) /*!< Bit mask for LCD_WF63TO60_WF63. */
#define BS_LCD_WF63TO60_WF63 (8U)          /*!< Bit field size in bits for LCD_WF63TO60_WF63. */

/*! @brief Read current value of the LCD_WF63TO60_WF63 field. */
#define BR_LCD_WF63TO60_WF63(x) (BME_UBFX32(HW_LCD_WF63TO60_ADDR(x), BP_LCD_WF63TO60_WF63, BS_LCD_WF63TO60_WF63))

/*! @brief Format value for bitfield LCD_WF63TO60_WF63. */
#define BF_LCD_WF63TO60_WF63(v) ((uint32_t)((uint32_t)(v) << BP_LCD_WF63TO60_WF63) & BM_LCD_WF63TO60_WF63)

/*! @brief Set the WF63 field to a new value. */
#define BW_LCD_WF63TO60_WF63(x, v) (BME_BFI32(HW_LCD_WF63TO60_ADDR(x), ((uint32_t)(v) << BP_LCD_WF63TO60_WF63), BP_LCD_WF63TO60_WF63, 8))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF0 - LCD Waveform Register 0.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF0 - LCD Waveform Register 0. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf0
{
    uint8_t U;
    struct _hw_lcd_wf0_bitfields
    {
        uint8_t BPALCD0 : 1;           /*!< [0]  */
        uint8_t BPBLCD0 : 1;           /*!< [1]  */
        uint8_t BPCLCD0 : 1;           /*!< [2]  */
        uint8_t BPDLCD0 : 1;           /*!< [3]  */
        uint8_t BPELCD0 : 1;           /*!< [4]  */
        uint8_t BPFLCD0 : 1;           /*!< [5]  */
        uint8_t BPGLCD0 : 1;           /*!< [6]  */
        uint8_t BPHLCD0 : 1;           /*!< [7]  */
    } B;
} hw_lcd_wf0_t;

/*!
 * @name Constants and macros for entire LCD_WF0 register
 */
/*@{*/
#define HW_LCD_WF0_ADDR(x)       ((x) + 0x20U)

#define HW_LCD_WF0(x)            (*(__IO hw_lcd_wf0_t *) HW_LCD_WF0_ADDR(x))
#define HW_LCD_WF0_RD(x)         (HW_LCD_WF0(x).U)
#define HW_LCD_WF0_WR(x, v)      (HW_LCD_WF0(x).U = (v))
#define HW_LCD_WF0_SET(x, v)     (BME_OR8(HW_LCD_WF0_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF0_CLR(x, v)     (BME_AND8(HW_LCD_WF0_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF0_TOG(x, v)     (BME_XOR8(HW_LCD_WF0_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF0 bitfields
 */

/*!
 * @name Register LCD_WF0, field BPALCD0[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF0_BPALCD0   (0U)          /*!< Bit position for LCD_WF0_BPALCD0. */
#define BM_LCD_WF0_BPALCD0   (0x01U)       /*!< Bit mask for LCD_WF0_BPALCD0. */
#define BS_LCD_WF0_BPALCD0   (1U)          /*!< Bit field size in bits for LCD_WF0_BPALCD0. */

/*! @brief Read current value of the LCD_WF0_BPALCD0 field. */
#define BR_LCD_WF0_BPALCD0(x) (BME_UBFX8(HW_LCD_WF0_ADDR(x), BP_LCD_WF0_BPALCD0, BS_LCD_WF0_BPALCD0))

/*! @brief Format value for bitfield LCD_WF0_BPALCD0. */
#define BF_LCD_WF0_BPALCD0(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF0_BPALCD0) & BM_LCD_WF0_BPALCD0)

/*! @brief Set the BPALCD0 field to a new value. */
#define BW_LCD_WF0_BPALCD0(x, v) (BME_BFI8(HW_LCD_WF0_ADDR(x), ((uint8_t)(v) << BP_LCD_WF0_BPALCD0), BP_LCD_WF0_BPALCD0, 1))
/*@}*/

/*!
 * @name Register LCD_WF0, field BPBLCD0[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF0_BPBLCD0   (1U)          /*!< Bit position for LCD_WF0_BPBLCD0. */
#define BM_LCD_WF0_BPBLCD0   (0x02U)       /*!< Bit mask for LCD_WF0_BPBLCD0. */
#define BS_LCD_WF0_BPBLCD0   (1U)          /*!< Bit field size in bits for LCD_WF0_BPBLCD0. */

/*! @brief Read current value of the LCD_WF0_BPBLCD0 field. */
#define BR_LCD_WF0_BPBLCD0(x) (BME_UBFX8(HW_LCD_WF0_ADDR(x), BP_LCD_WF0_BPBLCD0, BS_LCD_WF0_BPBLCD0))

/*! @brief Format value for bitfield LCD_WF0_BPBLCD0. */
#define BF_LCD_WF0_BPBLCD0(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF0_BPBLCD0) & BM_LCD_WF0_BPBLCD0)

/*! @brief Set the BPBLCD0 field to a new value. */
#define BW_LCD_WF0_BPBLCD0(x, v) (BME_BFI8(HW_LCD_WF0_ADDR(x), ((uint8_t)(v) << BP_LCD_WF0_BPBLCD0), BP_LCD_WF0_BPBLCD0, 1))
/*@}*/

/*!
 * @name Register LCD_WF0, field BPCLCD0[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF0_BPCLCD0   (2U)          /*!< Bit position for LCD_WF0_BPCLCD0. */
#define BM_LCD_WF0_BPCLCD0   (0x04U)       /*!< Bit mask for LCD_WF0_BPCLCD0. */
#define BS_LCD_WF0_BPCLCD0   (1U)          /*!< Bit field size in bits for LCD_WF0_BPCLCD0. */

/*! @brief Read current value of the LCD_WF0_BPCLCD0 field. */
#define BR_LCD_WF0_BPCLCD0(x) (BME_UBFX8(HW_LCD_WF0_ADDR(x), BP_LCD_WF0_BPCLCD0, BS_LCD_WF0_BPCLCD0))

/*! @brief Format value for bitfield LCD_WF0_BPCLCD0. */
#define BF_LCD_WF0_BPCLCD0(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF0_BPCLCD0) & BM_LCD_WF0_BPCLCD0)

/*! @brief Set the BPCLCD0 field to a new value. */
#define BW_LCD_WF0_BPCLCD0(x, v) (BME_BFI8(HW_LCD_WF0_ADDR(x), ((uint8_t)(v) << BP_LCD_WF0_BPCLCD0), BP_LCD_WF0_BPCLCD0, 1))
/*@}*/

/*!
 * @name Register LCD_WF0, field BPDLCD0[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF0_BPDLCD0   (3U)          /*!< Bit position for LCD_WF0_BPDLCD0. */
#define BM_LCD_WF0_BPDLCD0   (0x08U)       /*!< Bit mask for LCD_WF0_BPDLCD0. */
#define BS_LCD_WF0_BPDLCD0   (1U)          /*!< Bit field size in bits for LCD_WF0_BPDLCD0. */

/*! @brief Read current value of the LCD_WF0_BPDLCD0 field. */
#define BR_LCD_WF0_BPDLCD0(x) (BME_UBFX8(HW_LCD_WF0_ADDR(x), BP_LCD_WF0_BPDLCD0, BS_LCD_WF0_BPDLCD0))

/*! @brief Format value for bitfield LCD_WF0_BPDLCD0. */
#define BF_LCD_WF0_BPDLCD0(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF0_BPDLCD0) & BM_LCD_WF0_BPDLCD0)

/*! @brief Set the BPDLCD0 field to a new value. */
#define BW_LCD_WF0_BPDLCD0(x, v) (BME_BFI8(HW_LCD_WF0_ADDR(x), ((uint8_t)(v) << BP_LCD_WF0_BPDLCD0), BP_LCD_WF0_BPDLCD0, 1))
/*@}*/

/*!
 * @name Register LCD_WF0, field BPELCD0[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF0_BPELCD0   (4U)          /*!< Bit position for LCD_WF0_BPELCD0. */
#define BM_LCD_WF0_BPELCD0   (0x10U)       /*!< Bit mask for LCD_WF0_BPELCD0. */
#define BS_LCD_WF0_BPELCD0   (1U)          /*!< Bit field size in bits for LCD_WF0_BPELCD0. */

/*! @brief Read current value of the LCD_WF0_BPELCD0 field. */
#define BR_LCD_WF0_BPELCD0(x) (BME_UBFX8(HW_LCD_WF0_ADDR(x), BP_LCD_WF0_BPELCD0, BS_LCD_WF0_BPELCD0))

/*! @brief Format value for bitfield LCD_WF0_BPELCD0. */
#define BF_LCD_WF0_BPELCD0(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF0_BPELCD0) & BM_LCD_WF0_BPELCD0)

/*! @brief Set the BPELCD0 field to a new value. */
#define BW_LCD_WF0_BPELCD0(x, v) (BME_BFI8(HW_LCD_WF0_ADDR(x), ((uint8_t)(v) << BP_LCD_WF0_BPELCD0), BP_LCD_WF0_BPELCD0, 1))
/*@}*/

/*!
 * @name Register LCD_WF0, field BPFLCD0[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF0_BPFLCD0   (5U)          /*!< Bit position for LCD_WF0_BPFLCD0. */
#define BM_LCD_WF0_BPFLCD0   (0x20U)       /*!< Bit mask for LCD_WF0_BPFLCD0. */
#define BS_LCD_WF0_BPFLCD0   (1U)          /*!< Bit field size in bits for LCD_WF0_BPFLCD0. */

/*! @brief Read current value of the LCD_WF0_BPFLCD0 field. */
#define BR_LCD_WF0_BPFLCD0(x) (BME_UBFX8(HW_LCD_WF0_ADDR(x), BP_LCD_WF0_BPFLCD0, BS_LCD_WF0_BPFLCD0))

/*! @brief Format value for bitfield LCD_WF0_BPFLCD0. */
#define BF_LCD_WF0_BPFLCD0(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF0_BPFLCD0) & BM_LCD_WF0_BPFLCD0)

/*! @brief Set the BPFLCD0 field to a new value. */
#define BW_LCD_WF0_BPFLCD0(x, v) (BME_BFI8(HW_LCD_WF0_ADDR(x), ((uint8_t)(v) << BP_LCD_WF0_BPFLCD0), BP_LCD_WF0_BPFLCD0, 1))
/*@}*/

/*!
 * @name Register LCD_WF0, field BPGLCD0[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF0_BPGLCD0   (6U)          /*!< Bit position for LCD_WF0_BPGLCD0. */
#define BM_LCD_WF0_BPGLCD0   (0x40U)       /*!< Bit mask for LCD_WF0_BPGLCD0. */
#define BS_LCD_WF0_BPGLCD0   (1U)          /*!< Bit field size in bits for LCD_WF0_BPGLCD0. */

/*! @brief Read current value of the LCD_WF0_BPGLCD0 field. */
#define BR_LCD_WF0_BPGLCD0(x) (BME_UBFX8(HW_LCD_WF0_ADDR(x), BP_LCD_WF0_BPGLCD0, BS_LCD_WF0_BPGLCD0))

/*! @brief Format value for bitfield LCD_WF0_BPGLCD0. */
#define BF_LCD_WF0_BPGLCD0(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF0_BPGLCD0) & BM_LCD_WF0_BPGLCD0)

/*! @brief Set the BPGLCD0 field to a new value. */
#define BW_LCD_WF0_BPGLCD0(x, v) (BME_BFI8(HW_LCD_WF0_ADDR(x), ((uint8_t)(v) << BP_LCD_WF0_BPGLCD0), BP_LCD_WF0_BPGLCD0, 1))
/*@}*/

/*!
 * @name Register LCD_WF0, field BPHLCD0[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF0_BPHLCD0   (7U)          /*!< Bit position for LCD_WF0_BPHLCD0. */
#define BM_LCD_WF0_BPHLCD0   (0x80U)       /*!< Bit mask for LCD_WF0_BPHLCD0. */
#define BS_LCD_WF0_BPHLCD0   (1U)          /*!< Bit field size in bits for LCD_WF0_BPHLCD0. */

/*! @brief Read current value of the LCD_WF0_BPHLCD0 field. */
#define BR_LCD_WF0_BPHLCD0(x) (BME_UBFX8(HW_LCD_WF0_ADDR(x), BP_LCD_WF0_BPHLCD0, BS_LCD_WF0_BPHLCD0))

/*! @brief Format value for bitfield LCD_WF0_BPHLCD0. */
#define BF_LCD_WF0_BPHLCD0(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF0_BPHLCD0) & BM_LCD_WF0_BPHLCD0)

/*! @brief Set the BPHLCD0 field to a new value. */
#define BW_LCD_WF0_BPHLCD0(x, v) (BME_BFI8(HW_LCD_WF0_ADDR(x), ((uint8_t)(v) << BP_LCD_WF0_BPHLCD0), BP_LCD_WF0_BPHLCD0, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF1 - LCD Waveform Register 1.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF1 - LCD Waveform Register 1. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf1
{
    uint8_t U;
    struct _hw_lcd_wf1_bitfields
    {
        uint8_t BPALCD1 : 1;           /*!< [0]  */
        uint8_t BPBLCD1 : 1;           /*!< [1]  */
        uint8_t BPCLCD1 : 1;           /*!< [2]  */
        uint8_t BPDLCD1 : 1;           /*!< [3]  */
        uint8_t BPELCD1 : 1;           /*!< [4]  */
        uint8_t BPFLCD1 : 1;           /*!< [5]  */
        uint8_t BPGLCD1 : 1;           /*!< [6]  */
        uint8_t BPHLCD1 : 1;           /*!< [7]  */
    } B;
} hw_lcd_wf1_t;

/*!
 * @name Constants and macros for entire LCD_WF1 register
 */
/*@{*/
#define HW_LCD_WF1_ADDR(x)       ((x) + 0x21U)

#define HW_LCD_WF1(x)            (*(__IO hw_lcd_wf1_t *) HW_LCD_WF1_ADDR(x))
#define HW_LCD_WF1_RD(x)         (HW_LCD_WF1(x).U)
#define HW_LCD_WF1_WR(x, v)      (HW_LCD_WF1(x).U = (v))
#define HW_LCD_WF1_SET(x, v)     (BME_OR8(HW_LCD_WF1_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF1_CLR(x, v)     (BME_AND8(HW_LCD_WF1_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF1_TOG(x, v)     (BME_XOR8(HW_LCD_WF1_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF1 bitfields
 */

/*!
 * @name Register LCD_WF1, field BPALCD1[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF1_BPALCD1   (0U)          /*!< Bit position for LCD_WF1_BPALCD1. */
#define BM_LCD_WF1_BPALCD1   (0x01U)       /*!< Bit mask for LCD_WF1_BPALCD1. */
#define BS_LCD_WF1_BPALCD1   (1U)          /*!< Bit field size in bits for LCD_WF1_BPALCD1. */

/*! @brief Read current value of the LCD_WF1_BPALCD1 field. */
#define BR_LCD_WF1_BPALCD1(x) (BME_UBFX8(HW_LCD_WF1_ADDR(x), BP_LCD_WF1_BPALCD1, BS_LCD_WF1_BPALCD1))

/*! @brief Format value for bitfield LCD_WF1_BPALCD1. */
#define BF_LCD_WF1_BPALCD1(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF1_BPALCD1) & BM_LCD_WF1_BPALCD1)

/*! @brief Set the BPALCD1 field to a new value. */
#define BW_LCD_WF1_BPALCD1(x, v) (BME_BFI8(HW_LCD_WF1_ADDR(x), ((uint8_t)(v) << BP_LCD_WF1_BPALCD1), BP_LCD_WF1_BPALCD1, 1))
/*@}*/

/*!
 * @name Register LCD_WF1, field BPBLCD1[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF1_BPBLCD1   (1U)          /*!< Bit position for LCD_WF1_BPBLCD1. */
#define BM_LCD_WF1_BPBLCD1   (0x02U)       /*!< Bit mask for LCD_WF1_BPBLCD1. */
#define BS_LCD_WF1_BPBLCD1   (1U)          /*!< Bit field size in bits for LCD_WF1_BPBLCD1. */

/*! @brief Read current value of the LCD_WF1_BPBLCD1 field. */
#define BR_LCD_WF1_BPBLCD1(x) (BME_UBFX8(HW_LCD_WF1_ADDR(x), BP_LCD_WF1_BPBLCD1, BS_LCD_WF1_BPBLCD1))

/*! @brief Format value for bitfield LCD_WF1_BPBLCD1. */
#define BF_LCD_WF1_BPBLCD1(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF1_BPBLCD1) & BM_LCD_WF1_BPBLCD1)

/*! @brief Set the BPBLCD1 field to a new value. */
#define BW_LCD_WF1_BPBLCD1(x, v) (BME_BFI8(HW_LCD_WF1_ADDR(x), ((uint8_t)(v) << BP_LCD_WF1_BPBLCD1), BP_LCD_WF1_BPBLCD1, 1))
/*@}*/

/*!
 * @name Register LCD_WF1, field BPCLCD1[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF1_BPCLCD1   (2U)          /*!< Bit position for LCD_WF1_BPCLCD1. */
#define BM_LCD_WF1_BPCLCD1   (0x04U)       /*!< Bit mask for LCD_WF1_BPCLCD1. */
#define BS_LCD_WF1_BPCLCD1   (1U)          /*!< Bit field size in bits for LCD_WF1_BPCLCD1. */

/*! @brief Read current value of the LCD_WF1_BPCLCD1 field. */
#define BR_LCD_WF1_BPCLCD1(x) (BME_UBFX8(HW_LCD_WF1_ADDR(x), BP_LCD_WF1_BPCLCD1, BS_LCD_WF1_BPCLCD1))

/*! @brief Format value for bitfield LCD_WF1_BPCLCD1. */
#define BF_LCD_WF1_BPCLCD1(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF1_BPCLCD1) & BM_LCD_WF1_BPCLCD1)

/*! @brief Set the BPCLCD1 field to a new value. */
#define BW_LCD_WF1_BPCLCD1(x, v) (BME_BFI8(HW_LCD_WF1_ADDR(x), ((uint8_t)(v) << BP_LCD_WF1_BPCLCD1), BP_LCD_WF1_BPCLCD1, 1))
/*@}*/

/*!
 * @name Register LCD_WF1, field BPDLCD1[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF1_BPDLCD1   (3U)          /*!< Bit position for LCD_WF1_BPDLCD1. */
#define BM_LCD_WF1_BPDLCD1   (0x08U)       /*!< Bit mask for LCD_WF1_BPDLCD1. */
#define BS_LCD_WF1_BPDLCD1   (1U)          /*!< Bit field size in bits for LCD_WF1_BPDLCD1. */

/*! @brief Read current value of the LCD_WF1_BPDLCD1 field. */
#define BR_LCD_WF1_BPDLCD1(x) (BME_UBFX8(HW_LCD_WF1_ADDR(x), BP_LCD_WF1_BPDLCD1, BS_LCD_WF1_BPDLCD1))

/*! @brief Format value for bitfield LCD_WF1_BPDLCD1. */
#define BF_LCD_WF1_BPDLCD1(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF1_BPDLCD1) & BM_LCD_WF1_BPDLCD1)

/*! @brief Set the BPDLCD1 field to a new value. */
#define BW_LCD_WF1_BPDLCD1(x, v) (BME_BFI8(HW_LCD_WF1_ADDR(x), ((uint8_t)(v) << BP_LCD_WF1_BPDLCD1), BP_LCD_WF1_BPDLCD1, 1))
/*@}*/

/*!
 * @name Register LCD_WF1, field BPELCD1[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF1_BPELCD1   (4U)          /*!< Bit position for LCD_WF1_BPELCD1. */
#define BM_LCD_WF1_BPELCD1   (0x10U)       /*!< Bit mask for LCD_WF1_BPELCD1. */
#define BS_LCD_WF1_BPELCD1   (1U)          /*!< Bit field size in bits for LCD_WF1_BPELCD1. */

/*! @brief Read current value of the LCD_WF1_BPELCD1 field. */
#define BR_LCD_WF1_BPELCD1(x) (BME_UBFX8(HW_LCD_WF1_ADDR(x), BP_LCD_WF1_BPELCD1, BS_LCD_WF1_BPELCD1))

/*! @brief Format value for bitfield LCD_WF1_BPELCD1. */
#define BF_LCD_WF1_BPELCD1(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF1_BPELCD1) & BM_LCD_WF1_BPELCD1)

/*! @brief Set the BPELCD1 field to a new value. */
#define BW_LCD_WF1_BPELCD1(x, v) (BME_BFI8(HW_LCD_WF1_ADDR(x), ((uint8_t)(v) << BP_LCD_WF1_BPELCD1), BP_LCD_WF1_BPELCD1, 1))
/*@}*/

/*!
 * @name Register LCD_WF1, field BPFLCD1[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF1_BPFLCD1   (5U)          /*!< Bit position for LCD_WF1_BPFLCD1. */
#define BM_LCD_WF1_BPFLCD1   (0x20U)       /*!< Bit mask for LCD_WF1_BPFLCD1. */
#define BS_LCD_WF1_BPFLCD1   (1U)          /*!< Bit field size in bits for LCD_WF1_BPFLCD1. */

/*! @brief Read current value of the LCD_WF1_BPFLCD1 field. */
#define BR_LCD_WF1_BPFLCD1(x) (BME_UBFX8(HW_LCD_WF1_ADDR(x), BP_LCD_WF1_BPFLCD1, BS_LCD_WF1_BPFLCD1))

/*! @brief Format value for bitfield LCD_WF1_BPFLCD1. */
#define BF_LCD_WF1_BPFLCD1(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF1_BPFLCD1) & BM_LCD_WF1_BPFLCD1)

/*! @brief Set the BPFLCD1 field to a new value. */
#define BW_LCD_WF1_BPFLCD1(x, v) (BME_BFI8(HW_LCD_WF1_ADDR(x), ((uint8_t)(v) << BP_LCD_WF1_BPFLCD1), BP_LCD_WF1_BPFLCD1, 1))
/*@}*/

/*!
 * @name Register LCD_WF1, field BPGLCD1[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF1_BPGLCD1   (6U)          /*!< Bit position for LCD_WF1_BPGLCD1. */
#define BM_LCD_WF1_BPGLCD1   (0x40U)       /*!< Bit mask for LCD_WF1_BPGLCD1. */
#define BS_LCD_WF1_BPGLCD1   (1U)          /*!< Bit field size in bits for LCD_WF1_BPGLCD1. */

/*! @brief Read current value of the LCD_WF1_BPGLCD1 field. */
#define BR_LCD_WF1_BPGLCD1(x) (BME_UBFX8(HW_LCD_WF1_ADDR(x), BP_LCD_WF1_BPGLCD1, BS_LCD_WF1_BPGLCD1))

/*! @brief Format value for bitfield LCD_WF1_BPGLCD1. */
#define BF_LCD_WF1_BPGLCD1(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF1_BPGLCD1) & BM_LCD_WF1_BPGLCD1)

/*! @brief Set the BPGLCD1 field to a new value. */
#define BW_LCD_WF1_BPGLCD1(x, v) (BME_BFI8(HW_LCD_WF1_ADDR(x), ((uint8_t)(v) << BP_LCD_WF1_BPGLCD1), BP_LCD_WF1_BPGLCD1, 1))
/*@}*/

/*!
 * @name Register LCD_WF1, field BPHLCD1[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF1_BPHLCD1   (7U)          /*!< Bit position for LCD_WF1_BPHLCD1. */
#define BM_LCD_WF1_BPHLCD1   (0x80U)       /*!< Bit mask for LCD_WF1_BPHLCD1. */
#define BS_LCD_WF1_BPHLCD1   (1U)          /*!< Bit field size in bits for LCD_WF1_BPHLCD1. */

/*! @brief Read current value of the LCD_WF1_BPHLCD1 field. */
#define BR_LCD_WF1_BPHLCD1(x) (BME_UBFX8(HW_LCD_WF1_ADDR(x), BP_LCD_WF1_BPHLCD1, BS_LCD_WF1_BPHLCD1))

/*! @brief Format value for bitfield LCD_WF1_BPHLCD1. */
#define BF_LCD_WF1_BPHLCD1(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF1_BPHLCD1) & BM_LCD_WF1_BPHLCD1)

/*! @brief Set the BPHLCD1 field to a new value. */
#define BW_LCD_WF1_BPHLCD1(x, v) (BME_BFI8(HW_LCD_WF1_ADDR(x), ((uint8_t)(v) << BP_LCD_WF1_BPHLCD1), BP_LCD_WF1_BPHLCD1, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF2 - LCD Waveform Register 2.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF2 - LCD Waveform Register 2. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf2
{
    uint8_t U;
    struct _hw_lcd_wf2_bitfields
    {
        uint8_t BPALCD2 : 1;           /*!< [0]  */
        uint8_t BPBLCD2 : 1;           /*!< [1]  */
        uint8_t BPCLCD2 : 1;           /*!< [2]  */
        uint8_t BPDLCD2 : 1;           /*!< [3]  */
        uint8_t BPELCD2 : 1;           /*!< [4]  */
        uint8_t BPFLCD2 : 1;           /*!< [5]  */
        uint8_t BPGLCD2 : 1;           /*!< [6]  */
        uint8_t BPHLCD2 : 1;           /*!< [7]  */
    } B;
} hw_lcd_wf2_t;

/*!
 * @name Constants and macros for entire LCD_WF2 register
 */
/*@{*/
#define HW_LCD_WF2_ADDR(x)       ((x) + 0x22U)

#define HW_LCD_WF2(x)            (*(__IO hw_lcd_wf2_t *) HW_LCD_WF2_ADDR(x))
#define HW_LCD_WF2_RD(x)         (HW_LCD_WF2(x).U)
#define HW_LCD_WF2_WR(x, v)      (HW_LCD_WF2(x).U = (v))
#define HW_LCD_WF2_SET(x, v)     (BME_OR8(HW_LCD_WF2_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF2_CLR(x, v)     (BME_AND8(HW_LCD_WF2_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF2_TOG(x, v)     (BME_XOR8(HW_LCD_WF2_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF2 bitfields
 */

/*!
 * @name Register LCD_WF2, field BPALCD2[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF2_BPALCD2   (0U)          /*!< Bit position for LCD_WF2_BPALCD2. */
#define BM_LCD_WF2_BPALCD2   (0x01U)       /*!< Bit mask for LCD_WF2_BPALCD2. */
#define BS_LCD_WF2_BPALCD2   (1U)          /*!< Bit field size in bits for LCD_WF2_BPALCD2. */

/*! @brief Read current value of the LCD_WF2_BPALCD2 field. */
#define BR_LCD_WF2_BPALCD2(x) (BME_UBFX8(HW_LCD_WF2_ADDR(x), BP_LCD_WF2_BPALCD2, BS_LCD_WF2_BPALCD2))

/*! @brief Format value for bitfield LCD_WF2_BPALCD2. */
#define BF_LCD_WF2_BPALCD2(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF2_BPALCD2) & BM_LCD_WF2_BPALCD2)

/*! @brief Set the BPALCD2 field to a new value. */
#define BW_LCD_WF2_BPALCD2(x, v) (BME_BFI8(HW_LCD_WF2_ADDR(x), ((uint8_t)(v) << BP_LCD_WF2_BPALCD2), BP_LCD_WF2_BPALCD2, 1))
/*@}*/

/*!
 * @name Register LCD_WF2, field BPBLCD2[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF2_BPBLCD2   (1U)          /*!< Bit position for LCD_WF2_BPBLCD2. */
#define BM_LCD_WF2_BPBLCD2   (0x02U)       /*!< Bit mask for LCD_WF2_BPBLCD2. */
#define BS_LCD_WF2_BPBLCD2   (1U)          /*!< Bit field size in bits for LCD_WF2_BPBLCD2. */

/*! @brief Read current value of the LCD_WF2_BPBLCD2 field. */
#define BR_LCD_WF2_BPBLCD2(x) (BME_UBFX8(HW_LCD_WF2_ADDR(x), BP_LCD_WF2_BPBLCD2, BS_LCD_WF2_BPBLCD2))

/*! @brief Format value for bitfield LCD_WF2_BPBLCD2. */
#define BF_LCD_WF2_BPBLCD2(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF2_BPBLCD2) & BM_LCD_WF2_BPBLCD2)

/*! @brief Set the BPBLCD2 field to a new value. */
#define BW_LCD_WF2_BPBLCD2(x, v) (BME_BFI8(HW_LCD_WF2_ADDR(x), ((uint8_t)(v) << BP_LCD_WF2_BPBLCD2), BP_LCD_WF2_BPBLCD2, 1))
/*@}*/

/*!
 * @name Register LCD_WF2, field BPCLCD2[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF2_BPCLCD2   (2U)          /*!< Bit position for LCD_WF2_BPCLCD2. */
#define BM_LCD_WF2_BPCLCD2   (0x04U)       /*!< Bit mask for LCD_WF2_BPCLCD2. */
#define BS_LCD_WF2_BPCLCD2   (1U)          /*!< Bit field size in bits for LCD_WF2_BPCLCD2. */

/*! @brief Read current value of the LCD_WF2_BPCLCD2 field. */
#define BR_LCD_WF2_BPCLCD2(x) (BME_UBFX8(HW_LCD_WF2_ADDR(x), BP_LCD_WF2_BPCLCD2, BS_LCD_WF2_BPCLCD2))

/*! @brief Format value for bitfield LCD_WF2_BPCLCD2. */
#define BF_LCD_WF2_BPCLCD2(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF2_BPCLCD2) & BM_LCD_WF2_BPCLCD2)

/*! @brief Set the BPCLCD2 field to a new value. */
#define BW_LCD_WF2_BPCLCD2(x, v) (BME_BFI8(HW_LCD_WF2_ADDR(x), ((uint8_t)(v) << BP_LCD_WF2_BPCLCD2), BP_LCD_WF2_BPCLCD2, 1))
/*@}*/

/*!
 * @name Register LCD_WF2, field BPDLCD2[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF2_BPDLCD2   (3U)          /*!< Bit position for LCD_WF2_BPDLCD2. */
#define BM_LCD_WF2_BPDLCD2   (0x08U)       /*!< Bit mask for LCD_WF2_BPDLCD2. */
#define BS_LCD_WF2_BPDLCD2   (1U)          /*!< Bit field size in bits for LCD_WF2_BPDLCD2. */

/*! @brief Read current value of the LCD_WF2_BPDLCD2 field. */
#define BR_LCD_WF2_BPDLCD2(x) (BME_UBFX8(HW_LCD_WF2_ADDR(x), BP_LCD_WF2_BPDLCD2, BS_LCD_WF2_BPDLCD2))

/*! @brief Format value for bitfield LCD_WF2_BPDLCD2. */
#define BF_LCD_WF2_BPDLCD2(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF2_BPDLCD2) & BM_LCD_WF2_BPDLCD2)

/*! @brief Set the BPDLCD2 field to a new value. */
#define BW_LCD_WF2_BPDLCD2(x, v) (BME_BFI8(HW_LCD_WF2_ADDR(x), ((uint8_t)(v) << BP_LCD_WF2_BPDLCD2), BP_LCD_WF2_BPDLCD2, 1))
/*@}*/

/*!
 * @name Register LCD_WF2, field BPELCD2[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF2_BPELCD2   (4U)          /*!< Bit position for LCD_WF2_BPELCD2. */
#define BM_LCD_WF2_BPELCD2   (0x10U)       /*!< Bit mask for LCD_WF2_BPELCD2. */
#define BS_LCD_WF2_BPELCD2   (1U)          /*!< Bit field size in bits for LCD_WF2_BPELCD2. */

/*! @brief Read current value of the LCD_WF2_BPELCD2 field. */
#define BR_LCD_WF2_BPELCD2(x) (BME_UBFX8(HW_LCD_WF2_ADDR(x), BP_LCD_WF2_BPELCD2, BS_LCD_WF2_BPELCD2))

/*! @brief Format value for bitfield LCD_WF2_BPELCD2. */
#define BF_LCD_WF2_BPELCD2(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF2_BPELCD2) & BM_LCD_WF2_BPELCD2)

/*! @brief Set the BPELCD2 field to a new value. */
#define BW_LCD_WF2_BPELCD2(x, v) (BME_BFI8(HW_LCD_WF2_ADDR(x), ((uint8_t)(v) << BP_LCD_WF2_BPELCD2), BP_LCD_WF2_BPELCD2, 1))
/*@}*/

/*!
 * @name Register LCD_WF2, field BPFLCD2[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF2_BPFLCD2   (5U)          /*!< Bit position for LCD_WF2_BPFLCD2. */
#define BM_LCD_WF2_BPFLCD2   (0x20U)       /*!< Bit mask for LCD_WF2_BPFLCD2. */
#define BS_LCD_WF2_BPFLCD2   (1U)          /*!< Bit field size in bits for LCD_WF2_BPFLCD2. */

/*! @brief Read current value of the LCD_WF2_BPFLCD2 field. */
#define BR_LCD_WF2_BPFLCD2(x) (BME_UBFX8(HW_LCD_WF2_ADDR(x), BP_LCD_WF2_BPFLCD2, BS_LCD_WF2_BPFLCD2))

/*! @brief Format value for bitfield LCD_WF2_BPFLCD2. */
#define BF_LCD_WF2_BPFLCD2(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF2_BPFLCD2) & BM_LCD_WF2_BPFLCD2)

/*! @brief Set the BPFLCD2 field to a new value. */
#define BW_LCD_WF2_BPFLCD2(x, v) (BME_BFI8(HW_LCD_WF2_ADDR(x), ((uint8_t)(v) << BP_LCD_WF2_BPFLCD2), BP_LCD_WF2_BPFLCD2, 1))
/*@}*/

/*!
 * @name Register LCD_WF2, field BPGLCD2[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF2_BPGLCD2   (6U)          /*!< Bit position for LCD_WF2_BPGLCD2. */
#define BM_LCD_WF2_BPGLCD2   (0x40U)       /*!< Bit mask for LCD_WF2_BPGLCD2. */
#define BS_LCD_WF2_BPGLCD2   (1U)          /*!< Bit field size in bits for LCD_WF2_BPGLCD2. */

/*! @brief Read current value of the LCD_WF2_BPGLCD2 field. */
#define BR_LCD_WF2_BPGLCD2(x) (BME_UBFX8(HW_LCD_WF2_ADDR(x), BP_LCD_WF2_BPGLCD2, BS_LCD_WF2_BPGLCD2))

/*! @brief Format value for bitfield LCD_WF2_BPGLCD2. */
#define BF_LCD_WF2_BPGLCD2(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF2_BPGLCD2) & BM_LCD_WF2_BPGLCD2)

/*! @brief Set the BPGLCD2 field to a new value. */
#define BW_LCD_WF2_BPGLCD2(x, v) (BME_BFI8(HW_LCD_WF2_ADDR(x), ((uint8_t)(v) << BP_LCD_WF2_BPGLCD2), BP_LCD_WF2_BPGLCD2, 1))
/*@}*/

/*!
 * @name Register LCD_WF2, field BPHLCD2[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF2_BPHLCD2   (7U)          /*!< Bit position for LCD_WF2_BPHLCD2. */
#define BM_LCD_WF2_BPHLCD2   (0x80U)       /*!< Bit mask for LCD_WF2_BPHLCD2. */
#define BS_LCD_WF2_BPHLCD2   (1U)          /*!< Bit field size in bits for LCD_WF2_BPHLCD2. */

/*! @brief Read current value of the LCD_WF2_BPHLCD2 field. */
#define BR_LCD_WF2_BPHLCD2(x) (BME_UBFX8(HW_LCD_WF2_ADDR(x), BP_LCD_WF2_BPHLCD2, BS_LCD_WF2_BPHLCD2))

/*! @brief Format value for bitfield LCD_WF2_BPHLCD2. */
#define BF_LCD_WF2_BPHLCD2(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF2_BPHLCD2) & BM_LCD_WF2_BPHLCD2)

/*! @brief Set the BPHLCD2 field to a new value. */
#define BW_LCD_WF2_BPHLCD2(x, v) (BME_BFI8(HW_LCD_WF2_ADDR(x), ((uint8_t)(v) << BP_LCD_WF2_BPHLCD2), BP_LCD_WF2_BPHLCD2, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF3 - LCD Waveform Register 3.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF3 - LCD Waveform Register 3. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf3
{
    uint8_t U;
    struct _hw_lcd_wf3_bitfields
    {
        uint8_t BPALCD3 : 1;           /*!< [0]  */
        uint8_t BPBLCD3 : 1;           /*!< [1]  */
        uint8_t BPCLCD3 : 1;           /*!< [2]  */
        uint8_t BPDLCD3 : 1;           /*!< [3]  */
        uint8_t BPELCD3 : 1;           /*!< [4]  */
        uint8_t BPFLCD3 : 1;           /*!< [5]  */
        uint8_t BPGLCD3 : 1;           /*!< [6]  */
        uint8_t BPHLCD3 : 1;           /*!< [7]  */
    } B;
} hw_lcd_wf3_t;

/*!
 * @name Constants and macros for entire LCD_WF3 register
 */
/*@{*/
#define HW_LCD_WF3_ADDR(x)       ((x) + 0x23U)

#define HW_LCD_WF3(x)            (*(__IO hw_lcd_wf3_t *) HW_LCD_WF3_ADDR(x))
#define HW_LCD_WF3_RD(x)         (HW_LCD_WF3(x).U)
#define HW_LCD_WF3_WR(x, v)      (HW_LCD_WF3(x).U = (v))
#define HW_LCD_WF3_SET(x, v)     (BME_OR8(HW_LCD_WF3_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF3_CLR(x, v)     (BME_AND8(HW_LCD_WF3_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF3_TOG(x, v)     (BME_XOR8(HW_LCD_WF3_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF3 bitfields
 */

/*!
 * @name Register LCD_WF3, field BPALCD3[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF3_BPALCD3   (0U)          /*!< Bit position for LCD_WF3_BPALCD3. */
#define BM_LCD_WF3_BPALCD3   (0x01U)       /*!< Bit mask for LCD_WF3_BPALCD3. */
#define BS_LCD_WF3_BPALCD3   (1U)          /*!< Bit field size in bits for LCD_WF3_BPALCD3. */

/*! @brief Read current value of the LCD_WF3_BPALCD3 field. */
#define BR_LCD_WF3_BPALCD3(x) (BME_UBFX8(HW_LCD_WF3_ADDR(x), BP_LCD_WF3_BPALCD3, BS_LCD_WF3_BPALCD3))

/*! @brief Format value for bitfield LCD_WF3_BPALCD3. */
#define BF_LCD_WF3_BPALCD3(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF3_BPALCD3) & BM_LCD_WF3_BPALCD3)

/*! @brief Set the BPALCD3 field to a new value. */
#define BW_LCD_WF3_BPALCD3(x, v) (BME_BFI8(HW_LCD_WF3_ADDR(x), ((uint8_t)(v) << BP_LCD_WF3_BPALCD3), BP_LCD_WF3_BPALCD3, 1))
/*@}*/

/*!
 * @name Register LCD_WF3, field BPBLCD3[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF3_BPBLCD3   (1U)          /*!< Bit position for LCD_WF3_BPBLCD3. */
#define BM_LCD_WF3_BPBLCD3   (0x02U)       /*!< Bit mask for LCD_WF3_BPBLCD3. */
#define BS_LCD_WF3_BPBLCD3   (1U)          /*!< Bit field size in bits for LCD_WF3_BPBLCD3. */

/*! @brief Read current value of the LCD_WF3_BPBLCD3 field. */
#define BR_LCD_WF3_BPBLCD3(x) (BME_UBFX8(HW_LCD_WF3_ADDR(x), BP_LCD_WF3_BPBLCD3, BS_LCD_WF3_BPBLCD3))

/*! @brief Format value for bitfield LCD_WF3_BPBLCD3. */
#define BF_LCD_WF3_BPBLCD3(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF3_BPBLCD3) & BM_LCD_WF3_BPBLCD3)

/*! @brief Set the BPBLCD3 field to a new value. */
#define BW_LCD_WF3_BPBLCD3(x, v) (BME_BFI8(HW_LCD_WF3_ADDR(x), ((uint8_t)(v) << BP_LCD_WF3_BPBLCD3), BP_LCD_WF3_BPBLCD3, 1))
/*@}*/

/*!
 * @name Register LCD_WF3, field BPCLCD3[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF3_BPCLCD3   (2U)          /*!< Bit position for LCD_WF3_BPCLCD3. */
#define BM_LCD_WF3_BPCLCD3   (0x04U)       /*!< Bit mask for LCD_WF3_BPCLCD3. */
#define BS_LCD_WF3_BPCLCD3   (1U)          /*!< Bit field size in bits for LCD_WF3_BPCLCD3. */

/*! @brief Read current value of the LCD_WF3_BPCLCD3 field. */
#define BR_LCD_WF3_BPCLCD3(x) (BME_UBFX8(HW_LCD_WF3_ADDR(x), BP_LCD_WF3_BPCLCD3, BS_LCD_WF3_BPCLCD3))

/*! @brief Format value for bitfield LCD_WF3_BPCLCD3. */
#define BF_LCD_WF3_BPCLCD3(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF3_BPCLCD3) & BM_LCD_WF3_BPCLCD3)

/*! @brief Set the BPCLCD3 field to a new value. */
#define BW_LCD_WF3_BPCLCD3(x, v) (BME_BFI8(HW_LCD_WF3_ADDR(x), ((uint8_t)(v) << BP_LCD_WF3_BPCLCD3), BP_LCD_WF3_BPCLCD3, 1))
/*@}*/

/*!
 * @name Register LCD_WF3, field BPDLCD3[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF3_BPDLCD3   (3U)          /*!< Bit position for LCD_WF3_BPDLCD3. */
#define BM_LCD_WF3_BPDLCD3   (0x08U)       /*!< Bit mask for LCD_WF3_BPDLCD3. */
#define BS_LCD_WF3_BPDLCD3   (1U)          /*!< Bit field size in bits for LCD_WF3_BPDLCD3. */

/*! @brief Read current value of the LCD_WF3_BPDLCD3 field. */
#define BR_LCD_WF3_BPDLCD3(x) (BME_UBFX8(HW_LCD_WF3_ADDR(x), BP_LCD_WF3_BPDLCD3, BS_LCD_WF3_BPDLCD3))

/*! @brief Format value for bitfield LCD_WF3_BPDLCD3. */
#define BF_LCD_WF3_BPDLCD3(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF3_BPDLCD3) & BM_LCD_WF3_BPDLCD3)

/*! @brief Set the BPDLCD3 field to a new value. */
#define BW_LCD_WF3_BPDLCD3(x, v) (BME_BFI8(HW_LCD_WF3_ADDR(x), ((uint8_t)(v) << BP_LCD_WF3_BPDLCD3), BP_LCD_WF3_BPDLCD3, 1))
/*@}*/

/*!
 * @name Register LCD_WF3, field BPELCD3[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF3_BPELCD3   (4U)          /*!< Bit position for LCD_WF3_BPELCD3. */
#define BM_LCD_WF3_BPELCD3   (0x10U)       /*!< Bit mask for LCD_WF3_BPELCD3. */
#define BS_LCD_WF3_BPELCD3   (1U)          /*!< Bit field size in bits for LCD_WF3_BPELCD3. */

/*! @brief Read current value of the LCD_WF3_BPELCD3 field. */
#define BR_LCD_WF3_BPELCD3(x) (BME_UBFX8(HW_LCD_WF3_ADDR(x), BP_LCD_WF3_BPELCD3, BS_LCD_WF3_BPELCD3))

/*! @brief Format value for bitfield LCD_WF3_BPELCD3. */
#define BF_LCD_WF3_BPELCD3(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF3_BPELCD3) & BM_LCD_WF3_BPELCD3)

/*! @brief Set the BPELCD3 field to a new value. */
#define BW_LCD_WF3_BPELCD3(x, v) (BME_BFI8(HW_LCD_WF3_ADDR(x), ((uint8_t)(v) << BP_LCD_WF3_BPELCD3), BP_LCD_WF3_BPELCD3, 1))
/*@}*/

/*!
 * @name Register LCD_WF3, field BPFLCD3[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF3_BPFLCD3   (5U)          /*!< Bit position for LCD_WF3_BPFLCD3. */
#define BM_LCD_WF3_BPFLCD3   (0x20U)       /*!< Bit mask for LCD_WF3_BPFLCD3. */
#define BS_LCD_WF3_BPFLCD3   (1U)          /*!< Bit field size in bits for LCD_WF3_BPFLCD3. */

/*! @brief Read current value of the LCD_WF3_BPFLCD3 field. */
#define BR_LCD_WF3_BPFLCD3(x) (BME_UBFX8(HW_LCD_WF3_ADDR(x), BP_LCD_WF3_BPFLCD3, BS_LCD_WF3_BPFLCD3))

/*! @brief Format value for bitfield LCD_WF3_BPFLCD3. */
#define BF_LCD_WF3_BPFLCD3(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF3_BPFLCD3) & BM_LCD_WF3_BPFLCD3)

/*! @brief Set the BPFLCD3 field to a new value. */
#define BW_LCD_WF3_BPFLCD3(x, v) (BME_BFI8(HW_LCD_WF3_ADDR(x), ((uint8_t)(v) << BP_LCD_WF3_BPFLCD3), BP_LCD_WF3_BPFLCD3, 1))
/*@}*/

/*!
 * @name Register LCD_WF3, field BPGLCD3[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF3_BPGLCD3   (6U)          /*!< Bit position for LCD_WF3_BPGLCD3. */
#define BM_LCD_WF3_BPGLCD3   (0x40U)       /*!< Bit mask for LCD_WF3_BPGLCD3. */
#define BS_LCD_WF3_BPGLCD3   (1U)          /*!< Bit field size in bits for LCD_WF3_BPGLCD3. */

/*! @brief Read current value of the LCD_WF3_BPGLCD3 field. */
#define BR_LCD_WF3_BPGLCD3(x) (BME_UBFX8(HW_LCD_WF3_ADDR(x), BP_LCD_WF3_BPGLCD3, BS_LCD_WF3_BPGLCD3))

/*! @brief Format value for bitfield LCD_WF3_BPGLCD3. */
#define BF_LCD_WF3_BPGLCD3(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF3_BPGLCD3) & BM_LCD_WF3_BPGLCD3)

/*! @brief Set the BPGLCD3 field to a new value. */
#define BW_LCD_WF3_BPGLCD3(x, v) (BME_BFI8(HW_LCD_WF3_ADDR(x), ((uint8_t)(v) << BP_LCD_WF3_BPGLCD3), BP_LCD_WF3_BPGLCD3, 1))
/*@}*/

/*!
 * @name Register LCD_WF3, field BPHLCD3[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF3_BPHLCD3   (7U)          /*!< Bit position for LCD_WF3_BPHLCD3. */
#define BM_LCD_WF3_BPHLCD3   (0x80U)       /*!< Bit mask for LCD_WF3_BPHLCD3. */
#define BS_LCD_WF3_BPHLCD3   (1U)          /*!< Bit field size in bits for LCD_WF3_BPHLCD3. */

/*! @brief Read current value of the LCD_WF3_BPHLCD3 field. */
#define BR_LCD_WF3_BPHLCD3(x) (BME_UBFX8(HW_LCD_WF3_ADDR(x), BP_LCD_WF3_BPHLCD3, BS_LCD_WF3_BPHLCD3))

/*! @brief Format value for bitfield LCD_WF3_BPHLCD3. */
#define BF_LCD_WF3_BPHLCD3(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF3_BPHLCD3) & BM_LCD_WF3_BPHLCD3)

/*! @brief Set the BPHLCD3 field to a new value. */
#define BW_LCD_WF3_BPHLCD3(x, v) (BME_BFI8(HW_LCD_WF3_ADDR(x), ((uint8_t)(v) << BP_LCD_WF3_BPHLCD3), BP_LCD_WF3_BPHLCD3, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF4 - LCD Waveform Register 4.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF4 - LCD Waveform Register 4. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf4
{
    uint8_t U;
    struct _hw_lcd_wf4_bitfields
    {
        uint8_t BPALCD4 : 1;           /*!< [0]  */
        uint8_t BPBLCD4 : 1;           /*!< [1]  */
        uint8_t BPCLCD4 : 1;           /*!< [2]  */
        uint8_t BPDLCD4 : 1;           /*!< [3]  */
        uint8_t BPELCD4 : 1;           /*!< [4]  */
        uint8_t BPFLCD4 : 1;           /*!< [5]  */
        uint8_t BPGLCD4 : 1;           /*!< [6]  */
        uint8_t BPHLCD4 : 1;           /*!< [7]  */
    } B;
} hw_lcd_wf4_t;

/*!
 * @name Constants and macros for entire LCD_WF4 register
 */
/*@{*/
#define HW_LCD_WF4_ADDR(x)       ((x) + 0x24U)

#define HW_LCD_WF4(x)            (*(__IO hw_lcd_wf4_t *) HW_LCD_WF4_ADDR(x))
#define HW_LCD_WF4_RD(x)         (HW_LCD_WF4(x).U)
#define HW_LCD_WF4_WR(x, v)      (HW_LCD_WF4(x).U = (v))
#define HW_LCD_WF4_SET(x, v)     (BME_OR8(HW_LCD_WF4_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF4_CLR(x, v)     (BME_AND8(HW_LCD_WF4_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF4_TOG(x, v)     (BME_XOR8(HW_LCD_WF4_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF4 bitfields
 */

/*!
 * @name Register LCD_WF4, field BPALCD4[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF4_BPALCD4   (0U)          /*!< Bit position for LCD_WF4_BPALCD4. */
#define BM_LCD_WF4_BPALCD4   (0x01U)       /*!< Bit mask for LCD_WF4_BPALCD4. */
#define BS_LCD_WF4_BPALCD4   (1U)          /*!< Bit field size in bits for LCD_WF4_BPALCD4. */

/*! @brief Read current value of the LCD_WF4_BPALCD4 field. */
#define BR_LCD_WF4_BPALCD4(x) (BME_UBFX8(HW_LCD_WF4_ADDR(x), BP_LCD_WF4_BPALCD4, BS_LCD_WF4_BPALCD4))

/*! @brief Format value for bitfield LCD_WF4_BPALCD4. */
#define BF_LCD_WF4_BPALCD4(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF4_BPALCD4) & BM_LCD_WF4_BPALCD4)

/*! @brief Set the BPALCD4 field to a new value. */
#define BW_LCD_WF4_BPALCD4(x, v) (BME_BFI8(HW_LCD_WF4_ADDR(x), ((uint8_t)(v) << BP_LCD_WF4_BPALCD4), BP_LCD_WF4_BPALCD4, 1))
/*@}*/

/*!
 * @name Register LCD_WF4, field BPBLCD4[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF4_BPBLCD4   (1U)          /*!< Bit position for LCD_WF4_BPBLCD4. */
#define BM_LCD_WF4_BPBLCD4   (0x02U)       /*!< Bit mask for LCD_WF4_BPBLCD4. */
#define BS_LCD_WF4_BPBLCD4   (1U)          /*!< Bit field size in bits for LCD_WF4_BPBLCD4. */

/*! @brief Read current value of the LCD_WF4_BPBLCD4 field. */
#define BR_LCD_WF4_BPBLCD4(x) (BME_UBFX8(HW_LCD_WF4_ADDR(x), BP_LCD_WF4_BPBLCD4, BS_LCD_WF4_BPBLCD4))

/*! @brief Format value for bitfield LCD_WF4_BPBLCD4. */
#define BF_LCD_WF4_BPBLCD4(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF4_BPBLCD4) & BM_LCD_WF4_BPBLCD4)

/*! @brief Set the BPBLCD4 field to a new value. */
#define BW_LCD_WF4_BPBLCD4(x, v) (BME_BFI8(HW_LCD_WF4_ADDR(x), ((uint8_t)(v) << BP_LCD_WF4_BPBLCD4), BP_LCD_WF4_BPBLCD4, 1))
/*@}*/

/*!
 * @name Register LCD_WF4, field BPCLCD4[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF4_BPCLCD4   (2U)          /*!< Bit position for LCD_WF4_BPCLCD4. */
#define BM_LCD_WF4_BPCLCD4   (0x04U)       /*!< Bit mask for LCD_WF4_BPCLCD4. */
#define BS_LCD_WF4_BPCLCD4   (1U)          /*!< Bit field size in bits for LCD_WF4_BPCLCD4. */

/*! @brief Read current value of the LCD_WF4_BPCLCD4 field. */
#define BR_LCD_WF4_BPCLCD4(x) (BME_UBFX8(HW_LCD_WF4_ADDR(x), BP_LCD_WF4_BPCLCD4, BS_LCD_WF4_BPCLCD4))

/*! @brief Format value for bitfield LCD_WF4_BPCLCD4. */
#define BF_LCD_WF4_BPCLCD4(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF4_BPCLCD4) & BM_LCD_WF4_BPCLCD4)

/*! @brief Set the BPCLCD4 field to a new value. */
#define BW_LCD_WF4_BPCLCD4(x, v) (BME_BFI8(HW_LCD_WF4_ADDR(x), ((uint8_t)(v) << BP_LCD_WF4_BPCLCD4), BP_LCD_WF4_BPCLCD4, 1))
/*@}*/

/*!
 * @name Register LCD_WF4, field BPDLCD4[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF4_BPDLCD4   (3U)          /*!< Bit position for LCD_WF4_BPDLCD4. */
#define BM_LCD_WF4_BPDLCD4   (0x08U)       /*!< Bit mask for LCD_WF4_BPDLCD4. */
#define BS_LCD_WF4_BPDLCD4   (1U)          /*!< Bit field size in bits for LCD_WF4_BPDLCD4. */

/*! @brief Read current value of the LCD_WF4_BPDLCD4 field. */
#define BR_LCD_WF4_BPDLCD4(x) (BME_UBFX8(HW_LCD_WF4_ADDR(x), BP_LCD_WF4_BPDLCD4, BS_LCD_WF4_BPDLCD4))

/*! @brief Format value for bitfield LCD_WF4_BPDLCD4. */
#define BF_LCD_WF4_BPDLCD4(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF4_BPDLCD4) & BM_LCD_WF4_BPDLCD4)

/*! @brief Set the BPDLCD4 field to a new value. */
#define BW_LCD_WF4_BPDLCD4(x, v) (BME_BFI8(HW_LCD_WF4_ADDR(x), ((uint8_t)(v) << BP_LCD_WF4_BPDLCD4), BP_LCD_WF4_BPDLCD4, 1))
/*@}*/

/*!
 * @name Register LCD_WF4, field BPELCD4[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF4_BPELCD4   (4U)          /*!< Bit position for LCD_WF4_BPELCD4. */
#define BM_LCD_WF4_BPELCD4   (0x10U)       /*!< Bit mask for LCD_WF4_BPELCD4. */
#define BS_LCD_WF4_BPELCD4   (1U)          /*!< Bit field size in bits for LCD_WF4_BPELCD4. */

/*! @brief Read current value of the LCD_WF4_BPELCD4 field. */
#define BR_LCD_WF4_BPELCD4(x) (BME_UBFX8(HW_LCD_WF4_ADDR(x), BP_LCD_WF4_BPELCD4, BS_LCD_WF4_BPELCD4))

/*! @brief Format value for bitfield LCD_WF4_BPELCD4. */
#define BF_LCD_WF4_BPELCD4(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF4_BPELCD4) & BM_LCD_WF4_BPELCD4)

/*! @brief Set the BPELCD4 field to a new value. */
#define BW_LCD_WF4_BPELCD4(x, v) (BME_BFI8(HW_LCD_WF4_ADDR(x), ((uint8_t)(v) << BP_LCD_WF4_BPELCD4), BP_LCD_WF4_BPELCD4, 1))
/*@}*/

/*!
 * @name Register LCD_WF4, field BPFLCD4[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF4_BPFLCD4   (5U)          /*!< Bit position for LCD_WF4_BPFLCD4. */
#define BM_LCD_WF4_BPFLCD4   (0x20U)       /*!< Bit mask for LCD_WF4_BPFLCD4. */
#define BS_LCD_WF4_BPFLCD4   (1U)          /*!< Bit field size in bits for LCD_WF4_BPFLCD4. */

/*! @brief Read current value of the LCD_WF4_BPFLCD4 field. */
#define BR_LCD_WF4_BPFLCD4(x) (BME_UBFX8(HW_LCD_WF4_ADDR(x), BP_LCD_WF4_BPFLCD4, BS_LCD_WF4_BPFLCD4))

/*! @brief Format value for bitfield LCD_WF4_BPFLCD4. */
#define BF_LCD_WF4_BPFLCD4(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF4_BPFLCD4) & BM_LCD_WF4_BPFLCD4)

/*! @brief Set the BPFLCD4 field to a new value. */
#define BW_LCD_WF4_BPFLCD4(x, v) (BME_BFI8(HW_LCD_WF4_ADDR(x), ((uint8_t)(v) << BP_LCD_WF4_BPFLCD4), BP_LCD_WF4_BPFLCD4, 1))
/*@}*/

/*!
 * @name Register LCD_WF4, field BPGLCD4[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF4_BPGLCD4   (6U)          /*!< Bit position for LCD_WF4_BPGLCD4. */
#define BM_LCD_WF4_BPGLCD4   (0x40U)       /*!< Bit mask for LCD_WF4_BPGLCD4. */
#define BS_LCD_WF4_BPGLCD4   (1U)          /*!< Bit field size in bits for LCD_WF4_BPGLCD4. */

/*! @brief Read current value of the LCD_WF4_BPGLCD4 field. */
#define BR_LCD_WF4_BPGLCD4(x) (BME_UBFX8(HW_LCD_WF4_ADDR(x), BP_LCD_WF4_BPGLCD4, BS_LCD_WF4_BPGLCD4))

/*! @brief Format value for bitfield LCD_WF4_BPGLCD4. */
#define BF_LCD_WF4_BPGLCD4(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF4_BPGLCD4) & BM_LCD_WF4_BPGLCD4)

/*! @brief Set the BPGLCD4 field to a new value. */
#define BW_LCD_WF4_BPGLCD4(x, v) (BME_BFI8(HW_LCD_WF4_ADDR(x), ((uint8_t)(v) << BP_LCD_WF4_BPGLCD4), BP_LCD_WF4_BPGLCD4, 1))
/*@}*/

/*!
 * @name Register LCD_WF4, field BPHLCD4[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF4_BPHLCD4   (7U)          /*!< Bit position for LCD_WF4_BPHLCD4. */
#define BM_LCD_WF4_BPHLCD4   (0x80U)       /*!< Bit mask for LCD_WF4_BPHLCD4. */
#define BS_LCD_WF4_BPHLCD4   (1U)          /*!< Bit field size in bits for LCD_WF4_BPHLCD4. */

/*! @brief Read current value of the LCD_WF4_BPHLCD4 field. */
#define BR_LCD_WF4_BPHLCD4(x) (BME_UBFX8(HW_LCD_WF4_ADDR(x), BP_LCD_WF4_BPHLCD4, BS_LCD_WF4_BPHLCD4))

/*! @brief Format value for bitfield LCD_WF4_BPHLCD4. */
#define BF_LCD_WF4_BPHLCD4(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF4_BPHLCD4) & BM_LCD_WF4_BPHLCD4)

/*! @brief Set the BPHLCD4 field to a new value. */
#define BW_LCD_WF4_BPHLCD4(x, v) (BME_BFI8(HW_LCD_WF4_ADDR(x), ((uint8_t)(v) << BP_LCD_WF4_BPHLCD4), BP_LCD_WF4_BPHLCD4, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF5 - LCD Waveform Register 5.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF5 - LCD Waveform Register 5. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf5
{
    uint8_t U;
    struct _hw_lcd_wf5_bitfields
    {
        uint8_t BPALCD5 : 1;           /*!< [0]  */
        uint8_t BPBLCD5 : 1;           /*!< [1]  */
        uint8_t BPCLCD5 : 1;           /*!< [2]  */
        uint8_t BPDLCD5 : 1;           /*!< [3]  */
        uint8_t BPELCD5 : 1;           /*!< [4]  */
        uint8_t BPFLCD5 : 1;           /*!< [5]  */
        uint8_t BPGLCD5 : 1;           /*!< [6]  */
        uint8_t BPHLCD5 : 1;           /*!< [7]  */
    } B;
} hw_lcd_wf5_t;

/*!
 * @name Constants and macros for entire LCD_WF5 register
 */
/*@{*/
#define HW_LCD_WF5_ADDR(x)       ((x) + 0x25U)

#define HW_LCD_WF5(x)            (*(__IO hw_lcd_wf5_t *) HW_LCD_WF5_ADDR(x))
#define HW_LCD_WF5_RD(x)         (HW_LCD_WF5(x).U)
#define HW_LCD_WF5_WR(x, v)      (HW_LCD_WF5(x).U = (v))
#define HW_LCD_WF5_SET(x, v)     (BME_OR8(HW_LCD_WF5_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF5_CLR(x, v)     (BME_AND8(HW_LCD_WF5_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF5_TOG(x, v)     (BME_XOR8(HW_LCD_WF5_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF5 bitfields
 */

/*!
 * @name Register LCD_WF5, field BPALCD5[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF5_BPALCD5   (0U)          /*!< Bit position for LCD_WF5_BPALCD5. */
#define BM_LCD_WF5_BPALCD5   (0x01U)       /*!< Bit mask for LCD_WF5_BPALCD5. */
#define BS_LCD_WF5_BPALCD5   (1U)          /*!< Bit field size in bits for LCD_WF5_BPALCD5. */

/*! @brief Read current value of the LCD_WF5_BPALCD5 field. */
#define BR_LCD_WF5_BPALCD5(x) (BME_UBFX8(HW_LCD_WF5_ADDR(x), BP_LCD_WF5_BPALCD5, BS_LCD_WF5_BPALCD5))

/*! @brief Format value for bitfield LCD_WF5_BPALCD5. */
#define BF_LCD_WF5_BPALCD5(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF5_BPALCD5) & BM_LCD_WF5_BPALCD5)

/*! @brief Set the BPALCD5 field to a new value. */
#define BW_LCD_WF5_BPALCD5(x, v) (BME_BFI8(HW_LCD_WF5_ADDR(x), ((uint8_t)(v) << BP_LCD_WF5_BPALCD5), BP_LCD_WF5_BPALCD5, 1))
/*@}*/

/*!
 * @name Register LCD_WF5, field BPBLCD5[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF5_BPBLCD5   (1U)          /*!< Bit position for LCD_WF5_BPBLCD5. */
#define BM_LCD_WF5_BPBLCD5   (0x02U)       /*!< Bit mask for LCD_WF5_BPBLCD5. */
#define BS_LCD_WF5_BPBLCD5   (1U)          /*!< Bit field size in bits for LCD_WF5_BPBLCD5. */

/*! @brief Read current value of the LCD_WF5_BPBLCD5 field. */
#define BR_LCD_WF5_BPBLCD5(x) (BME_UBFX8(HW_LCD_WF5_ADDR(x), BP_LCD_WF5_BPBLCD5, BS_LCD_WF5_BPBLCD5))

/*! @brief Format value for bitfield LCD_WF5_BPBLCD5. */
#define BF_LCD_WF5_BPBLCD5(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF5_BPBLCD5) & BM_LCD_WF5_BPBLCD5)

/*! @brief Set the BPBLCD5 field to a new value. */
#define BW_LCD_WF5_BPBLCD5(x, v) (BME_BFI8(HW_LCD_WF5_ADDR(x), ((uint8_t)(v) << BP_LCD_WF5_BPBLCD5), BP_LCD_WF5_BPBLCD5, 1))
/*@}*/

/*!
 * @name Register LCD_WF5, field BPCLCD5[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF5_BPCLCD5   (2U)          /*!< Bit position for LCD_WF5_BPCLCD5. */
#define BM_LCD_WF5_BPCLCD5   (0x04U)       /*!< Bit mask for LCD_WF5_BPCLCD5. */
#define BS_LCD_WF5_BPCLCD5   (1U)          /*!< Bit field size in bits for LCD_WF5_BPCLCD5. */

/*! @brief Read current value of the LCD_WF5_BPCLCD5 field. */
#define BR_LCD_WF5_BPCLCD5(x) (BME_UBFX8(HW_LCD_WF5_ADDR(x), BP_LCD_WF5_BPCLCD5, BS_LCD_WF5_BPCLCD5))

/*! @brief Format value for bitfield LCD_WF5_BPCLCD5. */
#define BF_LCD_WF5_BPCLCD5(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF5_BPCLCD5) & BM_LCD_WF5_BPCLCD5)

/*! @brief Set the BPCLCD5 field to a new value. */
#define BW_LCD_WF5_BPCLCD5(x, v) (BME_BFI8(HW_LCD_WF5_ADDR(x), ((uint8_t)(v) << BP_LCD_WF5_BPCLCD5), BP_LCD_WF5_BPCLCD5, 1))
/*@}*/

/*!
 * @name Register LCD_WF5, field BPDLCD5[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF5_BPDLCD5   (3U)          /*!< Bit position for LCD_WF5_BPDLCD5. */
#define BM_LCD_WF5_BPDLCD5   (0x08U)       /*!< Bit mask for LCD_WF5_BPDLCD5. */
#define BS_LCD_WF5_BPDLCD5   (1U)          /*!< Bit field size in bits for LCD_WF5_BPDLCD5. */

/*! @brief Read current value of the LCD_WF5_BPDLCD5 field. */
#define BR_LCD_WF5_BPDLCD5(x) (BME_UBFX8(HW_LCD_WF5_ADDR(x), BP_LCD_WF5_BPDLCD5, BS_LCD_WF5_BPDLCD5))

/*! @brief Format value for bitfield LCD_WF5_BPDLCD5. */
#define BF_LCD_WF5_BPDLCD5(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF5_BPDLCD5) & BM_LCD_WF5_BPDLCD5)

/*! @brief Set the BPDLCD5 field to a new value. */
#define BW_LCD_WF5_BPDLCD5(x, v) (BME_BFI8(HW_LCD_WF5_ADDR(x), ((uint8_t)(v) << BP_LCD_WF5_BPDLCD5), BP_LCD_WF5_BPDLCD5, 1))
/*@}*/

/*!
 * @name Register LCD_WF5, field BPELCD5[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF5_BPELCD5   (4U)          /*!< Bit position for LCD_WF5_BPELCD5. */
#define BM_LCD_WF5_BPELCD5   (0x10U)       /*!< Bit mask for LCD_WF5_BPELCD5. */
#define BS_LCD_WF5_BPELCD5   (1U)          /*!< Bit field size in bits for LCD_WF5_BPELCD5. */

/*! @brief Read current value of the LCD_WF5_BPELCD5 field. */
#define BR_LCD_WF5_BPELCD5(x) (BME_UBFX8(HW_LCD_WF5_ADDR(x), BP_LCD_WF5_BPELCD5, BS_LCD_WF5_BPELCD5))

/*! @brief Format value for bitfield LCD_WF5_BPELCD5. */
#define BF_LCD_WF5_BPELCD5(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF5_BPELCD5) & BM_LCD_WF5_BPELCD5)

/*! @brief Set the BPELCD5 field to a new value. */
#define BW_LCD_WF5_BPELCD5(x, v) (BME_BFI8(HW_LCD_WF5_ADDR(x), ((uint8_t)(v) << BP_LCD_WF5_BPELCD5), BP_LCD_WF5_BPELCD5, 1))
/*@}*/

/*!
 * @name Register LCD_WF5, field BPFLCD5[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF5_BPFLCD5   (5U)          /*!< Bit position for LCD_WF5_BPFLCD5. */
#define BM_LCD_WF5_BPFLCD5   (0x20U)       /*!< Bit mask for LCD_WF5_BPFLCD5. */
#define BS_LCD_WF5_BPFLCD5   (1U)          /*!< Bit field size in bits for LCD_WF5_BPFLCD5. */

/*! @brief Read current value of the LCD_WF5_BPFLCD5 field. */
#define BR_LCD_WF5_BPFLCD5(x) (BME_UBFX8(HW_LCD_WF5_ADDR(x), BP_LCD_WF5_BPFLCD5, BS_LCD_WF5_BPFLCD5))

/*! @brief Format value for bitfield LCD_WF5_BPFLCD5. */
#define BF_LCD_WF5_BPFLCD5(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF5_BPFLCD5) & BM_LCD_WF5_BPFLCD5)

/*! @brief Set the BPFLCD5 field to a new value. */
#define BW_LCD_WF5_BPFLCD5(x, v) (BME_BFI8(HW_LCD_WF5_ADDR(x), ((uint8_t)(v) << BP_LCD_WF5_BPFLCD5), BP_LCD_WF5_BPFLCD5, 1))
/*@}*/

/*!
 * @name Register LCD_WF5, field BPGLCD5[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF5_BPGLCD5   (6U)          /*!< Bit position for LCD_WF5_BPGLCD5. */
#define BM_LCD_WF5_BPGLCD5   (0x40U)       /*!< Bit mask for LCD_WF5_BPGLCD5. */
#define BS_LCD_WF5_BPGLCD5   (1U)          /*!< Bit field size in bits for LCD_WF5_BPGLCD5. */

/*! @brief Read current value of the LCD_WF5_BPGLCD5 field. */
#define BR_LCD_WF5_BPGLCD5(x) (BME_UBFX8(HW_LCD_WF5_ADDR(x), BP_LCD_WF5_BPGLCD5, BS_LCD_WF5_BPGLCD5))

/*! @brief Format value for bitfield LCD_WF5_BPGLCD5. */
#define BF_LCD_WF5_BPGLCD5(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF5_BPGLCD5) & BM_LCD_WF5_BPGLCD5)

/*! @brief Set the BPGLCD5 field to a new value. */
#define BW_LCD_WF5_BPGLCD5(x, v) (BME_BFI8(HW_LCD_WF5_ADDR(x), ((uint8_t)(v) << BP_LCD_WF5_BPGLCD5), BP_LCD_WF5_BPGLCD5, 1))
/*@}*/

/*!
 * @name Register LCD_WF5, field BPHLCD5[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF5_BPHLCD5   (7U)          /*!< Bit position for LCD_WF5_BPHLCD5. */
#define BM_LCD_WF5_BPHLCD5   (0x80U)       /*!< Bit mask for LCD_WF5_BPHLCD5. */
#define BS_LCD_WF5_BPHLCD5   (1U)          /*!< Bit field size in bits for LCD_WF5_BPHLCD5. */

/*! @brief Read current value of the LCD_WF5_BPHLCD5 field. */
#define BR_LCD_WF5_BPHLCD5(x) (BME_UBFX8(HW_LCD_WF5_ADDR(x), BP_LCD_WF5_BPHLCD5, BS_LCD_WF5_BPHLCD5))

/*! @brief Format value for bitfield LCD_WF5_BPHLCD5. */
#define BF_LCD_WF5_BPHLCD5(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF5_BPHLCD5) & BM_LCD_WF5_BPHLCD5)

/*! @brief Set the BPHLCD5 field to a new value. */
#define BW_LCD_WF5_BPHLCD5(x, v) (BME_BFI8(HW_LCD_WF5_ADDR(x), ((uint8_t)(v) << BP_LCD_WF5_BPHLCD5), BP_LCD_WF5_BPHLCD5, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF6 - LCD Waveform Register 6.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF6 - LCD Waveform Register 6. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf6
{
    uint8_t U;
    struct _hw_lcd_wf6_bitfields
    {
        uint8_t BPALCD6 : 1;           /*!< [0]  */
        uint8_t BPBLCD6 : 1;           /*!< [1]  */
        uint8_t BPCLCD6 : 1;           /*!< [2]  */
        uint8_t BPDLCD6 : 1;           /*!< [3]  */
        uint8_t BPELCD6 : 1;           /*!< [4]  */
        uint8_t BPFLCD6 : 1;           /*!< [5]  */
        uint8_t BPGLCD6 : 1;           /*!< [6]  */
        uint8_t BPHLCD6 : 1;           /*!< [7]  */
    } B;
} hw_lcd_wf6_t;

/*!
 * @name Constants and macros for entire LCD_WF6 register
 */
/*@{*/
#define HW_LCD_WF6_ADDR(x)       ((x) + 0x26U)

#define HW_LCD_WF6(x)            (*(__IO hw_lcd_wf6_t *) HW_LCD_WF6_ADDR(x))
#define HW_LCD_WF6_RD(x)         (HW_LCD_WF6(x).U)
#define HW_LCD_WF6_WR(x, v)      (HW_LCD_WF6(x).U = (v))
#define HW_LCD_WF6_SET(x, v)     (BME_OR8(HW_LCD_WF6_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF6_CLR(x, v)     (BME_AND8(HW_LCD_WF6_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF6_TOG(x, v)     (BME_XOR8(HW_LCD_WF6_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF6 bitfields
 */

/*!
 * @name Register LCD_WF6, field BPALCD6[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF6_BPALCD6   (0U)          /*!< Bit position for LCD_WF6_BPALCD6. */
#define BM_LCD_WF6_BPALCD6   (0x01U)       /*!< Bit mask for LCD_WF6_BPALCD6. */
#define BS_LCD_WF6_BPALCD6   (1U)          /*!< Bit field size in bits for LCD_WF6_BPALCD6. */

/*! @brief Read current value of the LCD_WF6_BPALCD6 field. */
#define BR_LCD_WF6_BPALCD6(x) (BME_UBFX8(HW_LCD_WF6_ADDR(x), BP_LCD_WF6_BPALCD6, BS_LCD_WF6_BPALCD6))

/*! @brief Format value for bitfield LCD_WF6_BPALCD6. */
#define BF_LCD_WF6_BPALCD6(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF6_BPALCD6) & BM_LCD_WF6_BPALCD6)

/*! @brief Set the BPALCD6 field to a new value. */
#define BW_LCD_WF6_BPALCD6(x, v) (BME_BFI8(HW_LCD_WF6_ADDR(x), ((uint8_t)(v) << BP_LCD_WF6_BPALCD6), BP_LCD_WF6_BPALCD6, 1))
/*@}*/

/*!
 * @name Register LCD_WF6, field BPBLCD6[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF6_BPBLCD6   (1U)          /*!< Bit position for LCD_WF6_BPBLCD6. */
#define BM_LCD_WF6_BPBLCD6   (0x02U)       /*!< Bit mask for LCD_WF6_BPBLCD6. */
#define BS_LCD_WF6_BPBLCD6   (1U)          /*!< Bit field size in bits for LCD_WF6_BPBLCD6. */

/*! @brief Read current value of the LCD_WF6_BPBLCD6 field. */
#define BR_LCD_WF6_BPBLCD6(x) (BME_UBFX8(HW_LCD_WF6_ADDR(x), BP_LCD_WF6_BPBLCD6, BS_LCD_WF6_BPBLCD6))

/*! @brief Format value for bitfield LCD_WF6_BPBLCD6. */
#define BF_LCD_WF6_BPBLCD6(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF6_BPBLCD6) & BM_LCD_WF6_BPBLCD6)

/*! @brief Set the BPBLCD6 field to a new value. */
#define BW_LCD_WF6_BPBLCD6(x, v) (BME_BFI8(HW_LCD_WF6_ADDR(x), ((uint8_t)(v) << BP_LCD_WF6_BPBLCD6), BP_LCD_WF6_BPBLCD6, 1))
/*@}*/

/*!
 * @name Register LCD_WF6, field BPCLCD6[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF6_BPCLCD6   (2U)          /*!< Bit position for LCD_WF6_BPCLCD6. */
#define BM_LCD_WF6_BPCLCD6   (0x04U)       /*!< Bit mask for LCD_WF6_BPCLCD6. */
#define BS_LCD_WF6_BPCLCD6   (1U)          /*!< Bit field size in bits for LCD_WF6_BPCLCD6. */

/*! @brief Read current value of the LCD_WF6_BPCLCD6 field. */
#define BR_LCD_WF6_BPCLCD6(x) (BME_UBFX8(HW_LCD_WF6_ADDR(x), BP_LCD_WF6_BPCLCD6, BS_LCD_WF6_BPCLCD6))

/*! @brief Format value for bitfield LCD_WF6_BPCLCD6. */
#define BF_LCD_WF6_BPCLCD6(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF6_BPCLCD6) & BM_LCD_WF6_BPCLCD6)

/*! @brief Set the BPCLCD6 field to a new value. */
#define BW_LCD_WF6_BPCLCD6(x, v) (BME_BFI8(HW_LCD_WF6_ADDR(x), ((uint8_t)(v) << BP_LCD_WF6_BPCLCD6), BP_LCD_WF6_BPCLCD6, 1))
/*@}*/

/*!
 * @name Register LCD_WF6, field BPDLCD6[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF6_BPDLCD6   (3U)          /*!< Bit position for LCD_WF6_BPDLCD6. */
#define BM_LCD_WF6_BPDLCD6   (0x08U)       /*!< Bit mask for LCD_WF6_BPDLCD6. */
#define BS_LCD_WF6_BPDLCD6   (1U)          /*!< Bit field size in bits for LCD_WF6_BPDLCD6. */

/*! @brief Read current value of the LCD_WF6_BPDLCD6 field. */
#define BR_LCD_WF6_BPDLCD6(x) (BME_UBFX8(HW_LCD_WF6_ADDR(x), BP_LCD_WF6_BPDLCD6, BS_LCD_WF6_BPDLCD6))

/*! @brief Format value for bitfield LCD_WF6_BPDLCD6. */
#define BF_LCD_WF6_BPDLCD6(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF6_BPDLCD6) & BM_LCD_WF6_BPDLCD6)

/*! @brief Set the BPDLCD6 field to a new value. */
#define BW_LCD_WF6_BPDLCD6(x, v) (BME_BFI8(HW_LCD_WF6_ADDR(x), ((uint8_t)(v) << BP_LCD_WF6_BPDLCD6), BP_LCD_WF6_BPDLCD6, 1))
/*@}*/

/*!
 * @name Register LCD_WF6, field BPELCD6[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF6_BPELCD6   (4U)          /*!< Bit position for LCD_WF6_BPELCD6. */
#define BM_LCD_WF6_BPELCD6   (0x10U)       /*!< Bit mask for LCD_WF6_BPELCD6. */
#define BS_LCD_WF6_BPELCD6   (1U)          /*!< Bit field size in bits for LCD_WF6_BPELCD6. */

/*! @brief Read current value of the LCD_WF6_BPELCD6 field. */
#define BR_LCD_WF6_BPELCD6(x) (BME_UBFX8(HW_LCD_WF6_ADDR(x), BP_LCD_WF6_BPELCD6, BS_LCD_WF6_BPELCD6))

/*! @brief Format value for bitfield LCD_WF6_BPELCD6. */
#define BF_LCD_WF6_BPELCD6(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF6_BPELCD6) & BM_LCD_WF6_BPELCD6)

/*! @brief Set the BPELCD6 field to a new value. */
#define BW_LCD_WF6_BPELCD6(x, v) (BME_BFI8(HW_LCD_WF6_ADDR(x), ((uint8_t)(v) << BP_LCD_WF6_BPELCD6), BP_LCD_WF6_BPELCD6, 1))
/*@}*/

/*!
 * @name Register LCD_WF6, field BPFLCD6[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF6_BPFLCD6   (5U)          /*!< Bit position for LCD_WF6_BPFLCD6. */
#define BM_LCD_WF6_BPFLCD6   (0x20U)       /*!< Bit mask for LCD_WF6_BPFLCD6. */
#define BS_LCD_WF6_BPFLCD6   (1U)          /*!< Bit field size in bits for LCD_WF6_BPFLCD6. */

/*! @brief Read current value of the LCD_WF6_BPFLCD6 field. */
#define BR_LCD_WF6_BPFLCD6(x) (BME_UBFX8(HW_LCD_WF6_ADDR(x), BP_LCD_WF6_BPFLCD6, BS_LCD_WF6_BPFLCD6))

/*! @brief Format value for bitfield LCD_WF6_BPFLCD6. */
#define BF_LCD_WF6_BPFLCD6(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF6_BPFLCD6) & BM_LCD_WF6_BPFLCD6)

/*! @brief Set the BPFLCD6 field to a new value. */
#define BW_LCD_WF6_BPFLCD6(x, v) (BME_BFI8(HW_LCD_WF6_ADDR(x), ((uint8_t)(v) << BP_LCD_WF6_BPFLCD6), BP_LCD_WF6_BPFLCD6, 1))
/*@}*/

/*!
 * @name Register LCD_WF6, field BPGLCD6[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF6_BPGLCD6   (6U)          /*!< Bit position for LCD_WF6_BPGLCD6. */
#define BM_LCD_WF6_BPGLCD6   (0x40U)       /*!< Bit mask for LCD_WF6_BPGLCD6. */
#define BS_LCD_WF6_BPGLCD6   (1U)          /*!< Bit field size in bits for LCD_WF6_BPGLCD6. */

/*! @brief Read current value of the LCD_WF6_BPGLCD6 field. */
#define BR_LCD_WF6_BPGLCD6(x) (BME_UBFX8(HW_LCD_WF6_ADDR(x), BP_LCD_WF6_BPGLCD6, BS_LCD_WF6_BPGLCD6))

/*! @brief Format value for bitfield LCD_WF6_BPGLCD6. */
#define BF_LCD_WF6_BPGLCD6(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF6_BPGLCD6) & BM_LCD_WF6_BPGLCD6)

/*! @brief Set the BPGLCD6 field to a new value. */
#define BW_LCD_WF6_BPGLCD6(x, v) (BME_BFI8(HW_LCD_WF6_ADDR(x), ((uint8_t)(v) << BP_LCD_WF6_BPGLCD6), BP_LCD_WF6_BPGLCD6, 1))
/*@}*/

/*!
 * @name Register LCD_WF6, field BPHLCD6[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF6_BPHLCD6   (7U)          /*!< Bit position for LCD_WF6_BPHLCD6. */
#define BM_LCD_WF6_BPHLCD6   (0x80U)       /*!< Bit mask for LCD_WF6_BPHLCD6. */
#define BS_LCD_WF6_BPHLCD6   (1U)          /*!< Bit field size in bits for LCD_WF6_BPHLCD6. */

/*! @brief Read current value of the LCD_WF6_BPHLCD6 field. */
#define BR_LCD_WF6_BPHLCD6(x) (BME_UBFX8(HW_LCD_WF6_ADDR(x), BP_LCD_WF6_BPHLCD6, BS_LCD_WF6_BPHLCD6))

/*! @brief Format value for bitfield LCD_WF6_BPHLCD6. */
#define BF_LCD_WF6_BPHLCD6(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF6_BPHLCD6) & BM_LCD_WF6_BPHLCD6)

/*! @brief Set the BPHLCD6 field to a new value. */
#define BW_LCD_WF6_BPHLCD6(x, v) (BME_BFI8(HW_LCD_WF6_ADDR(x), ((uint8_t)(v) << BP_LCD_WF6_BPHLCD6), BP_LCD_WF6_BPHLCD6, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF7 - LCD Waveform Register 7.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF7 - LCD Waveform Register 7. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf7
{
    uint8_t U;
    struct _hw_lcd_wf7_bitfields
    {
        uint8_t BPALCD7 : 1;           /*!< [0]  */
        uint8_t BPBLCD7 : 1;           /*!< [1]  */
        uint8_t BPCLCD7 : 1;           /*!< [2]  */
        uint8_t BPDLCD7 : 1;           /*!< [3]  */
        uint8_t BPELCD7 : 1;           /*!< [4]  */
        uint8_t BPFLCD7 : 1;           /*!< [5]  */
        uint8_t BPGLCD7 : 1;           /*!< [6]  */
        uint8_t BPHLCD7 : 1;           /*!< [7]  */
    } B;
} hw_lcd_wf7_t;

/*!
 * @name Constants and macros for entire LCD_WF7 register
 */
/*@{*/
#define HW_LCD_WF7_ADDR(x)       ((x) + 0x27U)

#define HW_LCD_WF7(x)            (*(__IO hw_lcd_wf7_t *) HW_LCD_WF7_ADDR(x))
#define HW_LCD_WF7_RD(x)         (HW_LCD_WF7(x).U)
#define HW_LCD_WF7_WR(x, v)      (HW_LCD_WF7(x).U = (v))
#define HW_LCD_WF7_SET(x, v)     (BME_OR8(HW_LCD_WF7_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF7_CLR(x, v)     (BME_AND8(HW_LCD_WF7_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF7_TOG(x, v)     (BME_XOR8(HW_LCD_WF7_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF7 bitfields
 */

/*!
 * @name Register LCD_WF7, field BPALCD7[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF7_BPALCD7   (0U)          /*!< Bit position for LCD_WF7_BPALCD7. */
#define BM_LCD_WF7_BPALCD7   (0x01U)       /*!< Bit mask for LCD_WF7_BPALCD7. */
#define BS_LCD_WF7_BPALCD7   (1U)          /*!< Bit field size in bits for LCD_WF7_BPALCD7. */

/*! @brief Read current value of the LCD_WF7_BPALCD7 field. */
#define BR_LCD_WF7_BPALCD7(x) (BME_UBFX8(HW_LCD_WF7_ADDR(x), BP_LCD_WF7_BPALCD7, BS_LCD_WF7_BPALCD7))

/*! @brief Format value for bitfield LCD_WF7_BPALCD7. */
#define BF_LCD_WF7_BPALCD7(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF7_BPALCD7) & BM_LCD_WF7_BPALCD7)

/*! @brief Set the BPALCD7 field to a new value. */
#define BW_LCD_WF7_BPALCD7(x, v) (BME_BFI8(HW_LCD_WF7_ADDR(x), ((uint8_t)(v) << BP_LCD_WF7_BPALCD7), BP_LCD_WF7_BPALCD7, 1))
/*@}*/

/*!
 * @name Register LCD_WF7, field BPBLCD7[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF7_BPBLCD7   (1U)          /*!< Bit position for LCD_WF7_BPBLCD7. */
#define BM_LCD_WF7_BPBLCD7   (0x02U)       /*!< Bit mask for LCD_WF7_BPBLCD7. */
#define BS_LCD_WF7_BPBLCD7   (1U)          /*!< Bit field size in bits for LCD_WF7_BPBLCD7. */

/*! @brief Read current value of the LCD_WF7_BPBLCD7 field. */
#define BR_LCD_WF7_BPBLCD7(x) (BME_UBFX8(HW_LCD_WF7_ADDR(x), BP_LCD_WF7_BPBLCD7, BS_LCD_WF7_BPBLCD7))

/*! @brief Format value for bitfield LCD_WF7_BPBLCD7. */
#define BF_LCD_WF7_BPBLCD7(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF7_BPBLCD7) & BM_LCD_WF7_BPBLCD7)

/*! @brief Set the BPBLCD7 field to a new value. */
#define BW_LCD_WF7_BPBLCD7(x, v) (BME_BFI8(HW_LCD_WF7_ADDR(x), ((uint8_t)(v) << BP_LCD_WF7_BPBLCD7), BP_LCD_WF7_BPBLCD7, 1))
/*@}*/

/*!
 * @name Register LCD_WF7, field BPCLCD7[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF7_BPCLCD7   (2U)          /*!< Bit position for LCD_WF7_BPCLCD7. */
#define BM_LCD_WF7_BPCLCD7   (0x04U)       /*!< Bit mask for LCD_WF7_BPCLCD7. */
#define BS_LCD_WF7_BPCLCD7   (1U)          /*!< Bit field size in bits for LCD_WF7_BPCLCD7. */

/*! @brief Read current value of the LCD_WF7_BPCLCD7 field. */
#define BR_LCD_WF7_BPCLCD7(x) (BME_UBFX8(HW_LCD_WF7_ADDR(x), BP_LCD_WF7_BPCLCD7, BS_LCD_WF7_BPCLCD7))

/*! @brief Format value for bitfield LCD_WF7_BPCLCD7. */
#define BF_LCD_WF7_BPCLCD7(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF7_BPCLCD7) & BM_LCD_WF7_BPCLCD7)

/*! @brief Set the BPCLCD7 field to a new value. */
#define BW_LCD_WF7_BPCLCD7(x, v) (BME_BFI8(HW_LCD_WF7_ADDR(x), ((uint8_t)(v) << BP_LCD_WF7_BPCLCD7), BP_LCD_WF7_BPCLCD7, 1))
/*@}*/

/*!
 * @name Register LCD_WF7, field BPDLCD7[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF7_BPDLCD7   (3U)          /*!< Bit position for LCD_WF7_BPDLCD7. */
#define BM_LCD_WF7_BPDLCD7   (0x08U)       /*!< Bit mask for LCD_WF7_BPDLCD7. */
#define BS_LCD_WF7_BPDLCD7   (1U)          /*!< Bit field size in bits for LCD_WF7_BPDLCD7. */

/*! @brief Read current value of the LCD_WF7_BPDLCD7 field. */
#define BR_LCD_WF7_BPDLCD7(x) (BME_UBFX8(HW_LCD_WF7_ADDR(x), BP_LCD_WF7_BPDLCD7, BS_LCD_WF7_BPDLCD7))

/*! @brief Format value for bitfield LCD_WF7_BPDLCD7. */
#define BF_LCD_WF7_BPDLCD7(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF7_BPDLCD7) & BM_LCD_WF7_BPDLCD7)

/*! @brief Set the BPDLCD7 field to a new value. */
#define BW_LCD_WF7_BPDLCD7(x, v) (BME_BFI8(HW_LCD_WF7_ADDR(x), ((uint8_t)(v) << BP_LCD_WF7_BPDLCD7), BP_LCD_WF7_BPDLCD7, 1))
/*@}*/

/*!
 * @name Register LCD_WF7, field BPELCD7[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF7_BPELCD7   (4U)          /*!< Bit position for LCD_WF7_BPELCD7. */
#define BM_LCD_WF7_BPELCD7   (0x10U)       /*!< Bit mask for LCD_WF7_BPELCD7. */
#define BS_LCD_WF7_BPELCD7   (1U)          /*!< Bit field size in bits for LCD_WF7_BPELCD7. */

/*! @brief Read current value of the LCD_WF7_BPELCD7 field. */
#define BR_LCD_WF7_BPELCD7(x) (BME_UBFX8(HW_LCD_WF7_ADDR(x), BP_LCD_WF7_BPELCD7, BS_LCD_WF7_BPELCD7))

/*! @brief Format value for bitfield LCD_WF7_BPELCD7. */
#define BF_LCD_WF7_BPELCD7(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF7_BPELCD7) & BM_LCD_WF7_BPELCD7)

/*! @brief Set the BPELCD7 field to a new value. */
#define BW_LCD_WF7_BPELCD7(x, v) (BME_BFI8(HW_LCD_WF7_ADDR(x), ((uint8_t)(v) << BP_LCD_WF7_BPELCD7), BP_LCD_WF7_BPELCD7, 1))
/*@}*/

/*!
 * @name Register LCD_WF7, field BPFLCD7[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF7_BPFLCD7   (5U)          /*!< Bit position for LCD_WF7_BPFLCD7. */
#define BM_LCD_WF7_BPFLCD7   (0x20U)       /*!< Bit mask for LCD_WF7_BPFLCD7. */
#define BS_LCD_WF7_BPFLCD7   (1U)          /*!< Bit field size in bits for LCD_WF7_BPFLCD7. */

/*! @brief Read current value of the LCD_WF7_BPFLCD7 field. */
#define BR_LCD_WF7_BPFLCD7(x) (BME_UBFX8(HW_LCD_WF7_ADDR(x), BP_LCD_WF7_BPFLCD7, BS_LCD_WF7_BPFLCD7))

/*! @brief Format value for bitfield LCD_WF7_BPFLCD7. */
#define BF_LCD_WF7_BPFLCD7(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF7_BPFLCD7) & BM_LCD_WF7_BPFLCD7)

/*! @brief Set the BPFLCD7 field to a new value. */
#define BW_LCD_WF7_BPFLCD7(x, v) (BME_BFI8(HW_LCD_WF7_ADDR(x), ((uint8_t)(v) << BP_LCD_WF7_BPFLCD7), BP_LCD_WF7_BPFLCD7, 1))
/*@}*/

/*!
 * @name Register LCD_WF7, field BPGLCD7[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF7_BPGLCD7   (6U)          /*!< Bit position for LCD_WF7_BPGLCD7. */
#define BM_LCD_WF7_BPGLCD7   (0x40U)       /*!< Bit mask for LCD_WF7_BPGLCD7. */
#define BS_LCD_WF7_BPGLCD7   (1U)          /*!< Bit field size in bits for LCD_WF7_BPGLCD7. */

/*! @brief Read current value of the LCD_WF7_BPGLCD7 field. */
#define BR_LCD_WF7_BPGLCD7(x) (BME_UBFX8(HW_LCD_WF7_ADDR(x), BP_LCD_WF7_BPGLCD7, BS_LCD_WF7_BPGLCD7))

/*! @brief Format value for bitfield LCD_WF7_BPGLCD7. */
#define BF_LCD_WF7_BPGLCD7(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF7_BPGLCD7) & BM_LCD_WF7_BPGLCD7)

/*! @brief Set the BPGLCD7 field to a new value. */
#define BW_LCD_WF7_BPGLCD7(x, v) (BME_BFI8(HW_LCD_WF7_ADDR(x), ((uint8_t)(v) << BP_LCD_WF7_BPGLCD7), BP_LCD_WF7_BPGLCD7, 1))
/*@}*/

/*!
 * @name Register LCD_WF7, field BPHLCD7[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF7_BPHLCD7   (7U)          /*!< Bit position for LCD_WF7_BPHLCD7. */
#define BM_LCD_WF7_BPHLCD7   (0x80U)       /*!< Bit mask for LCD_WF7_BPHLCD7. */
#define BS_LCD_WF7_BPHLCD7   (1U)          /*!< Bit field size in bits for LCD_WF7_BPHLCD7. */

/*! @brief Read current value of the LCD_WF7_BPHLCD7 field. */
#define BR_LCD_WF7_BPHLCD7(x) (BME_UBFX8(HW_LCD_WF7_ADDR(x), BP_LCD_WF7_BPHLCD7, BS_LCD_WF7_BPHLCD7))

/*! @brief Format value for bitfield LCD_WF7_BPHLCD7. */
#define BF_LCD_WF7_BPHLCD7(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF7_BPHLCD7) & BM_LCD_WF7_BPHLCD7)

/*! @brief Set the BPHLCD7 field to a new value. */
#define BW_LCD_WF7_BPHLCD7(x, v) (BME_BFI8(HW_LCD_WF7_ADDR(x), ((uint8_t)(v) << BP_LCD_WF7_BPHLCD7), BP_LCD_WF7_BPHLCD7, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF8 - LCD Waveform Register 8.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF8 - LCD Waveform Register 8. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf8
{
    uint8_t U;
    struct _hw_lcd_wf8_bitfields
    {
        uint8_t BPALCD8 : 1;           /*!< [0]  */
        uint8_t BPBLCD8 : 1;           /*!< [1]  */
        uint8_t BPCLCD8 : 1;           /*!< [2]  */
        uint8_t BPDLCD8 : 1;           /*!< [3]  */
        uint8_t BPELCD8 : 1;           /*!< [4]  */
        uint8_t BPFLCD8 : 1;           /*!< [5]  */
        uint8_t BPGLCD8 : 1;           /*!< [6]  */
        uint8_t BPHLCD8 : 1;           /*!< [7]  */
    } B;
} hw_lcd_wf8_t;

/*!
 * @name Constants and macros for entire LCD_WF8 register
 */
/*@{*/
#define HW_LCD_WF8_ADDR(x)       ((x) + 0x28U)

#define HW_LCD_WF8(x)            (*(__IO hw_lcd_wf8_t *) HW_LCD_WF8_ADDR(x))
#define HW_LCD_WF8_RD(x)         (HW_LCD_WF8(x).U)
#define HW_LCD_WF8_WR(x, v)      (HW_LCD_WF8(x).U = (v))
#define HW_LCD_WF8_SET(x, v)     (BME_OR8(HW_LCD_WF8_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF8_CLR(x, v)     (BME_AND8(HW_LCD_WF8_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF8_TOG(x, v)     (BME_XOR8(HW_LCD_WF8_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF8 bitfields
 */

/*!
 * @name Register LCD_WF8, field BPALCD8[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF8_BPALCD8   (0U)          /*!< Bit position for LCD_WF8_BPALCD8. */
#define BM_LCD_WF8_BPALCD8   (0x01U)       /*!< Bit mask for LCD_WF8_BPALCD8. */
#define BS_LCD_WF8_BPALCD8   (1U)          /*!< Bit field size in bits for LCD_WF8_BPALCD8. */

/*! @brief Read current value of the LCD_WF8_BPALCD8 field. */
#define BR_LCD_WF8_BPALCD8(x) (BME_UBFX8(HW_LCD_WF8_ADDR(x), BP_LCD_WF8_BPALCD8, BS_LCD_WF8_BPALCD8))

/*! @brief Format value for bitfield LCD_WF8_BPALCD8. */
#define BF_LCD_WF8_BPALCD8(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF8_BPALCD8) & BM_LCD_WF8_BPALCD8)

/*! @brief Set the BPALCD8 field to a new value. */
#define BW_LCD_WF8_BPALCD8(x, v) (BME_BFI8(HW_LCD_WF8_ADDR(x), ((uint8_t)(v) << BP_LCD_WF8_BPALCD8), BP_LCD_WF8_BPALCD8, 1))
/*@}*/

/*!
 * @name Register LCD_WF8, field BPBLCD8[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF8_BPBLCD8   (1U)          /*!< Bit position for LCD_WF8_BPBLCD8. */
#define BM_LCD_WF8_BPBLCD8   (0x02U)       /*!< Bit mask for LCD_WF8_BPBLCD8. */
#define BS_LCD_WF8_BPBLCD8   (1U)          /*!< Bit field size in bits for LCD_WF8_BPBLCD8. */

/*! @brief Read current value of the LCD_WF8_BPBLCD8 field. */
#define BR_LCD_WF8_BPBLCD8(x) (BME_UBFX8(HW_LCD_WF8_ADDR(x), BP_LCD_WF8_BPBLCD8, BS_LCD_WF8_BPBLCD8))

/*! @brief Format value for bitfield LCD_WF8_BPBLCD8. */
#define BF_LCD_WF8_BPBLCD8(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF8_BPBLCD8) & BM_LCD_WF8_BPBLCD8)

/*! @brief Set the BPBLCD8 field to a new value. */
#define BW_LCD_WF8_BPBLCD8(x, v) (BME_BFI8(HW_LCD_WF8_ADDR(x), ((uint8_t)(v) << BP_LCD_WF8_BPBLCD8), BP_LCD_WF8_BPBLCD8, 1))
/*@}*/

/*!
 * @name Register LCD_WF8, field BPCLCD8[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF8_BPCLCD8   (2U)          /*!< Bit position for LCD_WF8_BPCLCD8. */
#define BM_LCD_WF8_BPCLCD8   (0x04U)       /*!< Bit mask for LCD_WF8_BPCLCD8. */
#define BS_LCD_WF8_BPCLCD8   (1U)          /*!< Bit field size in bits for LCD_WF8_BPCLCD8. */

/*! @brief Read current value of the LCD_WF8_BPCLCD8 field. */
#define BR_LCD_WF8_BPCLCD8(x) (BME_UBFX8(HW_LCD_WF8_ADDR(x), BP_LCD_WF8_BPCLCD8, BS_LCD_WF8_BPCLCD8))

/*! @brief Format value for bitfield LCD_WF8_BPCLCD8. */
#define BF_LCD_WF8_BPCLCD8(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF8_BPCLCD8) & BM_LCD_WF8_BPCLCD8)

/*! @brief Set the BPCLCD8 field to a new value. */
#define BW_LCD_WF8_BPCLCD8(x, v) (BME_BFI8(HW_LCD_WF8_ADDR(x), ((uint8_t)(v) << BP_LCD_WF8_BPCLCD8), BP_LCD_WF8_BPCLCD8, 1))
/*@}*/

/*!
 * @name Register LCD_WF8, field BPDLCD8[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF8_BPDLCD8   (3U)          /*!< Bit position for LCD_WF8_BPDLCD8. */
#define BM_LCD_WF8_BPDLCD8   (0x08U)       /*!< Bit mask for LCD_WF8_BPDLCD8. */
#define BS_LCD_WF8_BPDLCD8   (1U)          /*!< Bit field size in bits for LCD_WF8_BPDLCD8. */

/*! @brief Read current value of the LCD_WF8_BPDLCD8 field. */
#define BR_LCD_WF8_BPDLCD8(x) (BME_UBFX8(HW_LCD_WF8_ADDR(x), BP_LCD_WF8_BPDLCD8, BS_LCD_WF8_BPDLCD8))

/*! @brief Format value for bitfield LCD_WF8_BPDLCD8. */
#define BF_LCD_WF8_BPDLCD8(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF8_BPDLCD8) & BM_LCD_WF8_BPDLCD8)

/*! @brief Set the BPDLCD8 field to a new value. */
#define BW_LCD_WF8_BPDLCD8(x, v) (BME_BFI8(HW_LCD_WF8_ADDR(x), ((uint8_t)(v) << BP_LCD_WF8_BPDLCD8), BP_LCD_WF8_BPDLCD8, 1))
/*@}*/

/*!
 * @name Register LCD_WF8, field BPELCD8[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF8_BPELCD8   (4U)          /*!< Bit position for LCD_WF8_BPELCD8. */
#define BM_LCD_WF8_BPELCD8   (0x10U)       /*!< Bit mask for LCD_WF8_BPELCD8. */
#define BS_LCD_WF8_BPELCD8   (1U)          /*!< Bit field size in bits for LCD_WF8_BPELCD8. */

/*! @brief Read current value of the LCD_WF8_BPELCD8 field. */
#define BR_LCD_WF8_BPELCD8(x) (BME_UBFX8(HW_LCD_WF8_ADDR(x), BP_LCD_WF8_BPELCD8, BS_LCD_WF8_BPELCD8))

/*! @brief Format value for bitfield LCD_WF8_BPELCD8. */
#define BF_LCD_WF8_BPELCD8(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF8_BPELCD8) & BM_LCD_WF8_BPELCD8)

/*! @brief Set the BPELCD8 field to a new value. */
#define BW_LCD_WF8_BPELCD8(x, v) (BME_BFI8(HW_LCD_WF8_ADDR(x), ((uint8_t)(v) << BP_LCD_WF8_BPELCD8), BP_LCD_WF8_BPELCD8, 1))
/*@}*/

/*!
 * @name Register LCD_WF8, field BPFLCD8[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF8_BPFLCD8   (5U)          /*!< Bit position for LCD_WF8_BPFLCD8. */
#define BM_LCD_WF8_BPFLCD8   (0x20U)       /*!< Bit mask for LCD_WF8_BPFLCD8. */
#define BS_LCD_WF8_BPFLCD8   (1U)          /*!< Bit field size in bits for LCD_WF8_BPFLCD8. */

/*! @brief Read current value of the LCD_WF8_BPFLCD8 field. */
#define BR_LCD_WF8_BPFLCD8(x) (BME_UBFX8(HW_LCD_WF8_ADDR(x), BP_LCD_WF8_BPFLCD8, BS_LCD_WF8_BPFLCD8))

/*! @brief Format value for bitfield LCD_WF8_BPFLCD8. */
#define BF_LCD_WF8_BPFLCD8(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF8_BPFLCD8) & BM_LCD_WF8_BPFLCD8)

/*! @brief Set the BPFLCD8 field to a new value. */
#define BW_LCD_WF8_BPFLCD8(x, v) (BME_BFI8(HW_LCD_WF8_ADDR(x), ((uint8_t)(v) << BP_LCD_WF8_BPFLCD8), BP_LCD_WF8_BPFLCD8, 1))
/*@}*/

/*!
 * @name Register LCD_WF8, field BPGLCD8[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF8_BPGLCD8   (6U)          /*!< Bit position for LCD_WF8_BPGLCD8. */
#define BM_LCD_WF8_BPGLCD8   (0x40U)       /*!< Bit mask for LCD_WF8_BPGLCD8. */
#define BS_LCD_WF8_BPGLCD8   (1U)          /*!< Bit field size in bits for LCD_WF8_BPGLCD8. */

/*! @brief Read current value of the LCD_WF8_BPGLCD8 field. */
#define BR_LCD_WF8_BPGLCD8(x) (BME_UBFX8(HW_LCD_WF8_ADDR(x), BP_LCD_WF8_BPGLCD8, BS_LCD_WF8_BPGLCD8))

/*! @brief Format value for bitfield LCD_WF8_BPGLCD8. */
#define BF_LCD_WF8_BPGLCD8(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF8_BPGLCD8) & BM_LCD_WF8_BPGLCD8)

/*! @brief Set the BPGLCD8 field to a new value. */
#define BW_LCD_WF8_BPGLCD8(x, v) (BME_BFI8(HW_LCD_WF8_ADDR(x), ((uint8_t)(v) << BP_LCD_WF8_BPGLCD8), BP_LCD_WF8_BPGLCD8, 1))
/*@}*/

/*!
 * @name Register LCD_WF8, field BPHLCD8[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF8_BPHLCD8   (7U)          /*!< Bit position for LCD_WF8_BPHLCD8. */
#define BM_LCD_WF8_BPHLCD8   (0x80U)       /*!< Bit mask for LCD_WF8_BPHLCD8. */
#define BS_LCD_WF8_BPHLCD8   (1U)          /*!< Bit field size in bits for LCD_WF8_BPHLCD8. */

/*! @brief Read current value of the LCD_WF8_BPHLCD8 field. */
#define BR_LCD_WF8_BPHLCD8(x) (BME_UBFX8(HW_LCD_WF8_ADDR(x), BP_LCD_WF8_BPHLCD8, BS_LCD_WF8_BPHLCD8))

/*! @brief Format value for bitfield LCD_WF8_BPHLCD8. */
#define BF_LCD_WF8_BPHLCD8(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF8_BPHLCD8) & BM_LCD_WF8_BPHLCD8)

/*! @brief Set the BPHLCD8 field to a new value. */
#define BW_LCD_WF8_BPHLCD8(x, v) (BME_BFI8(HW_LCD_WF8_ADDR(x), ((uint8_t)(v) << BP_LCD_WF8_BPHLCD8), BP_LCD_WF8_BPHLCD8, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF9 - LCD Waveform Register 9.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF9 - LCD Waveform Register 9. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf9
{
    uint8_t U;
    struct _hw_lcd_wf9_bitfields
    {
        uint8_t BPALCD9 : 1;           /*!< [0]  */
        uint8_t BPBLCD9 : 1;           /*!< [1]  */
        uint8_t BPCLCD9 : 1;           /*!< [2]  */
        uint8_t BPDLCD9 : 1;           /*!< [3]  */
        uint8_t BPELCD9 : 1;           /*!< [4]  */
        uint8_t BPFLCD9 : 1;           /*!< [5]  */
        uint8_t BPGLCD9 : 1;           /*!< [6]  */
        uint8_t BPHLCD9 : 1;           /*!< [7]  */
    } B;
} hw_lcd_wf9_t;

/*!
 * @name Constants and macros for entire LCD_WF9 register
 */
/*@{*/
#define HW_LCD_WF9_ADDR(x)       ((x) + 0x29U)

#define HW_LCD_WF9(x)            (*(__IO hw_lcd_wf9_t *) HW_LCD_WF9_ADDR(x))
#define HW_LCD_WF9_RD(x)         (HW_LCD_WF9(x).U)
#define HW_LCD_WF9_WR(x, v)      (HW_LCD_WF9(x).U = (v))
#define HW_LCD_WF9_SET(x, v)     (BME_OR8(HW_LCD_WF9_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF9_CLR(x, v)     (BME_AND8(HW_LCD_WF9_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF9_TOG(x, v)     (BME_XOR8(HW_LCD_WF9_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF9 bitfields
 */

/*!
 * @name Register LCD_WF9, field BPALCD9[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF9_BPALCD9   (0U)          /*!< Bit position for LCD_WF9_BPALCD9. */
#define BM_LCD_WF9_BPALCD9   (0x01U)       /*!< Bit mask for LCD_WF9_BPALCD9. */
#define BS_LCD_WF9_BPALCD9   (1U)          /*!< Bit field size in bits for LCD_WF9_BPALCD9. */

/*! @brief Read current value of the LCD_WF9_BPALCD9 field. */
#define BR_LCD_WF9_BPALCD9(x) (BME_UBFX8(HW_LCD_WF9_ADDR(x), BP_LCD_WF9_BPALCD9, BS_LCD_WF9_BPALCD9))

/*! @brief Format value for bitfield LCD_WF9_BPALCD9. */
#define BF_LCD_WF9_BPALCD9(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF9_BPALCD9) & BM_LCD_WF9_BPALCD9)

/*! @brief Set the BPALCD9 field to a new value. */
#define BW_LCD_WF9_BPALCD9(x, v) (BME_BFI8(HW_LCD_WF9_ADDR(x), ((uint8_t)(v) << BP_LCD_WF9_BPALCD9), BP_LCD_WF9_BPALCD9, 1))
/*@}*/

/*!
 * @name Register LCD_WF9, field BPBLCD9[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF9_BPBLCD9   (1U)          /*!< Bit position for LCD_WF9_BPBLCD9. */
#define BM_LCD_WF9_BPBLCD9   (0x02U)       /*!< Bit mask for LCD_WF9_BPBLCD9. */
#define BS_LCD_WF9_BPBLCD9   (1U)          /*!< Bit field size in bits for LCD_WF9_BPBLCD9. */

/*! @brief Read current value of the LCD_WF9_BPBLCD9 field. */
#define BR_LCD_WF9_BPBLCD9(x) (BME_UBFX8(HW_LCD_WF9_ADDR(x), BP_LCD_WF9_BPBLCD9, BS_LCD_WF9_BPBLCD9))

/*! @brief Format value for bitfield LCD_WF9_BPBLCD9. */
#define BF_LCD_WF9_BPBLCD9(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF9_BPBLCD9) & BM_LCD_WF9_BPBLCD9)

/*! @brief Set the BPBLCD9 field to a new value. */
#define BW_LCD_WF9_BPBLCD9(x, v) (BME_BFI8(HW_LCD_WF9_ADDR(x), ((uint8_t)(v) << BP_LCD_WF9_BPBLCD9), BP_LCD_WF9_BPBLCD9, 1))
/*@}*/

/*!
 * @name Register LCD_WF9, field BPCLCD9[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF9_BPCLCD9   (2U)          /*!< Bit position for LCD_WF9_BPCLCD9. */
#define BM_LCD_WF9_BPCLCD9   (0x04U)       /*!< Bit mask for LCD_WF9_BPCLCD9. */
#define BS_LCD_WF9_BPCLCD9   (1U)          /*!< Bit field size in bits for LCD_WF9_BPCLCD9. */

/*! @brief Read current value of the LCD_WF9_BPCLCD9 field. */
#define BR_LCD_WF9_BPCLCD9(x) (BME_UBFX8(HW_LCD_WF9_ADDR(x), BP_LCD_WF9_BPCLCD9, BS_LCD_WF9_BPCLCD9))

/*! @brief Format value for bitfield LCD_WF9_BPCLCD9. */
#define BF_LCD_WF9_BPCLCD9(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF9_BPCLCD9) & BM_LCD_WF9_BPCLCD9)

/*! @brief Set the BPCLCD9 field to a new value. */
#define BW_LCD_WF9_BPCLCD9(x, v) (BME_BFI8(HW_LCD_WF9_ADDR(x), ((uint8_t)(v) << BP_LCD_WF9_BPCLCD9), BP_LCD_WF9_BPCLCD9, 1))
/*@}*/

/*!
 * @name Register LCD_WF9, field BPDLCD9[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF9_BPDLCD9   (3U)          /*!< Bit position for LCD_WF9_BPDLCD9. */
#define BM_LCD_WF9_BPDLCD9   (0x08U)       /*!< Bit mask for LCD_WF9_BPDLCD9. */
#define BS_LCD_WF9_BPDLCD9   (1U)          /*!< Bit field size in bits for LCD_WF9_BPDLCD9. */

/*! @brief Read current value of the LCD_WF9_BPDLCD9 field. */
#define BR_LCD_WF9_BPDLCD9(x) (BME_UBFX8(HW_LCD_WF9_ADDR(x), BP_LCD_WF9_BPDLCD9, BS_LCD_WF9_BPDLCD9))

/*! @brief Format value for bitfield LCD_WF9_BPDLCD9. */
#define BF_LCD_WF9_BPDLCD9(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF9_BPDLCD9) & BM_LCD_WF9_BPDLCD9)

/*! @brief Set the BPDLCD9 field to a new value. */
#define BW_LCD_WF9_BPDLCD9(x, v) (BME_BFI8(HW_LCD_WF9_ADDR(x), ((uint8_t)(v) << BP_LCD_WF9_BPDLCD9), BP_LCD_WF9_BPDLCD9, 1))
/*@}*/

/*!
 * @name Register LCD_WF9, field BPELCD9[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF9_BPELCD9   (4U)          /*!< Bit position for LCD_WF9_BPELCD9. */
#define BM_LCD_WF9_BPELCD9   (0x10U)       /*!< Bit mask for LCD_WF9_BPELCD9. */
#define BS_LCD_WF9_BPELCD9   (1U)          /*!< Bit field size in bits for LCD_WF9_BPELCD9. */

/*! @brief Read current value of the LCD_WF9_BPELCD9 field. */
#define BR_LCD_WF9_BPELCD9(x) (BME_UBFX8(HW_LCD_WF9_ADDR(x), BP_LCD_WF9_BPELCD9, BS_LCD_WF9_BPELCD9))

/*! @brief Format value for bitfield LCD_WF9_BPELCD9. */
#define BF_LCD_WF9_BPELCD9(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF9_BPELCD9) & BM_LCD_WF9_BPELCD9)

/*! @brief Set the BPELCD9 field to a new value. */
#define BW_LCD_WF9_BPELCD9(x, v) (BME_BFI8(HW_LCD_WF9_ADDR(x), ((uint8_t)(v) << BP_LCD_WF9_BPELCD9), BP_LCD_WF9_BPELCD9, 1))
/*@}*/

/*!
 * @name Register LCD_WF9, field BPFLCD9[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF9_BPFLCD9   (5U)          /*!< Bit position for LCD_WF9_BPFLCD9. */
#define BM_LCD_WF9_BPFLCD9   (0x20U)       /*!< Bit mask for LCD_WF9_BPFLCD9. */
#define BS_LCD_WF9_BPFLCD9   (1U)          /*!< Bit field size in bits for LCD_WF9_BPFLCD9. */

/*! @brief Read current value of the LCD_WF9_BPFLCD9 field. */
#define BR_LCD_WF9_BPFLCD9(x) (BME_UBFX8(HW_LCD_WF9_ADDR(x), BP_LCD_WF9_BPFLCD9, BS_LCD_WF9_BPFLCD9))

/*! @brief Format value for bitfield LCD_WF9_BPFLCD9. */
#define BF_LCD_WF9_BPFLCD9(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF9_BPFLCD9) & BM_LCD_WF9_BPFLCD9)

/*! @brief Set the BPFLCD9 field to a new value. */
#define BW_LCD_WF9_BPFLCD9(x, v) (BME_BFI8(HW_LCD_WF9_ADDR(x), ((uint8_t)(v) << BP_LCD_WF9_BPFLCD9), BP_LCD_WF9_BPFLCD9, 1))
/*@}*/

/*!
 * @name Register LCD_WF9, field BPGLCD9[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF9_BPGLCD9   (6U)          /*!< Bit position for LCD_WF9_BPGLCD9. */
#define BM_LCD_WF9_BPGLCD9   (0x40U)       /*!< Bit mask for LCD_WF9_BPGLCD9. */
#define BS_LCD_WF9_BPGLCD9   (1U)          /*!< Bit field size in bits for LCD_WF9_BPGLCD9. */

/*! @brief Read current value of the LCD_WF9_BPGLCD9 field. */
#define BR_LCD_WF9_BPGLCD9(x) (BME_UBFX8(HW_LCD_WF9_ADDR(x), BP_LCD_WF9_BPGLCD9, BS_LCD_WF9_BPGLCD9))

/*! @brief Format value for bitfield LCD_WF9_BPGLCD9. */
#define BF_LCD_WF9_BPGLCD9(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF9_BPGLCD9) & BM_LCD_WF9_BPGLCD9)

/*! @brief Set the BPGLCD9 field to a new value. */
#define BW_LCD_WF9_BPGLCD9(x, v) (BME_BFI8(HW_LCD_WF9_ADDR(x), ((uint8_t)(v) << BP_LCD_WF9_BPGLCD9), BP_LCD_WF9_BPGLCD9, 1))
/*@}*/

/*!
 * @name Register LCD_WF9, field BPHLCD9[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF9_BPHLCD9   (7U)          /*!< Bit position for LCD_WF9_BPHLCD9. */
#define BM_LCD_WF9_BPHLCD9   (0x80U)       /*!< Bit mask for LCD_WF9_BPHLCD9. */
#define BS_LCD_WF9_BPHLCD9   (1U)          /*!< Bit field size in bits for LCD_WF9_BPHLCD9. */

/*! @brief Read current value of the LCD_WF9_BPHLCD9 field. */
#define BR_LCD_WF9_BPHLCD9(x) (BME_UBFX8(HW_LCD_WF9_ADDR(x), BP_LCD_WF9_BPHLCD9, BS_LCD_WF9_BPHLCD9))

/*! @brief Format value for bitfield LCD_WF9_BPHLCD9. */
#define BF_LCD_WF9_BPHLCD9(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF9_BPHLCD9) & BM_LCD_WF9_BPHLCD9)

/*! @brief Set the BPHLCD9 field to a new value. */
#define BW_LCD_WF9_BPHLCD9(x, v) (BME_BFI8(HW_LCD_WF9_ADDR(x), ((uint8_t)(v) << BP_LCD_WF9_BPHLCD9), BP_LCD_WF9_BPHLCD9, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF10 - LCD Waveform Register 10.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF10 - LCD Waveform Register 10. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf10
{
    uint8_t U;
    struct _hw_lcd_wf10_bitfields
    {
        uint8_t BPALCD10 : 1;          /*!< [0]  */
        uint8_t BPBLCD10 : 1;          /*!< [1]  */
        uint8_t BPCLCD10 : 1;          /*!< [2]  */
        uint8_t BPDLCD10 : 1;          /*!< [3]  */
        uint8_t BPELCD10 : 1;          /*!< [4]  */
        uint8_t BPFLCD10 : 1;          /*!< [5]  */
        uint8_t BPGLCD10 : 1;          /*!< [6]  */
        uint8_t BPHLCD10 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf10_t;

/*!
 * @name Constants and macros for entire LCD_WF10 register
 */
/*@{*/
#define HW_LCD_WF10_ADDR(x)      ((x) + 0x2AU)

#define HW_LCD_WF10(x)           (*(__IO hw_lcd_wf10_t *) HW_LCD_WF10_ADDR(x))
#define HW_LCD_WF10_RD(x)        (HW_LCD_WF10(x).U)
#define HW_LCD_WF10_WR(x, v)     (HW_LCD_WF10(x).U = (v))
#define HW_LCD_WF10_SET(x, v)    (BME_OR8(HW_LCD_WF10_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF10_CLR(x, v)    (BME_AND8(HW_LCD_WF10_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF10_TOG(x, v)    (BME_XOR8(HW_LCD_WF10_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF10 bitfields
 */

/*!
 * @name Register LCD_WF10, field BPALCD10[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF10_BPALCD10 (0U)          /*!< Bit position for LCD_WF10_BPALCD10. */
#define BM_LCD_WF10_BPALCD10 (0x01U)       /*!< Bit mask for LCD_WF10_BPALCD10. */
#define BS_LCD_WF10_BPALCD10 (1U)          /*!< Bit field size in bits for LCD_WF10_BPALCD10. */

/*! @brief Read current value of the LCD_WF10_BPALCD10 field. */
#define BR_LCD_WF10_BPALCD10(x) (BME_UBFX8(HW_LCD_WF10_ADDR(x), BP_LCD_WF10_BPALCD10, BS_LCD_WF10_BPALCD10))

/*! @brief Format value for bitfield LCD_WF10_BPALCD10. */
#define BF_LCD_WF10_BPALCD10(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF10_BPALCD10) & BM_LCD_WF10_BPALCD10)

/*! @brief Set the BPALCD10 field to a new value. */
#define BW_LCD_WF10_BPALCD10(x, v) (BME_BFI8(HW_LCD_WF10_ADDR(x), ((uint8_t)(v) << BP_LCD_WF10_BPALCD10), BP_LCD_WF10_BPALCD10, 1))
/*@}*/

/*!
 * @name Register LCD_WF10, field BPBLCD10[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF10_BPBLCD10 (1U)          /*!< Bit position for LCD_WF10_BPBLCD10. */
#define BM_LCD_WF10_BPBLCD10 (0x02U)       /*!< Bit mask for LCD_WF10_BPBLCD10. */
#define BS_LCD_WF10_BPBLCD10 (1U)          /*!< Bit field size in bits for LCD_WF10_BPBLCD10. */

/*! @brief Read current value of the LCD_WF10_BPBLCD10 field. */
#define BR_LCD_WF10_BPBLCD10(x) (BME_UBFX8(HW_LCD_WF10_ADDR(x), BP_LCD_WF10_BPBLCD10, BS_LCD_WF10_BPBLCD10))

/*! @brief Format value for bitfield LCD_WF10_BPBLCD10. */
#define BF_LCD_WF10_BPBLCD10(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF10_BPBLCD10) & BM_LCD_WF10_BPBLCD10)

/*! @brief Set the BPBLCD10 field to a new value. */
#define BW_LCD_WF10_BPBLCD10(x, v) (BME_BFI8(HW_LCD_WF10_ADDR(x), ((uint8_t)(v) << BP_LCD_WF10_BPBLCD10), BP_LCD_WF10_BPBLCD10, 1))
/*@}*/

/*!
 * @name Register LCD_WF10, field BPCLCD10[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF10_BPCLCD10 (2U)          /*!< Bit position for LCD_WF10_BPCLCD10. */
#define BM_LCD_WF10_BPCLCD10 (0x04U)       /*!< Bit mask for LCD_WF10_BPCLCD10. */
#define BS_LCD_WF10_BPCLCD10 (1U)          /*!< Bit field size in bits for LCD_WF10_BPCLCD10. */

/*! @brief Read current value of the LCD_WF10_BPCLCD10 field. */
#define BR_LCD_WF10_BPCLCD10(x) (BME_UBFX8(HW_LCD_WF10_ADDR(x), BP_LCD_WF10_BPCLCD10, BS_LCD_WF10_BPCLCD10))

/*! @brief Format value for bitfield LCD_WF10_BPCLCD10. */
#define BF_LCD_WF10_BPCLCD10(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF10_BPCLCD10) & BM_LCD_WF10_BPCLCD10)

/*! @brief Set the BPCLCD10 field to a new value. */
#define BW_LCD_WF10_BPCLCD10(x, v) (BME_BFI8(HW_LCD_WF10_ADDR(x), ((uint8_t)(v) << BP_LCD_WF10_BPCLCD10), BP_LCD_WF10_BPCLCD10, 1))
/*@}*/

/*!
 * @name Register LCD_WF10, field BPDLCD10[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF10_BPDLCD10 (3U)          /*!< Bit position for LCD_WF10_BPDLCD10. */
#define BM_LCD_WF10_BPDLCD10 (0x08U)       /*!< Bit mask for LCD_WF10_BPDLCD10. */
#define BS_LCD_WF10_BPDLCD10 (1U)          /*!< Bit field size in bits for LCD_WF10_BPDLCD10. */

/*! @brief Read current value of the LCD_WF10_BPDLCD10 field. */
#define BR_LCD_WF10_BPDLCD10(x) (BME_UBFX8(HW_LCD_WF10_ADDR(x), BP_LCD_WF10_BPDLCD10, BS_LCD_WF10_BPDLCD10))

/*! @brief Format value for bitfield LCD_WF10_BPDLCD10. */
#define BF_LCD_WF10_BPDLCD10(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF10_BPDLCD10) & BM_LCD_WF10_BPDLCD10)

/*! @brief Set the BPDLCD10 field to a new value. */
#define BW_LCD_WF10_BPDLCD10(x, v) (BME_BFI8(HW_LCD_WF10_ADDR(x), ((uint8_t)(v) << BP_LCD_WF10_BPDLCD10), BP_LCD_WF10_BPDLCD10, 1))
/*@}*/

/*!
 * @name Register LCD_WF10, field BPELCD10[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF10_BPELCD10 (4U)          /*!< Bit position for LCD_WF10_BPELCD10. */
#define BM_LCD_WF10_BPELCD10 (0x10U)       /*!< Bit mask for LCD_WF10_BPELCD10. */
#define BS_LCD_WF10_BPELCD10 (1U)          /*!< Bit field size in bits for LCD_WF10_BPELCD10. */

/*! @brief Read current value of the LCD_WF10_BPELCD10 field. */
#define BR_LCD_WF10_BPELCD10(x) (BME_UBFX8(HW_LCD_WF10_ADDR(x), BP_LCD_WF10_BPELCD10, BS_LCD_WF10_BPELCD10))

/*! @brief Format value for bitfield LCD_WF10_BPELCD10. */
#define BF_LCD_WF10_BPELCD10(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF10_BPELCD10) & BM_LCD_WF10_BPELCD10)

/*! @brief Set the BPELCD10 field to a new value. */
#define BW_LCD_WF10_BPELCD10(x, v) (BME_BFI8(HW_LCD_WF10_ADDR(x), ((uint8_t)(v) << BP_LCD_WF10_BPELCD10), BP_LCD_WF10_BPELCD10, 1))
/*@}*/

/*!
 * @name Register LCD_WF10, field BPFLCD10[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF10_BPFLCD10 (5U)          /*!< Bit position for LCD_WF10_BPFLCD10. */
#define BM_LCD_WF10_BPFLCD10 (0x20U)       /*!< Bit mask for LCD_WF10_BPFLCD10. */
#define BS_LCD_WF10_BPFLCD10 (1U)          /*!< Bit field size in bits for LCD_WF10_BPFLCD10. */

/*! @brief Read current value of the LCD_WF10_BPFLCD10 field. */
#define BR_LCD_WF10_BPFLCD10(x) (BME_UBFX8(HW_LCD_WF10_ADDR(x), BP_LCD_WF10_BPFLCD10, BS_LCD_WF10_BPFLCD10))

/*! @brief Format value for bitfield LCD_WF10_BPFLCD10. */
#define BF_LCD_WF10_BPFLCD10(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF10_BPFLCD10) & BM_LCD_WF10_BPFLCD10)

/*! @brief Set the BPFLCD10 field to a new value. */
#define BW_LCD_WF10_BPFLCD10(x, v) (BME_BFI8(HW_LCD_WF10_ADDR(x), ((uint8_t)(v) << BP_LCD_WF10_BPFLCD10), BP_LCD_WF10_BPFLCD10, 1))
/*@}*/

/*!
 * @name Register LCD_WF10, field BPGLCD10[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF10_BPGLCD10 (6U)          /*!< Bit position for LCD_WF10_BPGLCD10. */
#define BM_LCD_WF10_BPGLCD10 (0x40U)       /*!< Bit mask for LCD_WF10_BPGLCD10. */
#define BS_LCD_WF10_BPGLCD10 (1U)          /*!< Bit field size in bits for LCD_WF10_BPGLCD10. */

/*! @brief Read current value of the LCD_WF10_BPGLCD10 field. */
#define BR_LCD_WF10_BPGLCD10(x) (BME_UBFX8(HW_LCD_WF10_ADDR(x), BP_LCD_WF10_BPGLCD10, BS_LCD_WF10_BPGLCD10))

/*! @brief Format value for bitfield LCD_WF10_BPGLCD10. */
#define BF_LCD_WF10_BPGLCD10(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF10_BPGLCD10) & BM_LCD_WF10_BPGLCD10)

/*! @brief Set the BPGLCD10 field to a new value. */
#define BW_LCD_WF10_BPGLCD10(x, v) (BME_BFI8(HW_LCD_WF10_ADDR(x), ((uint8_t)(v) << BP_LCD_WF10_BPGLCD10), BP_LCD_WF10_BPGLCD10, 1))
/*@}*/

/*!
 * @name Register LCD_WF10, field BPHLCD10[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF10_BPHLCD10 (7U)          /*!< Bit position for LCD_WF10_BPHLCD10. */
#define BM_LCD_WF10_BPHLCD10 (0x80U)       /*!< Bit mask for LCD_WF10_BPHLCD10. */
#define BS_LCD_WF10_BPHLCD10 (1U)          /*!< Bit field size in bits for LCD_WF10_BPHLCD10. */

/*! @brief Read current value of the LCD_WF10_BPHLCD10 field. */
#define BR_LCD_WF10_BPHLCD10(x) (BME_UBFX8(HW_LCD_WF10_ADDR(x), BP_LCD_WF10_BPHLCD10, BS_LCD_WF10_BPHLCD10))

/*! @brief Format value for bitfield LCD_WF10_BPHLCD10. */
#define BF_LCD_WF10_BPHLCD10(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF10_BPHLCD10) & BM_LCD_WF10_BPHLCD10)

/*! @brief Set the BPHLCD10 field to a new value. */
#define BW_LCD_WF10_BPHLCD10(x, v) (BME_BFI8(HW_LCD_WF10_ADDR(x), ((uint8_t)(v) << BP_LCD_WF10_BPHLCD10), BP_LCD_WF10_BPHLCD10, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF11 - LCD Waveform Register 11.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF11 - LCD Waveform Register 11. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf11
{
    uint8_t U;
    struct _hw_lcd_wf11_bitfields
    {
        uint8_t BPALCD11 : 1;          /*!< [0]  */
        uint8_t BPBLCD11 : 1;          /*!< [1]  */
        uint8_t BPCLCD11 : 1;          /*!< [2]  */
        uint8_t BPDLCD11 : 1;          /*!< [3]  */
        uint8_t BPELCD11 : 1;          /*!< [4]  */
        uint8_t BPFLCD11 : 1;          /*!< [5]  */
        uint8_t BPGLCD11 : 1;          /*!< [6]  */
        uint8_t BPHLCD11 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf11_t;

/*!
 * @name Constants and macros for entire LCD_WF11 register
 */
/*@{*/
#define HW_LCD_WF11_ADDR(x)      ((x) + 0x2BU)

#define HW_LCD_WF11(x)           (*(__IO hw_lcd_wf11_t *) HW_LCD_WF11_ADDR(x))
#define HW_LCD_WF11_RD(x)        (HW_LCD_WF11(x).U)
#define HW_LCD_WF11_WR(x, v)     (HW_LCD_WF11(x).U = (v))
#define HW_LCD_WF11_SET(x, v)    (BME_OR8(HW_LCD_WF11_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF11_CLR(x, v)    (BME_AND8(HW_LCD_WF11_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF11_TOG(x, v)    (BME_XOR8(HW_LCD_WF11_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF11 bitfields
 */

/*!
 * @name Register LCD_WF11, field BPALCD11[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF11_BPALCD11 (0U)          /*!< Bit position for LCD_WF11_BPALCD11. */
#define BM_LCD_WF11_BPALCD11 (0x01U)       /*!< Bit mask for LCD_WF11_BPALCD11. */
#define BS_LCD_WF11_BPALCD11 (1U)          /*!< Bit field size in bits for LCD_WF11_BPALCD11. */

/*! @brief Read current value of the LCD_WF11_BPALCD11 field. */
#define BR_LCD_WF11_BPALCD11(x) (BME_UBFX8(HW_LCD_WF11_ADDR(x), BP_LCD_WF11_BPALCD11, BS_LCD_WF11_BPALCD11))

/*! @brief Format value for bitfield LCD_WF11_BPALCD11. */
#define BF_LCD_WF11_BPALCD11(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF11_BPALCD11) & BM_LCD_WF11_BPALCD11)

/*! @brief Set the BPALCD11 field to a new value. */
#define BW_LCD_WF11_BPALCD11(x, v) (BME_BFI8(HW_LCD_WF11_ADDR(x), ((uint8_t)(v) << BP_LCD_WF11_BPALCD11), BP_LCD_WF11_BPALCD11, 1))
/*@}*/

/*!
 * @name Register LCD_WF11, field BPBLCD11[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF11_BPBLCD11 (1U)          /*!< Bit position for LCD_WF11_BPBLCD11. */
#define BM_LCD_WF11_BPBLCD11 (0x02U)       /*!< Bit mask for LCD_WF11_BPBLCD11. */
#define BS_LCD_WF11_BPBLCD11 (1U)          /*!< Bit field size in bits for LCD_WF11_BPBLCD11. */

/*! @brief Read current value of the LCD_WF11_BPBLCD11 field. */
#define BR_LCD_WF11_BPBLCD11(x) (BME_UBFX8(HW_LCD_WF11_ADDR(x), BP_LCD_WF11_BPBLCD11, BS_LCD_WF11_BPBLCD11))

/*! @brief Format value for bitfield LCD_WF11_BPBLCD11. */
#define BF_LCD_WF11_BPBLCD11(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF11_BPBLCD11) & BM_LCD_WF11_BPBLCD11)

/*! @brief Set the BPBLCD11 field to a new value. */
#define BW_LCD_WF11_BPBLCD11(x, v) (BME_BFI8(HW_LCD_WF11_ADDR(x), ((uint8_t)(v) << BP_LCD_WF11_BPBLCD11), BP_LCD_WF11_BPBLCD11, 1))
/*@}*/

/*!
 * @name Register LCD_WF11, field BPCLCD11[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF11_BPCLCD11 (2U)          /*!< Bit position for LCD_WF11_BPCLCD11. */
#define BM_LCD_WF11_BPCLCD11 (0x04U)       /*!< Bit mask for LCD_WF11_BPCLCD11. */
#define BS_LCD_WF11_BPCLCD11 (1U)          /*!< Bit field size in bits for LCD_WF11_BPCLCD11. */

/*! @brief Read current value of the LCD_WF11_BPCLCD11 field. */
#define BR_LCD_WF11_BPCLCD11(x) (BME_UBFX8(HW_LCD_WF11_ADDR(x), BP_LCD_WF11_BPCLCD11, BS_LCD_WF11_BPCLCD11))

/*! @brief Format value for bitfield LCD_WF11_BPCLCD11. */
#define BF_LCD_WF11_BPCLCD11(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF11_BPCLCD11) & BM_LCD_WF11_BPCLCD11)

/*! @brief Set the BPCLCD11 field to a new value. */
#define BW_LCD_WF11_BPCLCD11(x, v) (BME_BFI8(HW_LCD_WF11_ADDR(x), ((uint8_t)(v) << BP_LCD_WF11_BPCLCD11), BP_LCD_WF11_BPCLCD11, 1))
/*@}*/

/*!
 * @name Register LCD_WF11, field BPDLCD11[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF11_BPDLCD11 (3U)          /*!< Bit position for LCD_WF11_BPDLCD11. */
#define BM_LCD_WF11_BPDLCD11 (0x08U)       /*!< Bit mask for LCD_WF11_BPDLCD11. */
#define BS_LCD_WF11_BPDLCD11 (1U)          /*!< Bit field size in bits for LCD_WF11_BPDLCD11. */

/*! @brief Read current value of the LCD_WF11_BPDLCD11 field. */
#define BR_LCD_WF11_BPDLCD11(x) (BME_UBFX8(HW_LCD_WF11_ADDR(x), BP_LCD_WF11_BPDLCD11, BS_LCD_WF11_BPDLCD11))

/*! @brief Format value for bitfield LCD_WF11_BPDLCD11. */
#define BF_LCD_WF11_BPDLCD11(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF11_BPDLCD11) & BM_LCD_WF11_BPDLCD11)

/*! @brief Set the BPDLCD11 field to a new value. */
#define BW_LCD_WF11_BPDLCD11(x, v) (BME_BFI8(HW_LCD_WF11_ADDR(x), ((uint8_t)(v) << BP_LCD_WF11_BPDLCD11), BP_LCD_WF11_BPDLCD11, 1))
/*@}*/

/*!
 * @name Register LCD_WF11, field BPELCD11[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF11_BPELCD11 (4U)          /*!< Bit position for LCD_WF11_BPELCD11. */
#define BM_LCD_WF11_BPELCD11 (0x10U)       /*!< Bit mask for LCD_WF11_BPELCD11. */
#define BS_LCD_WF11_BPELCD11 (1U)          /*!< Bit field size in bits for LCD_WF11_BPELCD11. */

/*! @brief Read current value of the LCD_WF11_BPELCD11 field. */
#define BR_LCD_WF11_BPELCD11(x) (BME_UBFX8(HW_LCD_WF11_ADDR(x), BP_LCD_WF11_BPELCD11, BS_LCD_WF11_BPELCD11))

/*! @brief Format value for bitfield LCD_WF11_BPELCD11. */
#define BF_LCD_WF11_BPELCD11(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF11_BPELCD11) & BM_LCD_WF11_BPELCD11)

/*! @brief Set the BPELCD11 field to a new value. */
#define BW_LCD_WF11_BPELCD11(x, v) (BME_BFI8(HW_LCD_WF11_ADDR(x), ((uint8_t)(v) << BP_LCD_WF11_BPELCD11), BP_LCD_WF11_BPELCD11, 1))
/*@}*/

/*!
 * @name Register LCD_WF11, field BPFLCD11[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF11_BPFLCD11 (5U)          /*!< Bit position for LCD_WF11_BPFLCD11. */
#define BM_LCD_WF11_BPFLCD11 (0x20U)       /*!< Bit mask for LCD_WF11_BPFLCD11. */
#define BS_LCD_WF11_BPFLCD11 (1U)          /*!< Bit field size in bits for LCD_WF11_BPFLCD11. */

/*! @brief Read current value of the LCD_WF11_BPFLCD11 field. */
#define BR_LCD_WF11_BPFLCD11(x) (BME_UBFX8(HW_LCD_WF11_ADDR(x), BP_LCD_WF11_BPFLCD11, BS_LCD_WF11_BPFLCD11))

/*! @brief Format value for bitfield LCD_WF11_BPFLCD11. */
#define BF_LCD_WF11_BPFLCD11(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF11_BPFLCD11) & BM_LCD_WF11_BPFLCD11)

/*! @brief Set the BPFLCD11 field to a new value. */
#define BW_LCD_WF11_BPFLCD11(x, v) (BME_BFI8(HW_LCD_WF11_ADDR(x), ((uint8_t)(v) << BP_LCD_WF11_BPFLCD11), BP_LCD_WF11_BPFLCD11, 1))
/*@}*/

/*!
 * @name Register LCD_WF11, field BPGLCD11[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF11_BPGLCD11 (6U)          /*!< Bit position for LCD_WF11_BPGLCD11. */
#define BM_LCD_WF11_BPGLCD11 (0x40U)       /*!< Bit mask for LCD_WF11_BPGLCD11. */
#define BS_LCD_WF11_BPGLCD11 (1U)          /*!< Bit field size in bits for LCD_WF11_BPGLCD11. */

/*! @brief Read current value of the LCD_WF11_BPGLCD11 field. */
#define BR_LCD_WF11_BPGLCD11(x) (BME_UBFX8(HW_LCD_WF11_ADDR(x), BP_LCD_WF11_BPGLCD11, BS_LCD_WF11_BPGLCD11))

/*! @brief Format value for bitfield LCD_WF11_BPGLCD11. */
#define BF_LCD_WF11_BPGLCD11(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF11_BPGLCD11) & BM_LCD_WF11_BPGLCD11)

/*! @brief Set the BPGLCD11 field to a new value. */
#define BW_LCD_WF11_BPGLCD11(x, v) (BME_BFI8(HW_LCD_WF11_ADDR(x), ((uint8_t)(v) << BP_LCD_WF11_BPGLCD11), BP_LCD_WF11_BPGLCD11, 1))
/*@}*/

/*!
 * @name Register LCD_WF11, field BPHLCD11[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF11_BPHLCD11 (7U)          /*!< Bit position for LCD_WF11_BPHLCD11. */
#define BM_LCD_WF11_BPHLCD11 (0x80U)       /*!< Bit mask for LCD_WF11_BPHLCD11. */
#define BS_LCD_WF11_BPHLCD11 (1U)          /*!< Bit field size in bits for LCD_WF11_BPHLCD11. */

/*! @brief Read current value of the LCD_WF11_BPHLCD11 field. */
#define BR_LCD_WF11_BPHLCD11(x) (BME_UBFX8(HW_LCD_WF11_ADDR(x), BP_LCD_WF11_BPHLCD11, BS_LCD_WF11_BPHLCD11))

/*! @brief Format value for bitfield LCD_WF11_BPHLCD11. */
#define BF_LCD_WF11_BPHLCD11(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF11_BPHLCD11) & BM_LCD_WF11_BPHLCD11)

/*! @brief Set the BPHLCD11 field to a new value. */
#define BW_LCD_WF11_BPHLCD11(x, v) (BME_BFI8(HW_LCD_WF11_ADDR(x), ((uint8_t)(v) << BP_LCD_WF11_BPHLCD11), BP_LCD_WF11_BPHLCD11, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF12 - LCD Waveform Register 12.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF12 - LCD Waveform Register 12. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf12
{
    uint8_t U;
    struct _hw_lcd_wf12_bitfields
    {
        uint8_t BPALCD12 : 1;          /*!< [0]  */
        uint8_t BPBLCD12 : 1;          /*!< [1]  */
        uint8_t BPCLCD12 : 1;          /*!< [2]  */
        uint8_t BPDLCD12 : 1;          /*!< [3]  */
        uint8_t BPELCD12 : 1;          /*!< [4]  */
        uint8_t BPFLCD12 : 1;          /*!< [5]  */
        uint8_t BPGLCD12 : 1;          /*!< [6]  */
        uint8_t BPHLCD12 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf12_t;

/*!
 * @name Constants and macros for entire LCD_WF12 register
 */
/*@{*/
#define HW_LCD_WF12_ADDR(x)      ((x) + 0x2CU)

#define HW_LCD_WF12(x)           (*(__IO hw_lcd_wf12_t *) HW_LCD_WF12_ADDR(x))
#define HW_LCD_WF12_RD(x)        (HW_LCD_WF12(x).U)
#define HW_LCD_WF12_WR(x, v)     (HW_LCD_WF12(x).U = (v))
#define HW_LCD_WF12_SET(x, v)    (BME_OR8(HW_LCD_WF12_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF12_CLR(x, v)    (BME_AND8(HW_LCD_WF12_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF12_TOG(x, v)    (BME_XOR8(HW_LCD_WF12_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF12 bitfields
 */

/*!
 * @name Register LCD_WF12, field BPALCD12[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF12_BPALCD12 (0U)          /*!< Bit position for LCD_WF12_BPALCD12. */
#define BM_LCD_WF12_BPALCD12 (0x01U)       /*!< Bit mask for LCD_WF12_BPALCD12. */
#define BS_LCD_WF12_BPALCD12 (1U)          /*!< Bit field size in bits for LCD_WF12_BPALCD12. */

/*! @brief Read current value of the LCD_WF12_BPALCD12 field. */
#define BR_LCD_WF12_BPALCD12(x) (BME_UBFX8(HW_LCD_WF12_ADDR(x), BP_LCD_WF12_BPALCD12, BS_LCD_WF12_BPALCD12))

/*! @brief Format value for bitfield LCD_WF12_BPALCD12. */
#define BF_LCD_WF12_BPALCD12(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF12_BPALCD12) & BM_LCD_WF12_BPALCD12)

/*! @brief Set the BPALCD12 field to a new value. */
#define BW_LCD_WF12_BPALCD12(x, v) (BME_BFI8(HW_LCD_WF12_ADDR(x), ((uint8_t)(v) << BP_LCD_WF12_BPALCD12), BP_LCD_WF12_BPALCD12, 1))
/*@}*/

/*!
 * @name Register LCD_WF12, field BPBLCD12[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF12_BPBLCD12 (1U)          /*!< Bit position for LCD_WF12_BPBLCD12. */
#define BM_LCD_WF12_BPBLCD12 (0x02U)       /*!< Bit mask for LCD_WF12_BPBLCD12. */
#define BS_LCD_WF12_BPBLCD12 (1U)          /*!< Bit field size in bits for LCD_WF12_BPBLCD12. */

/*! @brief Read current value of the LCD_WF12_BPBLCD12 field. */
#define BR_LCD_WF12_BPBLCD12(x) (BME_UBFX8(HW_LCD_WF12_ADDR(x), BP_LCD_WF12_BPBLCD12, BS_LCD_WF12_BPBLCD12))

/*! @brief Format value for bitfield LCD_WF12_BPBLCD12. */
#define BF_LCD_WF12_BPBLCD12(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF12_BPBLCD12) & BM_LCD_WF12_BPBLCD12)

/*! @brief Set the BPBLCD12 field to a new value. */
#define BW_LCD_WF12_BPBLCD12(x, v) (BME_BFI8(HW_LCD_WF12_ADDR(x), ((uint8_t)(v) << BP_LCD_WF12_BPBLCD12), BP_LCD_WF12_BPBLCD12, 1))
/*@}*/

/*!
 * @name Register LCD_WF12, field BPCLCD12[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF12_BPCLCD12 (2U)          /*!< Bit position for LCD_WF12_BPCLCD12. */
#define BM_LCD_WF12_BPCLCD12 (0x04U)       /*!< Bit mask for LCD_WF12_BPCLCD12. */
#define BS_LCD_WF12_BPCLCD12 (1U)          /*!< Bit field size in bits for LCD_WF12_BPCLCD12. */

/*! @brief Read current value of the LCD_WF12_BPCLCD12 field. */
#define BR_LCD_WF12_BPCLCD12(x) (BME_UBFX8(HW_LCD_WF12_ADDR(x), BP_LCD_WF12_BPCLCD12, BS_LCD_WF12_BPCLCD12))

/*! @brief Format value for bitfield LCD_WF12_BPCLCD12. */
#define BF_LCD_WF12_BPCLCD12(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF12_BPCLCD12) & BM_LCD_WF12_BPCLCD12)

/*! @brief Set the BPCLCD12 field to a new value. */
#define BW_LCD_WF12_BPCLCD12(x, v) (BME_BFI8(HW_LCD_WF12_ADDR(x), ((uint8_t)(v) << BP_LCD_WF12_BPCLCD12), BP_LCD_WF12_BPCLCD12, 1))
/*@}*/

/*!
 * @name Register LCD_WF12, field BPDLCD12[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF12_BPDLCD12 (3U)          /*!< Bit position for LCD_WF12_BPDLCD12. */
#define BM_LCD_WF12_BPDLCD12 (0x08U)       /*!< Bit mask for LCD_WF12_BPDLCD12. */
#define BS_LCD_WF12_BPDLCD12 (1U)          /*!< Bit field size in bits for LCD_WF12_BPDLCD12. */

/*! @brief Read current value of the LCD_WF12_BPDLCD12 field. */
#define BR_LCD_WF12_BPDLCD12(x) (BME_UBFX8(HW_LCD_WF12_ADDR(x), BP_LCD_WF12_BPDLCD12, BS_LCD_WF12_BPDLCD12))

/*! @brief Format value for bitfield LCD_WF12_BPDLCD12. */
#define BF_LCD_WF12_BPDLCD12(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF12_BPDLCD12) & BM_LCD_WF12_BPDLCD12)

/*! @brief Set the BPDLCD12 field to a new value. */
#define BW_LCD_WF12_BPDLCD12(x, v) (BME_BFI8(HW_LCD_WF12_ADDR(x), ((uint8_t)(v) << BP_LCD_WF12_BPDLCD12), BP_LCD_WF12_BPDLCD12, 1))
/*@}*/

/*!
 * @name Register LCD_WF12, field BPELCD12[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF12_BPELCD12 (4U)          /*!< Bit position for LCD_WF12_BPELCD12. */
#define BM_LCD_WF12_BPELCD12 (0x10U)       /*!< Bit mask for LCD_WF12_BPELCD12. */
#define BS_LCD_WF12_BPELCD12 (1U)          /*!< Bit field size in bits for LCD_WF12_BPELCD12. */

/*! @brief Read current value of the LCD_WF12_BPELCD12 field. */
#define BR_LCD_WF12_BPELCD12(x) (BME_UBFX8(HW_LCD_WF12_ADDR(x), BP_LCD_WF12_BPELCD12, BS_LCD_WF12_BPELCD12))

/*! @brief Format value for bitfield LCD_WF12_BPELCD12. */
#define BF_LCD_WF12_BPELCD12(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF12_BPELCD12) & BM_LCD_WF12_BPELCD12)

/*! @brief Set the BPELCD12 field to a new value. */
#define BW_LCD_WF12_BPELCD12(x, v) (BME_BFI8(HW_LCD_WF12_ADDR(x), ((uint8_t)(v) << BP_LCD_WF12_BPELCD12), BP_LCD_WF12_BPELCD12, 1))
/*@}*/

/*!
 * @name Register LCD_WF12, field BPFLCD12[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF12_BPFLCD12 (5U)          /*!< Bit position for LCD_WF12_BPFLCD12. */
#define BM_LCD_WF12_BPFLCD12 (0x20U)       /*!< Bit mask for LCD_WF12_BPFLCD12. */
#define BS_LCD_WF12_BPFLCD12 (1U)          /*!< Bit field size in bits for LCD_WF12_BPFLCD12. */

/*! @brief Read current value of the LCD_WF12_BPFLCD12 field. */
#define BR_LCD_WF12_BPFLCD12(x) (BME_UBFX8(HW_LCD_WF12_ADDR(x), BP_LCD_WF12_BPFLCD12, BS_LCD_WF12_BPFLCD12))

/*! @brief Format value for bitfield LCD_WF12_BPFLCD12. */
#define BF_LCD_WF12_BPFLCD12(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF12_BPFLCD12) & BM_LCD_WF12_BPFLCD12)

/*! @brief Set the BPFLCD12 field to a new value. */
#define BW_LCD_WF12_BPFLCD12(x, v) (BME_BFI8(HW_LCD_WF12_ADDR(x), ((uint8_t)(v) << BP_LCD_WF12_BPFLCD12), BP_LCD_WF12_BPFLCD12, 1))
/*@}*/

/*!
 * @name Register LCD_WF12, field BPGLCD12[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF12_BPGLCD12 (6U)          /*!< Bit position for LCD_WF12_BPGLCD12. */
#define BM_LCD_WF12_BPGLCD12 (0x40U)       /*!< Bit mask for LCD_WF12_BPGLCD12. */
#define BS_LCD_WF12_BPGLCD12 (1U)          /*!< Bit field size in bits for LCD_WF12_BPGLCD12. */

/*! @brief Read current value of the LCD_WF12_BPGLCD12 field. */
#define BR_LCD_WF12_BPGLCD12(x) (BME_UBFX8(HW_LCD_WF12_ADDR(x), BP_LCD_WF12_BPGLCD12, BS_LCD_WF12_BPGLCD12))

/*! @brief Format value for bitfield LCD_WF12_BPGLCD12. */
#define BF_LCD_WF12_BPGLCD12(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF12_BPGLCD12) & BM_LCD_WF12_BPGLCD12)

/*! @brief Set the BPGLCD12 field to a new value. */
#define BW_LCD_WF12_BPGLCD12(x, v) (BME_BFI8(HW_LCD_WF12_ADDR(x), ((uint8_t)(v) << BP_LCD_WF12_BPGLCD12), BP_LCD_WF12_BPGLCD12, 1))
/*@}*/

/*!
 * @name Register LCD_WF12, field BPHLCD12[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF12_BPHLCD12 (7U)          /*!< Bit position for LCD_WF12_BPHLCD12. */
#define BM_LCD_WF12_BPHLCD12 (0x80U)       /*!< Bit mask for LCD_WF12_BPHLCD12. */
#define BS_LCD_WF12_BPHLCD12 (1U)          /*!< Bit field size in bits for LCD_WF12_BPHLCD12. */

/*! @brief Read current value of the LCD_WF12_BPHLCD12 field. */
#define BR_LCD_WF12_BPHLCD12(x) (BME_UBFX8(HW_LCD_WF12_ADDR(x), BP_LCD_WF12_BPHLCD12, BS_LCD_WF12_BPHLCD12))

/*! @brief Format value for bitfield LCD_WF12_BPHLCD12. */
#define BF_LCD_WF12_BPHLCD12(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF12_BPHLCD12) & BM_LCD_WF12_BPHLCD12)

/*! @brief Set the BPHLCD12 field to a new value. */
#define BW_LCD_WF12_BPHLCD12(x, v) (BME_BFI8(HW_LCD_WF12_ADDR(x), ((uint8_t)(v) << BP_LCD_WF12_BPHLCD12), BP_LCD_WF12_BPHLCD12, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF13 - LCD Waveform Register 13.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF13 - LCD Waveform Register 13. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf13
{
    uint8_t U;
    struct _hw_lcd_wf13_bitfields
    {
        uint8_t BPALCD13 : 1;          /*!< [0]  */
        uint8_t BPBLCD13 : 1;          /*!< [1]  */
        uint8_t BPCLCD13 : 1;          /*!< [2]  */
        uint8_t BPDLCD13 : 1;          /*!< [3]  */
        uint8_t BPELCD13 : 1;          /*!< [4]  */
        uint8_t BPFLCD13 : 1;          /*!< [5]  */
        uint8_t BPGLCD13 : 1;          /*!< [6]  */
        uint8_t BPHLCD13 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf13_t;

/*!
 * @name Constants and macros for entire LCD_WF13 register
 */
/*@{*/
#define HW_LCD_WF13_ADDR(x)      ((x) + 0x2DU)

#define HW_LCD_WF13(x)           (*(__IO hw_lcd_wf13_t *) HW_LCD_WF13_ADDR(x))
#define HW_LCD_WF13_RD(x)        (HW_LCD_WF13(x).U)
#define HW_LCD_WF13_WR(x, v)     (HW_LCD_WF13(x).U = (v))
#define HW_LCD_WF13_SET(x, v)    (BME_OR8(HW_LCD_WF13_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF13_CLR(x, v)    (BME_AND8(HW_LCD_WF13_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF13_TOG(x, v)    (BME_XOR8(HW_LCD_WF13_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF13 bitfields
 */

/*!
 * @name Register LCD_WF13, field BPALCD13[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF13_BPALCD13 (0U)          /*!< Bit position for LCD_WF13_BPALCD13. */
#define BM_LCD_WF13_BPALCD13 (0x01U)       /*!< Bit mask for LCD_WF13_BPALCD13. */
#define BS_LCD_WF13_BPALCD13 (1U)          /*!< Bit field size in bits for LCD_WF13_BPALCD13. */

/*! @brief Read current value of the LCD_WF13_BPALCD13 field. */
#define BR_LCD_WF13_BPALCD13(x) (BME_UBFX8(HW_LCD_WF13_ADDR(x), BP_LCD_WF13_BPALCD13, BS_LCD_WF13_BPALCD13))

/*! @brief Format value for bitfield LCD_WF13_BPALCD13. */
#define BF_LCD_WF13_BPALCD13(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF13_BPALCD13) & BM_LCD_WF13_BPALCD13)

/*! @brief Set the BPALCD13 field to a new value. */
#define BW_LCD_WF13_BPALCD13(x, v) (BME_BFI8(HW_LCD_WF13_ADDR(x), ((uint8_t)(v) << BP_LCD_WF13_BPALCD13), BP_LCD_WF13_BPALCD13, 1))
/*@}*/

/*!
 * @name Register LCD_WF13, field BPBLCD13[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF13_BPBLCD13 (1U)          /*!< Bit position for LCD_WF13_BPBLCD13. */
#define BM_LCD_WF13_BPBLCD13 (0x02U)       /*!< Bit mask for LCD_WF13_BPBLCD13. */
#define BS_LCD_WF13_BPBLCD13 (1U)          /*!< Bit field size in bits for LCD_WF13_BPBLCD13. */

/*! @brief Read current value of the LCD_WF13_BPBLCD13 field. */
#define BR_LCD_WF13_BPBLCD13(x) (BME_UBFX8(HW_LCD_WF13_ADDR(x), BP_LCD_WF13_BPBLCD13, BS_LCD_WF13_BPBLCD13))

/*! @brief Format value for bitfield LCD_WF13_BPBLCD13. */
#define BF_LCD_WF13_BPBLCD13(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF13_BPBLCD13) & BM_LCD_WF13_BPBLCD13)

/*! @brief Set the BPBLCD13 field to a new value. */
#define BW_LCD_WF13_BPBLCD13(x, v) (BME_BFI8(HW_LCD_WF13_ADDR(x), ((uint8_t)(v) << BP_LCD_WF13_BPBLCD13), BP_LCD_WF13_BPBLCD13, 1))
/*@}*/

/*!
 * @name Register LCD_WF13, field BPCLCD13[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF13_BPCLCD13 (2U)          /*!< Bit position for LCD_WF13_BPCLCD13. */
#define BM_LCD_WF13_BPCLCD13 (0x04U)       /*!< Bit mask for LCD_WF13_BPCLCD13. */
#define BS_LCD_WF13_BPCLCD13 (1U)          /*!< Bit field size in bits for LCD_WF13_BPCLCD13. */

/*! @brief Read current value of the LCD_WF13_BPCLCD13 field. */
#define BR_LCD_WF13_BPCLCD13(x) (BME_UBFX8(HW_LCD_WF13_ADDR(x), BP_LCD_WF13_BPCLCD13, BS_LCD_WF13_BPCLCD13))

/*! @brief Format value for bitfield LCD_WF13_BPCLCD13. */
#define BF_LCD_WF13_BPCLCD13(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF13_BPCLCD13) & BM_LCD_WF13_BPCLCD13)

/*! @brief Set the BPCLCD13 field to a new value. */
#define BW_LCD_WF13_BPCLCD13(x, v) (BME_BFI8(HW_LCD_WF13_ADDR(x), ((uint8_t)(v) << BP_LCD_WF13_BPCLCD13), BP_LCD_WF13_BPCLCD13, 1))
/*@}*/

/*!
 * @name Register LCD_WF13, field BPDLCD13[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF13_BPDLCD13 (3U)          /*!< Bit position for LCD_WF13_BPDLCD13. */
#define BM_LCD_WF13_BPDLCD13 (0x08U)       /*!< Bit mask for LCD_WF13_BPDLCD13. */
#define BS_LCD_WF13_BPDLCD13 (1U)          /*!< Bit field size in bits for LCD_WF13_BPDLCD13. */

/*! @brief Read current value of the LCD_WF13_BPDLCD13 field. */
#define BR_LCD_WF13_BPDLCD13(x) (BME_UBFX8(HW_LCD_WF13_ADDR(x), BP_LCD_WF13_BPDLCD13, BS_LCD_WF13_BPDLCD13))

/*! @brief Format value for bitfield LCD_WF13_BPDLCD13. */
#define BF_LCD_WF13_BPDLCD13(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF13_BPDLCD13) & BM_LCD_WF13_BPDLCD13)

/*! @brief Set the BPDLCD13 field to a new value. */
#define BW_LCD_WF13_BPDLCD13(x, v) (BME_BFI8(HW_LCD_WF13_ADDR(x), ((uint8_t)(v) << BP_LCD_WF13_BPDLCD13), BP_LCD_WF13_BPDLCD13, 1))
/*@}*/

/*!
 * @name Register LCD_WF13, field BPELCD13[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF13_BPELCD13 (4U)          /*!< Bit position for LCD_WF13_BPELCD13. */
#define BM_LCD_WF13_BPELCD13 (0x10U)       /*!< Bit mask for LCD_WF13_BPELCD13. */
#define BS_LCD_WF13_BPELCD13 (1U)          /*!< Bit field size in bits for LCD_WF13_BPELCD13. */

/*! @brief Read current value of the LCD_WF13_BPELCD13 field. */
#define BR_LCD_WF13_BPELCD13(x) (BME_UBFX8(HW_LCD_WF13_ADDR(x), BP_LCD_WF13_BPELCD13, BS_LCD_WF13_BPELCD13))

/*! @brief Format value for bitfield LCD_WF13_BPELCD13. */
#define BF_LCD_WF13_BPELCD13(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF13_BPELCD13) & BM_LCD_WF13_BPELCD13)

/*! @brief Set the BPELCD13 field to a new value. */
#define BW_LCD_WF13_BPELCD13(x, v) (BME_BFI8(HW_LCD_WF13_ADDR(x), ((uint8_t)(v) << BP_LCD_WF13_BPELCD13), BP_LCD_WF13_BPELCD13, 1))
/*@}*/

/*!
 * @name Register LCD_WF13, field BPFLCD13[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF13_BPFLCD13 (5U)          /*!< Bit position for LCD_WF13_BPFLCD13. */
#define BM_LCD_WF13_BPFLCD13 (0x20U)       /*!< Bit mask for LCD_WF13_BPFLCD13. */
#define BS_LCD_WF13_BPFLCD13 (1U)          /*!< Bit field size in bits for LCD_WF13_BPFLCD13. */

/*! @brief Read current value of the LCD_WF13_BPFLCD13 field. */
#define BR_LCD_WF13_BPFLCD13(x) (BME_UBFX8(HW_LCD_WF13_ADDR(x), BP_LCD_WF13_BPFLCD13, BS_LCD_WF13_BPFLCD13))

/*! @brief Format value for bitfield LCD_WF13_BPFLCD13. */
#define BF_LCD_WF13_BPFLCD13(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF13_BPFLCD13) & BM_LCD_WF13_BPFLCD13)

/*! @brief Set the BPFLCD13 field to a new value. */
#define BW_LCD_WF13_BPFLCD13(x, v) (BME_BFI8(HW_LCD_WF13_ADDR(x), ((uint8_t)(v) << BP_LCD_WF13_BPFLCD13), BP_LCD_WF13_BPFLCD13, 1))
/*@}*/

/*!
 * @name Register LCD_WF13, field BPGLCD13[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF13_BPGLCD13 (6U)          /*!< Bit position for LCD_WF13_BPGLCD13. */
#define BM_LCD_WF13_BPGLCD13 (0x40U)       /*!< Bit mask for LCD_WF13_BPGLCD13. */
#define BS_LCD_WF13_BPGLCD13 (1U)          /*!< Bit field size in bits for LCD_WF13_BPGLCD13. */

/*! @brief Read current value of the LCD_WF13_BPGLCD13 field. */
#define BR_LCD_WF13_BPGLCD13(x) (BME_UBFX8(HW_LCD_WF13_ADDR(x), BP_LCD_WF13_BPGLCD13, BS_LCD_WF13_BPGLCD13))

/*! @brief Format value for bitfield LCD_WF13_BPGLCD13. */
#define BF_LCD_WF13_BPGLCD13(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF13_BPGLCD13) & BM_LCD_WF13_BPGLCD13)

/*! @brief Set the BPGLCD13 field to a new value. */
#define BW_LCD_WF13_BPGLCD13(x, v) (BME_BFI8(HW_LCD_WF13_ADDR(x), ((uint8_t)(v) << BP_LCD_WF13_BPGLCD13), BP_LCD_WF13_BPGLCD13, 1))
/*@}*/

/*!
 * @name Register LCD_WF13, field BPHLCD13[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF13_BPHLCD13 (7U)          /*!< Bit position for LCD_WF13_BPHLCD13. */
#define BM_LCD_WF13_BPHLCD13 (0x80U)       /*!< Bit mask for LCD_WF13_BPHLCD13. */
#define BS_LCD_WF13_BPHLCD13 (1U)          /*!< Bit field size in bits for LCD_WF13_BPHLCD13. */

/*! @brief Read current value of the LCD_WF13_BPHLCD13 field. */
#define BR_LCD_WF13_BPHLCD13(x) (BME_UBFX8(HW_LCD_WF13_ADDR(x), BP_LCD_WF13_BPHLCD13, BS_LCD_WF13_BPHLCD13))

/*! @brief Format value for bitfield LCD_WF13_BPHLCD13. */
#define BF_LCD_WF13_BPHLCD13(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF13_BPHLCD13) & BM_LCD_WF13_BPHLCD13)

/*! @brief Set the BPHLCD13 field to a new value. */
#define BW_LCD_WF13_BPHLCD13(x, v) (BME_BFI8(HW_LCD_WF13_ADDR(x), ((uint8_t)(v) << BP_LCD_WF13_BPHLCD13), BP_LCD_WF13_BPHLCD13, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF14 - LCD Waveform Register 14.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF14 - LCD Waveform Register 14. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf14
{
    uint8_t U;
    struct _hw_lcd_wf14_bitfields
    {
        uint8_t BPALCD14 : 1;          /*!< [0]  */
        uint8_t BPBLCD14 : 1;          /*!< [1]  */
        uint8_t BPCLCD14 : 1;          /*!< [2]  */
        uint8_t BPDLCD14 : 1;          /*!< [3]  */
        uint8_t BPELCD14 : 1;          /*!< [4]  */
        uint8_t BPFLCD14 : 1;          /*!< [5]  */
        uint8_t BPGLCD14 : 1;          /*!< [6]  */
        uint8_t BPHLCD14 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf14_t;

/*!
 * @name Constants and macros for entire LCD_WF14 register
 */
/*@{*/
#define HW_LCD_WF14_ADDR(x)      ((x) + 0x2EU)

#define HW_LCD_WF14(x)           (*(__IO hw_lcd_wf14_t *) HW_LCD_WF14_ADDR(x))
#define HW_LCD_WF14_RD(x)        (HW_LCD_WF14(x).U)
#define HW_LCD_WF14_WR(x, v)     (HW_LCD_WF14(x).U = (v))
#define HW_LCD_WF14_SET(x, v)    (BME_OR8(HW_LCD_WF14_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF14_CLR(x, v)    (BME_AND8(HW_LCD_WF14_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF14_TOG(x, v)    (BME_XOR8(HW_LCD_WF14_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF14 bitfields
 */

/*!
 * @name Register LCD_WF14, field BPALCD14[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF14_BPALCD14 (0U)          /*!< Bit position for LCD_WF14_BPALCD14. */
#define BM_LCD_WF14_BPALCD14 (0x01U)       /*!< Bit mask for LCD_WF14_BPALCD14. */
#define BS_LCD_WF14_BPALCD14 (1U)          /*!< Bit field size in bits for LCD_WF14_BPALCD14. */

/*! @brief Read current value of the LCD_WF14_BPALCD14 field. */
#define BR_LCD_WF14_BPALCD14(x) (BME_UBFX8(HW_LCD_WF14_ADDR(x), BP_LCD_WF14_BPALCD14, BS_LCD_WF14_BPALCD14))

/*! @brief Format value for bitfield LCD_WF14_BPALCD14. */
#define BF_LCD_WF14_BPALCD14(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF14_BPALCD14) & BM_LCD_WF14_BPALCD14)

/*! @brief Set the BPALCD14 field to a new value. */
#define BW_LCD_WF14_BPALCD14(x, v) (BME_BFI8(HW_LCD_WF14_ADDR(x), ((uint8_t)(v) << BP_LCD_WF14_BPALCD14), BP_LCD_WF14_BPALCD14, 1))
/*@}*/

/*!
 * @name Register LCD_WF14, field BPBLCD14[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF14_BPBLCD14 (1U)          /*!< Bit position for LCD_WF14_BPBLCD14. */
#define BM_LCD_WF14_BPBLCD14 (0x02U)       /*!< Bit mask for LCD_WF14_BPBLCD14. */
#define BS_LCD_WF14_BPBLCD14 (1U)          /*!< Bit field size in bits for LCD_WF14_BPBLCD14. */

/*! @brief Read current value of the LCD_WF14_BPBLCD14 field. */
#define BR_LCD_WF14_BPBLCD14(x) (BME_UBFX8(HW_LCD_WF14_ADDR(x), BP_LCD_WF14_BPBLCD14, BS_LCD_WF14_BPBLCD14))

/*! @brief Format value for bitfield LCD_WF14_BPBLCD14. */
#define BF_LCD_WF14_BPBLCD14(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF14_BPBLCD14) & BM_LCD_WF14_BPBLCD14)

/*! @brief Set the BPBLCD14 field to a new value. */
#define BW_LCD_WF14_BPBLCD14(x, v) (BME_BFI8(HW_LCD_WF14_ADDR(x), ((uint8_t)(v) << BP_LCD_WF14_BPBLCD14), BP_LCD_WF14_BPBLCD14, 1))
/*@}*/

/*!
 * @name Register LCD_WF14, field BPCLCD14[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF14_BPCLCD14 (2U)          /*!< Bit position for LCD_WF14_BPCLCD14. */
#define BM_LCD_WF14_BPCLCD14 (0x04U)       /*!< Bit mask for LCD_WF14_BPCLCD14. */
#define BS_LCD_WF14_BPCLCD14 (1U)          /*!< Bit field size in bits for LCD_WF14_BPCLCD14. */

/*! @brief Read current value of the LCD_WF14_BPCLCD14 field. */
#define BR_LCD_WF14_BPCLCD14(x) (BME_UBFX8(HW_LCD_WF14_ADDR(x), BP_LCD_WF14_BPCLCD14, BS_LCD_WF14_BPCLCD14))

/*! @brief Format value for bitfield LCD_WF14_BPCLCD14. */
#define BF_LCD_WF14_BPCLCD14(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF14_BPCLCD14) & BM_LCD_WF14_BPCLCD14)

/*! @brief Set the BPCLCD14 field to a new value. */
#define BW_LCD_WF14_BPCLCD14(x, v) (BME_BFI8(HW_LCD_WF14_ADDR(x), ((uint8_t)(v) << BP_LCD_WF14_BPCLCD14), BP_LCD_WF14_BPCLCD14, 1))
/*@}*/

/*!
 * @name Register LCD_WF14, field BPDLCD14[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF14_BPDLCD14 (3U)          /*!< Bit position for LCD_WF14_BPDLCD14. */
#define BM_LCD_WF14_BPDLCD14 (0x08U)       /*!< Bit mask for LCD_WF14_BPDLCD14. */
#define BS_LCD_WF14_BPDLCD14 (1U)          /*!< Bit field size in bits for LCD_WF14_BPDLCD14. */

/*! @brief Read current value of the LCD_WF14_BPDLCD14 field. */
#define BR_LCD_WF14_BPDLCD14(x) (BME_UBFX8(HW_LCD_WF14_ADDR(x), BP_LCD_WF14_BPDLCD14, BS_LCD_WF14_BPDLCD14))

/*! @brief Format value for bitfield LCD_WF14_BPDLCD14. */
#define BF_LCD_WF14_BPDLCD14(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF14_BPDLCD14) & BM_LCD_WF14_BPDLCD14)

/*! @brief Set the BPDLCD14 field to a new value. */
#define BW_LCD_WF14_BPDLCD14(x, v) (BME_BFI8(HW_LCD_WF14_ADDR(x), ((uint8_t)(v) << BP_LCD_WF14_BPDLCD14), BP_LCD_WF14_BPDLCD14, 1))
/*@}*/

/*!
 * @name Register LCD_WF14, field BPELCD14[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF14_BPELCD14 (4U)          /*!< Bit position for LCD_WF14_BPELCD14. */
#define BM_LCD_WF14_BPELCD14 (0x10U)       /*!< Bit mask for LCD_WF14_BPELCD14. */
#define BS_LCD_WF14_BPELCD14 (1U)          /*!< Bit field size in bits for LCD_WF14_BPELCD14. */

/*! @brief Read current value of the LCD_WF14_BPELCD14 field. */
#define BR_LCD_WF14_BPELCD14(x) (BME_UBFX8(HW_LCD_WF14_ADDR(x), BP_LCD_WF14_BPELCD14, BS_LCD_WF14_BPELCD14))

/*! @brief Format value for bitfield LCD_WF14_BPELCD14. */
#define BF_LCD_WF14_BPELCD14(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF14_BPELCD14) & BM_LCD_WF14_BPELCD14)

/*! @brief Set the BPELCD14 field to a new value. */
#define BW_LCD_WF14_BPELCD14(x, v) (BME_BFI8(HW_LCD_WF14_ADDR(x), ((uint8_t)(v) << BP_LCD_WF14_BPELCD14), BP_LCD_WF14_BPELCD14, 1))
/*@}*/

/*!
 * @name Register LCD_WF14, field BPFLCD14[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF14_BPFLCD14 (5U)          /*!< Bit position for LCD_WF14_BPFLCD14. */
#define BM_LCD_WF14_BPFLCD14 (0x20U)       /*!< Bit mask for LCD_WF14_BPFLCD14. */
#define BS_LCD_WF14_BPFLCD14 (1U)          /*!< Bit field size in bits for LCD_WF14_BPFLCD14. */

/*! @brief Read current value of the LCD_WF14_BPFLCD14 field. */
#define BR_LCD_WF14_BPFLCD14(x) (BME_UBFX8(HW_LCD_WF14_ADDR(x), BP_LCD_WF14_BPFLCD14, BS_LCD_WF14_BPFLCD14))

/*! @brief Format value for bitfield LCD_WF14_BPFLCD14. */
#define BF_LCD_WF14_BPFLCD14(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF14_BPFLCD14) & BM_LCD_WF14_BPFLCD14)

/*! @brief Set the BPFLCD14 field to a new value. */
#define BW_LCD_WF14_BPFLCD14(x, v) (BME_BFI8(HW_LCD_WF14_ADDR(x), ((uint8_t)(v) << BP_LCD_WF14_BPFLCD14), BP_LCD_WF14_BPFLCD14, 1))
/*@}*/

/*!
 * @name Register LCD_WF14, field BPGLCD14[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF14_BPGLCD14 (6U)          /*!< Bit position for LCD_WF14_BPGLCD14. */
#define BM_LCD_WF14_BPGLCD14 (0x40U)       /*!< Bit mask for LCD_WF14_BPGLCD14. */
#define BS_LCD_WF14_BPGLCD14 (1U)          /*!< Bit field size in bits for LCD_WF14_BPGLCD14. */

/*! @brief Read current value of the LCD_WF14_BPGLCD14 field. */
#define BR_LCD_WF14_BPGLCD14(x) (BME_UBFX8(HW_LCD_WF14_ADDR(x), BP_LCD_WF14_BPGLCD14, BS_LCD_WF14_BPGLCD14))

/*! @brief Format value for bitfield LCD_WF14_BPGLCD14. */
#define BF_LCD_WF14_BPGLCD14(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF14_BPGLCD14) & BM_LCD_WF14_BPGLCD14)

/*! @brief Set the BPGLCD14 field to a new value. */
#define BW_LCD_WF14_BPGLCD14(x, v) (BME_BFI8(HW_LCD_WF14_ADDR(x), ((uint8_t)(v) << BP_LCD_WF14_BPGLCD14), BP_LCD_WF14_BPGLCD14, 1))
/*@}*/

/*!
 * @name Register LCD_WF14, field BPHLCD14[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF14_BPHLCD14 (7U)          /*!< Bit position for LCD_WF14_BPHLCD14. */
#define BM_LCD_WF14_BPHLCD14 (0x80U)       /*!< Bit mask for LCD_WF14_BPHLCD14. */
#define BS_LCD_WF14_BPHLCD14 (1U)          /*!< Bit field size in bits for LCD_WF14_BPHLCD14. */

/*! @brief Read current value of the LCD_WF14_BPHLCD14 field. */
#define BR_LCD_WF14_BPHLCD14(x) (BME_UBFX8(HW_LCD_WF14_ADDR(x), BP_LCD_WF14_BPHLCD14, BS_LCD_WF14_BPHLCD14))

/*! @brief Format value for bitfield LCD_WF14_BPHLCD14. */
#define BF_LCD_WF14_BPHLCD14(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF14_BPHLCD14) & BM_LCD_WF14_BPHLCD14)

/*! @brief Set the BPHLCD14 field to a new value. */
#define BW_LCD_WF14_BPHLCD14(x, v) (BME_BFI8(HW_LCD_WF14_ADDR(x), ((uint8_t)(v) << BP_LCD_WF14_BPHLCD14), BP_LCD_WF14_BPHLCD14, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF15 - LCD Waveform Register 15.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF15 - LCD Waveform Register 15. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf15
{
    uint8_t U;
    struct _hw_lcd_wf15_bitfields
    {
        uint8_t BPALCD15 : 1;          /*!< [0]  */
        uint8_t BPBLCD15 : 1;          /*!< [1]  */
        uint8_t BPCLCD15 : 1;          /*!< [2]  */
        uint8_t BPDLCD15 : 1;          /*!< [3]  */
        uint8_t BPELCD15 : 1;          /*!< [4]  */
        uint8_t BPFLCD15 : 1;          /*!< [5]  */
        uint8_t BPGLCD15 : 1;          /*!< [6]  */
        uint8_t BPHLCD15 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf15_t;

/*!
 * @name Constants and macros for entire LCD_WF15 register
 */
/*@{*/
#define HW_LCD_WF15_ADDR(x)      ((x) + 0x2FU)

#define HW_LCD_WF15(x)           (*(__IO hw_lcd_wf15_t *) HW_LCD_WF15_ADDR(x))
#define HW_LCD_WF15_RD(x)        (HW_LCD_WF15(x).U)
#define HW_LCD_WF15_WR(x, v)     (HW_LCD_WF15(x).U = (v))
#define HW_LCD_WF15_SET(x, v)    (BME_OR8(HW_LCD_WF15_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF15_CLR(x, v)    (BME_AND8(HW_LCD_WF15_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF15_TOG(x, v)    (BME_XOR8(HW_LCD_WF15_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF15 bitfields
 */

/*!
 * @name Register LCD_WF15, field BPALCD15[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF15_BPALCD15 (0U)          /*!< Bit position for LCD_WF15_BPALCD15. */
#define BM_LCD_WF15_BPALCD15 (0x01U)       /*!< Bit mask for LCD_WF15_BPALCD15. */
#define BS_LCD_WF15_BPALCD15 (1U)          /*!< Bit field size in bits for LCD_WF15_BPALCD15. */

/*! @brief Read current value of the LCD_WF15_BPALCD15 field. */
#define BR_LCD_WF15_BPALCD15(x) (BME_UBFX8(HW_LCD_WF15_ADDR(x), BP_LCD_WF15_BPALCD15, BS_LCD_WF15_BPALCD15))

/*! @brief Format value for bitfield LCD_WF15_BPALCD15. */
#define BF_LCD_WF15_BPALCD15(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF15_BPALCD15) & BM_LCD_WF15_BPALCD15)

/*! @brief Set the BPALCD15 field to a new value. */
#define BW_LCD_WF15_BPALCD15(x, v) (BME_BFI8(HW_LCD_WF15_ADDR(x), ((uint8_t)(v) << BP_LCD_WF15_BPALCD15), BP_LCD_WF15_BPALCD15, 1))
/*@}*/

/*!
 * @name Register LCD_WF15, field BPBLCD15[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF15_BPBLCD15 (1U)          /*!< Bit position for LCD_WF15_BPBLCD15. */
#define BM_LCD_WF15_BPBLCD15 (0x02U)       /*!< Bit mask for LCD_WF15_BPBLCD15. */
#define BS_LCD_WF15_BPBLCD15 (1U)          /*!< Bit field size in bits for LCD_WF15_BPBLCD15. */

/*! @brief Read current value of the LCD_WF15_BPBLCD15 field. */
#define BR_LCD_WF15_BPBLCD15(x) (BME_UBFX8(HW_LCD_WF15_ADDR(x), BP_LCD_WF15_BPBLCD15, BS_LCD_WF15_BPBLCD15))

/*! @brief Format value for bitfield LCD_WF15_BPBLCD15. */
#define BF_LCD_WF15_BPBLCD15(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF15_BPBLCD15) & BM_LCD_WF15_BPBLCD15)

/*! @brief Set the BPBLCD15 field to a new value. */
#define BW_LCD_WF15_BPBLCD15(x, v) (BME_BFI8(HW_LCD_WF15_ADDR(x), ((uint8_t)(v) << BP_LCD_WF15_BPBLCD15), BP_LCD_WF15_BPBLCD15, 1))
/*@}*/

/*!
 * @name Register LCD_WF15, field BPCLCD15[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF15_BPCLCD15 (2U)          /*!< Bit position for LCD_WF15_BPCLCD15. */
#define BM_LCD_WF15_BPCLCD15 (0x04U)       /*!< Bit mask for LCD_WF15_BPCLCD15. */
#define BS_LCD_WF15_BPCLCD15 (1U)          /*!< Bit field size in bits for LCD_WF15_BPCLCD15. */

/*! @brief Read current value of the LCD_WF15_BPCLCD15 field. */
#define BR_LCD_WF15_BPCLCD15(x) (BME_UBFX8(HW_LCD_WF15_ADDR(x), BP_LCD_WF15_BPCLCD15, BS_LCD_WF15_BPCLCD15))

/*! @brief Format value for bitfield LCD_WF15_BPCLCD15. */
#define BF_LCD_WF15_BPCLCD15(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF15_BPCLCD15) & BM_LCD_WF15_BPCLCD15)

/*! @brief Set the BPCLCD15 field to a new value. */
#define BW_LCD_WF15_BPCLCD15(x, v) (BME_BFI8(HW_LCD_WF15_ADDR(x), ((uint8_t)(v) << BP_LCD_WF15_BPCLCD15), BP_LCD_WF15_BPCLCD15, 1))
/*@}*/

/*!
 * @name Register LCD_WF15, field BPDLCD15[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF15_BPDLCD15 (3U)          /*!< Bit position for LCD_WF15_BPDLCD15. */
#define BM_LCD_WF15_BPDLCD15 (0x08U)       /*!< Bit mask for LCD_WF15_BPDLCD15. */
#define BS_LCD_WF15_BPDLCD15 (1U)          /*!< Bit field size in bits for LCD_WF15_BPDLCD15. */

/*! @brief Read current value of the LCD_WF15_BPDLCD15 field. */
#define BR_LCD_WF15_BPDLCD15(x) (BME_UBFX8(HW_LCD_WF15_ADDR(x), BP_LCD_WF15_BPDLCD15, BS_LCD_WF15_BPDLCD15))

/*! @brief Format value for bitfield LCD_WF15_BPDLCD15. */
#define BF_LCD_WF15_BPDLCD15(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF15_BPDLCD15) & BM_LCD_WF15_BPDLCD15)

/*! @brief Set the BPDLCD15 field to a new value. */
#define BW_LCD_WF15_BPDLCD15(x, v) (BME_BFI8(HW_LCD_WF15_ADDR(x), ((uint8_t)(v) << BP_LCD_WF15_BPDLCD15), BP_LCD_WF15_BPDLCD15, 1))
/*@}*/

/*!
 * @name Register LCD_WF15, field BPELCD15[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF15_BPELCD15 (4U)          /*!< Bit position for LCD_WF15_BPELCD15. */
#define BM_LCD_WF15_BPELCD15 (0x10U)       /*!< Bit mask for LCD_WF15_BPELCD15. */
#define BS_LCD_WF15_BPELCD15 (1U)          /*!< Bit field size in bits for LCD_WF15_BPELCD15. */

/*! @brief Read current value of the LCD_WF15_BPELCD15 field. */
#define BR_LCD_WF15_BPELCD15(x) (BME_UBFX8(HW_LCD_WF15_ADDR(x), BP_LCD_WF15_BPELCD15, BS_LCD_WF15_BPELCD15))

/*! @brief Format value for bitfield LCD_WF15_BPELCD15. */
#define BF_LCD_WF15_BPELCD15(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF15_BPELCD15) & BM_LCD_WF15_BPELCD15)

/*! @brief Set the BPELCD15 field to a new value. */
#define BW_LCD_WF15_BPELCD15(x, v) (BME_BFI8(HW_LCD_WF15_ADDR(x), ((uint8_t)(v) << BP_LCD_WF15_BPELCD15), BP_LCD_WF15_BPELCD15, 1))
/*@}*/

/*!
 * @name Register LCD_WF15, field BPFLCD15[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF15_BPFLCD15 (5U)          /*!< Bit position for LCD_WF15_BPFLCD15. */
#define BM_LCD_WF15_BPFLCD15 (0x20U)       /*!< Bit mask for LCD_WF15_BPFLCD15. */
#define BS_LCD_WF15_BPFLCD15 (1U)          /*!< Bit field size in bits for LCD_WF15_BPFLCD15. */

/*! @brief Read current value of the LCD_WF15_BPFLCD15 field. */
#define BR_LCD_WF15_BPFLCD15(x) (BME_UBFX8(HW_LCD_WF15_ADDR(x), BP_LCD_WF15_BPFLCD15, BS_LCD_WF15_BPFLCD15))

/*! @brief Format value for bitfield LCD_WF15_BPFLCD15. */
#define BF_LCD_WF15_BPFLCD15(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF15_BPFLCD15) & BM_LCD_WF15_BPFLCD15)

/*! @brief Set the BPFLCD15 field to a new value. */
#define BW_LCD_WF15_BPFLCD15(x, v) (BME_BFI8(HW_LCD_WF15_ADDR(x), ((uint8_t)(v) << BP_LCD_WF15_BPFLCD15), BP_LCD_WF15_BPFLCD15, 1))
/*@}*/

/*!
 * @name Register LCD_WF15, field BPGLCD15[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF15_BPGLCD15 (6U)          /*!< Bit position for LCD_WF15_BPGLCD15. */
#define BM_LCD_WF15_BPGLCD15 (0x40U)       /*!< Bit mask for LCD_WF15_BPGLCD15. */
#define BS_LCD_WF15_BPGLCD15 (1U)          /*!< Bit field size in bits for LCD_WF15_BPGLCD15. */

/*! @brief Read current value of the LCD_WF15_BPGLCD15 field. */
#define BR_LCD_WF15_BPGLCD15(x) (BME_UBFX8(HW_LCD_WF15_ADDR(x), BP_LCD_WF15_BPGLCD15, BS_LCD_WF15_BPGLCD15))

/*! @brief Format value for bitfield LCD_WF15_BPGLCD15. */
#define BF_LCD_WF15_BPGLCD15(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF15_BPGLCD15) & BM_LCD_WF15_BPGLCD15)

/*! @brief Set the BPGLCD15 field to a new value. */
#define BW_LCD_WF15_BPGLCD15(x, v) (BME_BFI8(HW_LCD_WF15_ADDR(x), ((uint8_t)(v) << BP_LCD_WF15_BPGLCD15), BP_LCD_WF15_BPGLCD15, 1))
/*@}*/

/*!
 * @name Register LCD_WF15, field BPHLCD15[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF15_BPHLCD15 (7U)          /*!< Bit position for LCD_WF15_BPHLCD15. */
#define BM_LCD_WF15_BPHLCD15 (0x80U)       /*!< Bit mask for LCD_WF15_BPHLCD15. */
#define BS_LCD_WF15_BPHLCD15 (1U)          /*!< Bit field size in bits for LCD_WF15_BPHLCD15. */

/*! @brief Read current value of the LCD_WF15_BPHLCD15 field. */
#define BR_LCD_WF15_BPHLCD15(x) (BME_UBFX8(HW_LCD_WF15_ADDR(x), BP_LCD_WF15_BPHLCD15, BS_LCD_WF15_BPHLCD15))

/*! @brief Format value for bitfield LCD_WF15_BPHLCD15. */
#define BF_LCD_WF15_BPHLCD15(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF15_BPHLCD15) & BM_LCD_WF15_BPHLCD15)

/*! @brief Set the BPHLCD15 field to a new value. */
#define BW_LCD_WF15_BPHLCD15(x, v) (BME_BFI8(HW_LCD_WF15_ADDR(x), ((uint8_t)(v) << BP_LCD_WF15_BPHLCD15), BP_LCD_WF15_BPHLCD15, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF16 - LCD Waveform Register 16.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF16 - LCD Waveform Register 16. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf16
{
    uint8_t U;
    struct _hw_lcd_wf16_bitfields
    {
        uint8_t BPALCD16 : 1;          /*!< [0]  */
        uint8_t BPBLCD16 : 1;          /*!< [1]  */
        uint8_t BPCLCD16 : 1;          /*!< [2]  */
        uint8_t BPDLCD16 : 1;          /*!< [3]  */
        uint8_t BPELCD16 : 1;          /*!< [4]  */
        uint8_t BPFLCD16 : 1;          /*!< [5]  */
        uint8_t BPGLCD16 : 1;          /*!< [6]  */
        uint8_t BPHLCD16 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf16_t;

/*!
 * @name Constants and macros for entire LCD_WF16 register
 */
/*@{*/
#define HW_LCD_WF16_ADDR(x)      ((x) + 0x30U)

#define HW_LCD_WF16(x)           (*(__IO hw_lcd_wf16_t *) HW_LCD_WF16_ADDR(x))
#define HW_LCD_WF16_RD(x)        (HW_LCD_WF16(x).U)
#define HW_LCD_WF16_WR(x, v)     (HW_LCD_WF16(x).U = (v))
#define HW_LCD_WF16_SET(x, v)    (BME_OR8(HW_LCD_WF16_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF16_CLR(x, v)    (BME_AND8(HW_LCD_WF16_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF16_TOG(x, v)    (BME_XOR8(HW_LCD_WF16_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF16 bitfields
 */

/*!
 * @name Register LCD_WF16, field BPALCD16[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF16_BPALCD16 (0U)          /*!< Bit position for LCD_WF16_BPALCD16. */
#define BM_LCD_WF16_BPALCD16 (0x01U)       /*!< Bit mask for LCD_WF16_BPALCD16. */
#define BS_LCD_WF16_BPALCD16 (1U)          /*!< Bit field size in bits for LCD_WF16_BPALCD16. */

/*! @brief Read current value of the LCD_WF16_BPALCD16 field. */
#define BR_LCD_WF16_BPALCD16(x) (BME_UBFX8(HW_LCD_WF16_ADDR(x), BP_LCD_WF16_BPALCD16, BS_LCD_WF16_BPALCD16))

/*! @brief Format value for bitfield LCD_WF16_BPALCD16. */
#define BF_LCD_WF16_BPALCD16(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF16_BPALCD16) & BM_LCD_WF16_BPALCD16)

/*! @brief Set the BPALCD16 field to a new value. */
#define BW_LCD_WF16_BPALCD16(x, v) (BME_BFI8(HW_LCD_WF16_ADDR(x), ((uint8_t)(v) << BP_LCD_WF16_BPALCD16), BP_LCD_WF16_BPALCD16, 1))
/*@}*/

/*!
 * @name Register LCD_WF16, field BPBLCD16[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF16_BPBLCD16 (1U)          /*!< Bit position for LCD_WF16_BPBLCD16. */
#define BM_LCD_WF16_BPBLCD16 (0x02U)       /*!< Bit mask for LCD_WF16_BPBLCD16. */
#define BS_LCD_WF16_BPBLCD16 (1U)          /*!< Bit field size in bits for LCD_WF16_BPBLCD16. */

/*! @brief Read current value of the LCD_WF16_BPBLCD16 field. */
#define BR_LCD_WF16_BPBLCD16(x) (BME_UBFX8(HW_LCD_WF16_ADDR(x), BP_LCD_WF16_BPBLCD16, BS_LCD_WF16_BPBLCD16))

/*! @brief Format value for bitfield LCD_WF16_BPBLCD16. */
#define BF_LCD_WF16_BPBLCD16(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF16_BPBLCD16) & BM_LCD_WF16_BPBLCD16)

/*! @brief Set the BPBLCD16 field to a new value. */
#define BW_LCD_WF16_BPBLCD16(x, v) (BME_BFI8(HW_LCD_WF16_ADDR(x), ((uint8_t)(v) << BP_LCD_WF16_BPBLCD16), BP_LCD_WF16_BPBLCD16, 1))
/*@}*/

/*!
 * @name Register LCD_WF16, field BPCLCD16[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF16_BPCLCD16 (2U)          /*!< Bit position for LCD_WF16_BPCLCD16. */
#define BM_LCD_WF16_BPCLCD16 (0x04U)       /*!< Bit mask for LCD_WF16_BPCLCD16. */
#define BS_LCD_WF16_BPCLCD16 (1U)          /*!< Bit field size in bits for LCD_WF16_BPCLCD16. */

/*! @brief Read current value of the LCD_WF16_BPCLCD16 field. */
#define BR_LCD_WF16_BPCLCD16(x) (BME_UBFX8(HW_LCD_WF16_ADDR(x), BP_LCD_WF16_BPCLCD16, BS_LCD_WF16_BPCLCD16))

/*! @brief Format value for bitfield LCD_WF16_BPCLCD16. */
#define BF_LCD_WF16_BPCLCD16(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF16_BPCLCD16) & BM_LCD_WF16_BPCLCD16)

/*! @brief Set the BPCLCD16 field to a new value. */
#define BW_LCD_WF16_BPCLCD16(x, v) (BME_BFI8(HW_LCD_WF16_ADDR(x), ((uint8_t)(v) << BP_LCD_WF16_BPCLCD16), BP_LCD_WF16_BPCLCD16, 1))
/*@}*/

/*!
 * @name Register LCD_WF16, field BPDLCD16[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF16_BPDLCD16 (3U)          /*!< Bit position for LCD_WF16_BPDLCD16. */
#define BM_LCD_WF16_BPDLCD16 (0x08U)       /*!< Bit mask for LCD_WF16_BPDLCD16. */
#define BS_LCD_WF16_BPDLCD16 (1U)          /*!< Bit field size in bits for LCD_WF16_BPDLCD16. */

/*! @brief Read current value of the LCD_WF16_BPDLCD16 field. */
#define BR_LCD_WF16_BPDLCD16(x) (BME_UBFX8(HW_LCD_WF16_ADDR(x), BP_LCD_WF16_BPDLCD16, BS_LCD_WF16_BPDLCD16))

/*! @brief Format value for bitfield LCD_WF16_BPDLCD16. */
#define BF_LCD_WF16_BPDLCD16(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF16_BPDLCD16) & BM_LCD_WF16_BPDLCD16)

/*! @brief Set the BPDLCD16 field to a new value. */
#define BW_LCD_WF16_BPDLCD16(x, v) (BME_BFI8(HW_LCD_WF16_ADDR(x), ((uint8_t)(v) << BP_LCD_WF16_BPDLCD16), BP_LCD_WF16_BPDLCD16, 1))
/*@}*/

/*!
 * @name Register LCD_WF16, field BPELCD16[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF16_BPELCD16 (4U)          /*!< Bit position for LCD_WF16_BPELCD16. */
#define BM_LCD_WF16_BPELCD16 (0x10U)       /*!< Bit mask for LCD_WF16_BPELCD16. */
#define BS_LCD_WF16_BPELCD16 (1U)          /*!< Bit field size in bits for LCD_WF16_BPELCD16. */

/*! @brief Read current value of the LCD_WF16_BPELCD16 field. */
#define BR_LCD_WF16_BPELCD16(x) (BME_UBFX8(HW_LCD_WF16_ADDR(x), BP_LCD_WF16_BPELCD16, BS_LCD_WF16_BPELCD16))

/*! @brief Format value for bitfield LCD_WF16_BPELCD16. */
#define BF_LCD_WF16_BPELCD16(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF16_BPELCD16) & BM_LCD_WF16_BPELCD16)

/*! @brief Set the BPELCD16 field to a new value. */
#define BW_LCD_WF16_BPELCD16(x, v) (BME_BFI8(HW_LCD_WF16_ADDR(x), ((uint8_t)(v) << BP_LCD_WF16_BPELCD16), BP_LCD_WF16_BPELCD16, 1))
/*@}*/

/*!
 * @name Register LCD_WF16, field BPFLCD16[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF16_BPFLCD16 (5U)          /*!< Bit position for LCD_WF16_BPFLCD16. */
#define BM_LCD_WF16_BPFLCD16 (0x20U)       /*!< Bit mask for LCD_WF16_BPFLCD16. */
#define BS_LCD_WF16_BPFLCD16 (1U)          /*!< Bit field size in bits for LCD_WF16_BPFLCD16. */

/*! @brief Read current value of the LCD_WF16_BPFLCD16 field. */
#define BR_LCD_WF16_BPFLCD16(x) (BME_UBFX8(HW_LCD_WF16_ADDR(x), BP_LCD_WF16_BPFLCD16, BS_LCD_WF16_BPFLCD16))

/*! @brief Format value for bitfield LCD_WF16_BPFLCD16. */
#define BF_LCD_WF16_BPFLCD16(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF16_BPFLCD16) & BM_LCD_WF16_BPFLCD16)

/*! @brief Set the BPFLCD16 field to a new value. */
#define BW_LCD_WF16_BPFLCD16(x, v) (BME_BFI8(HW_LCD_WF16_ADDR(x), ((uint8_t)(v) << BP_LCD_WF16_BPFLCD16), BP_LCD_WF16_BPFLCD16, 1))
/*@}*/

/*!
 * @name Register LCD_WF16, field BPGLCD16[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF16_BPGLCD16 (6U)          /*!< Bit position for LCD_WF16_BPGLCD16. */
#define BM_LCD_WF16_BPGLCD16 (0x40U)       /*!< Bit mask for LCD_WF16_BPGLCD16. */
#define BS_LCD_WF16_BPGLCD16 (1U)          /*!< Bit field size in bits for LCD_WF16_BPGLCD16. */

/*! @brief Read current value of the LCD_WF16_BPGLCD16 field. */
#define BR_LCD_WF16_BPGLCD16(x) (BME_UBFX8(HW_LCD_WF16_ADDR(x), BP_LCD_WF16_BPGLCD16, BS_LCD_WF16_BPGLCD16))

/*! @brief Format value for bitfield LCD_WF16_BPGLCD16. */
#define BF_LCD_WF16_BPGLCD16(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF16_BPGLCD16) & BM_LCD_WF16_BPGLCD16)

/*! @brief Set the BPGLCD16 field to a new value. */
#define BW_LCD_WF16_BPGLCD16(x, v) (BME_BFI8(HW_LCD_WF16_ADDR(x), ((uint8_t)(v) << BP_LCD_WF16_BPGLCD16), BP_LCD_WF16_BPGLCD16, 1))
/*@}*/

/*!
 * @name Register LCD_WF16, field BPHLCD16[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF16_BPHLCD16 (7U)          /*!< Bit position for LCD_WF16_BPHLCD16. */
#define BM_LCD_WF16_BPHLCD16 (0x80U)       /*!< Bit mask for LCD_WF16_BPHLCD16. */
#define BS_LCD_WF16_BPHLCD16 (1U)          /*!< Bit field size in bits for LCD_WF16_BPHLCD16. */

/*! @brief Read current value of the LCD_WF16_BPHLCD16 field. */
#define BR_LCD_WF16_BPHLCD16(x) (BME_UBFX8(HW_LCD_WF16_ADDR(x), BP_LCD_WF16_BPHLCD16, BS_LCD_WF16_BPHLCD16))

/*! @brief Format value for bitfield LCD_WF16_BPHLCD16. */
#define BF_LCD_WF16_BPHLCD16(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF16_BPHLCD16) & BM_LCD_WF16_BPHLCD16)

/*! @brief Set the BPHLCD16 field to a new value. */
#define BW_LCD_WF16_BPHLCD16(x, v) (BME_BFI8(HW_LCD_WF16_ADDR(x), ((uint8_t)(v) << BP_LCD_WF16_BPHLCD16), BP_LCD_WF16_BPHLCD16, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF17 - LCD Waveform Register 17.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF17 - LCD Waveform Register 17. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf17
{
    uint8_t U;
    struct _hw_lcd_wf17_bitfields
    {
        uint8_t BPALCD17 : 1;          /*!< [0]  */
        uint8_t BPBLCD17 : 1;          /*!< [1]  */
        uint8_t BPCLCD17 : 1;          /*!< [2]  */
        uint8_t BPDLCD17 : 1;          /*!< [3]  */
        uint8_t BPELCD17 : 1;          /*!< [4]  */
        uint8_t BPFLCD17 : 1;          /*!< [5]  */
        uint8_t BPGLCD17 : 1;          /*!< [6]  */
        uint8_t BPHLCD17 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf17_t;

/*!
 * @name Constants and macros for entire LCD_WF17 register
 */
/*@{*/
#define HW_LCD_WF17_ADDR(x)      ((x) + 0x31U)

#define HW_LCD_WF17(x)           (*(__IO hw_lcd_wf17_t *) HW_LCD_WF17_ADDR(x))
#define HW_LCD_WF17_RD(x)        (HW_LCD_WF17(x).U)
#define HW_LCD_WF17_WR(x, v)     (HW_LCD_WF17(x).U = (v))
#define HW_LCD_WF17_SET(x, v)    (BME_OR8(HW_LCD_WF17_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF17_CLR(x, v)    (BME_AND8(HW_LCD_WF17_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF17_TOG(x, v)    (BME_XOR8(HW_LCD_WF17_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF17 bitfields
 */

/*!
 * @name Register LCD_WF17, field BPALCD17[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF17_BPALCD17 (0U)          /*!< Bit position for LCD_WF17_BPALCD17. */
#define BM_LCD_WF17_BPALCD17 (0x01U)       /*!< Bit mask for LCD_WF17_BPALCD17. */
#define BS_LCD_WF17_BPALCD17 (1U)          /*!< Bit field size in bits for LCD_WF17_BPALCD17. */

/*! @brief Read current value of the LCD_WF17_BPALCD17 field. */
#define BR_LCD_WF17_BPALCD17(x) (BME_UBFX8(HW_LCD_WF17_ADDR(x), BP_LCD_WF17_BPALCD17, BS_LCD_WF17_BPALCD17))

/*! @brief Format value for bitfield LCD_WF17_BPALCD17. */
#define BF_LCD_WF17_BPALCD17(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF17_BPALCD17) & BM_LCD_WF17_BPALCD17)

/*! @brief Set the BPALCD17 field to a new value. */
#define BW_LCD_WF17_BPALCD17(x, v) (BME_BFI8(HW_LCD_WF17_ADDR(x), ((uint8_t)(v) << BP_LCD_WF17_BPALCD17), BP_LCD_WF17_BPALCD17, 1))
/*@}*/

/*!
 * @name Register LCD_WF17, field BPBLCD17[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF17_BPBLCD17 (1U)          /*!< Bit position for LCD_WF17_BPBLCD17. */
#define BM_LCD_WF17_BPBLCD17 (0x02U)       /*!< Bit mask for LCD_WF17_BPBLCD17. */
#define BS_LCD_WF17_BPBLCD17 (1U)          /*!< Bit field size in bits for LCD_WF17_BPBLCD17. */

/*! @brief Read current value of the LCD_WF17_BPBLCD17 field. */
#define BR_LCD_WF17_BPBLCD17(x) (BME_UBFX8(HW_LCD_WF17_ADDR(x), BP_LCD_WF17_BPBLCD17, BS_LCD_WF17_BPBLCD17))

/*! @brief Format value for bitfield LCD_WF17_BPBLCD17. */
#define BF_LCD_WF17_BPBLCD17(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF17_BPBLCD17) & BM_LCD_WF17_BPBLCD17)

/*! @brief Set the BPBLCD17 field to a new value. */
#define BW_LCD_WF17_BPBLCD17(x, v) (BME_BFI8(HW_LCD_WF17_ADDR(x), ((uint8_t)(v) << BP_LCD_WF17_BPBLCD17), BP_LCD_WF17_BPBLCD17, 1))
/*@}*/

/*!
 * @name Register LCD_WF17, field BPCLCD17[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF17_BPCLCD17 (2U)          /*!< Bit position for LCD_WF17_BPCLCD17. */
#define BM_LCD_WF17_BPCLCD17 (0x04U)       /*!< Bit mask for LCD_WF17_BPCLCD17. */
#define BS_LCD_WF17_BPCLCD17 (1U)          /*!< Bit field size in bits for LCD_WF17_BPCLCD17. */

/*! @brief Read current value of the LCD_WF17_BPCLCD17 field. */
#define BR_LCD_WF17_BPCLCD17(x) (BME_UBFX8(HW_LCD_WF17_ADDR(x), BP_LCD_WF17_BPCLCD17, BS_LCD_WF17_BPCLCD17))

/*! @brief Format value for bitfield LCD_WF17_BPCLCD17. */
#define BF_LCD_WF17_BPCLCD17(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF17_BPCLCD17) & BM_LCD_WF17_BPCLCD17)

/*! @brief Set the BPCLCD17 field to a new value. */
#define BW_LCD_WF17_BPCLCD17(x, v) (BME_BFI8(HW_LCD_WF17_ADDR(x), ((uint8_t)(v) << BP_LCD_WF17_BPCLCD17), BP_LCD_WF17_BPCLCD17, 1))
/*@}*/

/*!
 * @name Register LCD_WF17, field BPDLCD17[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF17_BPDLCD17 (3U)          /*!< Bit position for LCD_WF17_BPDLCD17. */
#define BM_LCD_WF17_BPDLCD17 (0x08U)       /*!< Bit mask for LCD_WF17_BPDLCD17. */
#define BS_LCD_WF17_BPDLCD17 (1U)          /*!< Bit field size in bits for LCD_WF17_BPDLCD17. */

/*! @brief Read current value of the LCD_WF17_BPDLCD17 field. */
#define BR_LCD_WF17_BPDLCD17(x) (BME_UBFX8(HW_LCD_WF17_ADDR(x), BP_LCD_WF17_BPDLCD17, BS_LCD_WF17_BPDLCD17))

/*! @brief Format value for bitfield LCD_WF17_BPDLCD17. */
#define BF_LCD_WF17_BPDLCD17(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF17_BPDLCD17) & BM_LCD_WF17_BPDLCD17)

/*! @brief Set the BPDLCD17 field to a new value. */
#define BW_LCD_WF17_BPDLCD17(x, v) (BME_BFI8(HW_LCD_WF17_ADDR(x), ((uint8_t)(v) << BP_LCD_WF17_BPDLCD17), BP_LCD_WF17_BPDLCD17, 1))
/*@}*/

/*!
 * @name Register LCD_WF17, field BPELCD17[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF17_BPELCD17 (4U)          /*!< Bit position for LCD_WF17_BPELCD17. */
#define BM_LCD_WF17_BPELCD17 (0x10U)       /*!< Bit mask for LCD_WF17_BPELCD17. */
#define BS_LCD_WF17_BPELCD17 (1U)          /*!< Bit field size in bits for LCD_WF17_BPELCD17. */

/*! @brief Read current value of the LCD_WF17_BPELCD17 field. */
#define BR_LCD_WF17_BPELCD17(x) (BME_UBFX8(HW_LCD_WF17_ADDR(x), BP_LCD_WF17_BPELCD17, BS_LCD_WF17_BPELCD17))

/*! @brief Format value for bitfield LCD_WF17_BPELCD17. */
#define BF_LCD_WF17_BPELCD17(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF17_BPELCD17) & BM_LCD_WF17_BPELCD17)

/*! @brief Set the BPELCD17 field to a new value. */
#define BW_LCD_WF17_BPELCD17(x, v) (BME_BFI8(HW_LCD_WF17_ADDR(x), ((uint8_t)(v) << BP_LCD_WF17_BPELCD17), BP_LCD_WF17_BPELCD17, 1))
/*@}*/

/*!
 * @name Register LCD_WF17, field BPFLCD17[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF17_BPFLCD17 (5U)          /*!< Bit position for LCD_WF17_BPFLCD17. */
#define BM_LCD_WF17_BPFLCD17 (0x20U)       /*!< Bit mask for LCD_WF17_BPFLCD17. */
#define BS_LCD_WF17_BPFLCD17 (1U)          /*!< Bit field size in bits for LCD_WF17_BPFLCD17. */

/*! @brief Read current value of the LCD_WF17_BPFLCD17 field. */
#define BR_LCD_WF17_BPFLCD17(x) (BME_UBFX8(HW_LCD_WF17_ADDR(x), BP_LCD_WF17_BPFLCD17, BS_LCD_WF17_BPFLCD17))

/*! @brief Format value for bitfield LCD_WF17_BPFLCD17. */
#define BF_LCD_WF17_BPFLCD17(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF17_BPFLCD17) & BM_LCD_WF17_BPFLCD17)

/*! @brief Set the BPFLCD17 field to a new value. */
#define BW_LCD_WF17_BPFLCD17(x, v) (BME_BFI8(HW_LCD_WF17_ADDR(x), ((uint8_t)(v) << BP_LCD_WF17_BPFLCD17), BP_LCD_WF17_BPFLCD17, 1))
/*@}*/

/*!
 * @name Register LCD_WF17, field BPGLCD17[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF17_BPGLCD17 (6U)          /*!< Bit position for LCD_WF17_BPGLCD17. */
#define BM_LCD_WF17_BPGLCD17 (0x40U)       /*!< Bit mask for LCD_WF17_BPGLCD17. */
#define BS_LCD_WF17_BPGLCD17 (1U)          /*!< Bit field size in bits for LCD_WF17_BPGLCD17. */

/*! @brief Read current value of the LCD_WF17_BPGLCD17 field. */
#define BR_LCD_WF17_BPGLCD17(x) (BME_UBFX8(HW_LCD_WF17_ADDR(x), BP_LCD_WF17_BPGLCD17, BS_LCD_WF17_BPGLCD17))

/*! @brief Format value for bitfield LCD_WF17_BPGLCD17. */
#define BF_LCD_WF17_BPGLCD17(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF17_BPGLCD17) & BM_LCD_WF17_BPGLCD17)

/*! @brief Set the BPGLCD17 field to a new value. */
#define BW_LCD_WF17_BPGLCD17(x, v) (BME_BFI8(HW_LCD_WF17_ADDR(x), ((uint8_t)(v) << BP_LCD_WF17_BPGLCD17), BP_LCD_WF17_BPGLCD17, 1))
/*@}*/

/*!
 * @name Register LCD_WF17, field BPHLCD17[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF17_BPHLCD17 (7U)          /*!< Bit position for LCD_WF17_BPHLCD17. */
#define BM_LCD_WF17_BPHLCD17 (0x80U)       /*!< Bit mask for LCD_WF17_BPHLCD17. */
#define BS_LCD_WF17_BPHLCD17 (1U)          /*!< Bit field size in bits for LCD_WF17_BPHLCD17. */

/*! @brief Read current value of the LCD_WF17_BPHLCD17 field. */
#define BR_LCD_WF17_BPHLCD17(x) (BME_UBFX8(HW_LCD_WF17_ADDR(x), BP_LCD_WF17_BPHLCD17, BS_LCD_WF17_BPHLCD17))

/*! @brief Format value for bitfield LCD_WF17_BPHLCD17. */
#define BF_LCD_WF17_BPHLCD17(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF17_BPHLCD17) & BM_LCD_WF17_BPHLCD17)

/*! @brief Set the BPHLCD17 field to a new value. */
#define BW_LCD_WF17_BPHLCD17(x, v) (BME_BFI8(HW_LCD_WF17_ADDR(x), ((uint8_t)(v) << BP_LCD_WF17_BPHLCD17), BP_LCD_WF17_BPHLCD17, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF18 - LCD Waveform Register 18.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF18 - LCD Waveform Register 18. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf18
{
    uint8_t U;
    struct _hw_lcd_wf18_bitfields
    {
        uint8_t BPALCD18 : 1;          /*!< [0]  */
        uint8_t BPBLCD18 : 1;          /*!< [1]  */
        uint8_t BPCLCD18 : 1;          /*!< [2]  */
        uint8_t BPDLCD18 : 1;          /*!< [3]  */
        uint8_t BPELCD18 : 1;          /*!< [4]  */
        uint8_t BPFLCD18 : 1;          /*!< [5]  */
        uint8_t BPGLCD18 : 1;          /*!< [6]  */
        uint8_t BPHLCD18 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf18_t;

/*!
 * @name Constants and macros for entire LCD_WF18 register
 */
/*@{*/
#define HW_LCD_WF18_ADDR(x)      ((x) + 0x32U)

#define HW_LCD_WF18(x)           (*(__IO hw_lcd_wf18_t *) HW_LCD_WF18_ADDR(x))
#define HW_LCD_WF18_RD(x)        (HW_LCD_WF18(x).U)
#define HW_LCD_WF18_WR(x, v)     (HW_LCD_WF18(x).U = (v))
#define HW_LCD_WF18_SET(x, v)    (BME_OR8(HW_LCD_WF18_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF18_CLR(x, v)    (BME_AND8(HW_LCD_WF18_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF18_TOG(x, v)    (BME_XOR8(HW_LCD_WF18_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF18 bitfields
 */

/*!
 * @name Register LCD_WF18, field BPALCD18[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF18_BPALCD18 (0U)          /*!< Bit position for LCD_WF18_BPALCD18. */
#define BM_LCD_WF18_BPALCD18 (0x01U)       /*!< Bit mask for LCD_WF18_BPALCD18. */
#define BS_LCD_WF18_BPALCD18 (1U)          /*!< Bit field size in bits for LCD_WF18_BPALCD18. */

/*! @brief Read current value of the LCD_WF18_BPALCD18 field. */
#define BR_LCD_WF18_BPALCD18(x) (BME_UBFX8(HW_LCD_WF18_ADDR(x), BP_LCD_WF18_BPALCD18, BS_LCD_WF18_BPALCD18))

/*! @brief Format value for bitfield LCD_WF18_BPALCD18. */
#define BF_LCD_WF18_BPALCD18(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF18_BPALCD18) & BM_LCD_WF18_BPALCD18)

/*! @brief Set the BPALCD18 field to a new value. */
#define BW_LCD_WF18_BPALCD18(x, v) (BME_BFI8(HW_LCD_WF18_ADDR(x), ((uint8_t)(v) << BP_LCD_WF18_BPALCD18), BP_LCD_WF18_BPALCD18, 1))
/*@}*/

/*!
 * @name Register LCD_WF18, field BPBLCD18[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF18_BPBLCD18 (1U)          /*!< Bit position for LCD_WF18_BPBLCD18. */
#define BM_LCD_WF18_BPBLCD18 (0x02U)       /*!< Bit mask for LCD_WF18_BPBLCD18. */
#define BS_LCD_WF18_BPBLCD18 (1U)          /*!< Bit field size in bits for LCD_WF18_BPBLCD18. */

/*! @brief Read current value of the LCD_WF18_BPBLCD18 field. */
#define BR_LCD_WF18_BPBLCD18(x) (BME_UBFX8(HW_LCD_WF18_ADDR(x), BP_LCD_WF18_BPBLCD18, BS_LCD_WF18_BPBLCD18))

/*! @brief Format value for bitfield LCD_WF18_BPBLCD18. */
#define BF_LCD_WF18_BPBLCD18(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF18_BPBLCD18) & BM_LCD_WF18_BPBLCD18)

/*! @brief Set the BPBLCD18 field to a new value. */
#define BW_LCD_WF18_BPBLCD18(x, v) (BME_BFI8(HW_LCD_WF18_ADDR(x), ((uint8_t)(v) << BP_LCD_WF18_BPBLCD18), BP_LCD_WF18_BPBLCD18, 1))
/*@}*/

/*!
 * @name Register LCD_WF18, field BPCLCD18[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF18_BPCLCD18 (2U)          /*!< Bit position for LCD_WF18_BPCLCD18. */
#define BM_LCD_WF18_BPCLCD18 (0x04U)       /*!< Bit mask for LCD_WF18_BPCLCD18. */
#define BS_LCD_WF18_BPCLCD18 (1U)          /*!< Bit field size in bits for LCD_WF18_BPCLCD18. */

/*! @brief Read current value of the LCD_WF18_BPCLCD18 field. */
#define BR_LCD_WF18_BPCLCD18(x) (BME_UBFX8(HW_LCD_WF18_ADDR(x), BP_LCD_WF18_BPCLCD18, BS_LCD_WF18_BPCLCD18))

/*! @brief Format value for bitfield LCD_WF18_BPCLCD18. */
#define BF_LCD_WF18_BPCLCD18(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF18_BPCLCD18) & BM_LCD_WF18_BPCLCD18)

/*! @brief Set the BPCLCD18 field to a new value. */
#define BW_LCD_WF18_BPCLCD18(x, v) (BME_BFI8(HW_LCD_WF18_ADDR(x), ((uint8_t)(v) << BP_LCD_WF18_BPCLCD18), BP_LCD_WF18_BPCLCD18, 1))
/*@}*/

/*!
 * @name Register LCD_WF18, field BPDLCD18[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF18_BPDLCD18 (3U)          /*!< Bit position for LCD_WF18_BPDLCD18. */
#define BM_LCD_WF18_BPDLCD18 (0x08U)       /*!< Bit mask for LCD_WF18_BPDLCD18. */
#define BS_LCD_WF18_BPDLCD18 (1U)          /*!< Bit field size in bits for LCD_WF18_BPDLCD18. */

/*! @brief Read current value of the LCD_WF18_BPDLCD18 field. */
#define BR_LCD_WF18_BPDLCD18(x) (BME_UBFX8(HW_LCD_WF18_ADDR(x), BP_LCD_WF18_BPDLCD18, BS_LCD_WF18_BPDLCD18))

/*! @brief Format value for bitfield LCD_WF18_BPDLCD18. */
#define BF_LCD_WF18_BPDLCD18(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF18_BPDLCD18) & BM_LCD_WF18_BPDLCD18)

/*! @brief Set the BPDLCD18 field to a new value. */
#define BW_LCD_WF18_BPDLCD18(x, v) (BME_BFI8(HW_LCD_WF18_ADDR(x), ((uint8_t)(v) << BP_LCD_WF18_BPDLCD18), BP_LCD_WF18_BPDLCD18, 1))
/*@}*/

/*!
 * @name Register LCD_WF18, field BPELCD18[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF18_BPELCD18 (4U)          /*!< Bit position for LCD_WF18_BPELCD18. */
#define BM_LCD_WF18_BPELCD18 (0x10U)       /*!< Bit mask for LCD_WF18_BPELCD18. */
#define BS_LCD_WF18_BPELCD18 (1U)          /*!< Bit field size in bits for LCD_WF18_BPELCD18. */

/*! @brief Read current value of the LCD_WF18_BPELCD18 field. */
#define BR_LCD_WF18_BPELCD18(x) (BME_UBFX8(HW_LCD_WF18_ADDR(x), BP_LCD_WF18_BPELCD18, BS_LCD_WF18_BPELCD18))

/*! @brief Format value for bitfield LCD_WF18_BPELCD18. */
#define BF_LCD_WF18_BPELCD18(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF18_BPELCD18) & BM_LCD_WF18_BPELCD18)

/*! @brief Set the BPELCD18 field to a new value. */
#define BW_LCD_WF18_BPELCD18(x, v) (BME_BFI8(HW_LCD_WF18_ADDR(x), ((uint8_t)(v) << BP_LCD_WF18_BPELCD18), BP_LCD_WF18_BPELCD18, 1))
/*@}*/

/*!
 * @name Register LCD_WF18, field BPFLCD18[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF18_BPFLCD18 (5U)          /*!< Bit position for LCD_WF18_BPFLCD18. */
#define BM_LCD_WF18_BPFLCD18 (0x20U)       /*!< Bit mask for LCD_WF18_BPFLCD18. */
#define BS_LCD_WF18_BPFLCD18 (1U)          /*!< Bit field size in bits for LCD_WF18_BPFLCD18. */

/*! @brief Read current value of the LCD_WF18_BPFLCD18 field. */
#define BR_LCD_WF18_BPFLCD18(x) (BME_UBFX8(HW_LCD_WF18_ADDR(x), BP_LCD_WF18_BPFLCD18, BS_LCD_WF18_BPFLCD18))

/*! @brief Format value for bitfield LCD_WF18_BPFLCD18. */
#define BF_LCD_WF18_BPFLCD18(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF18_BPFLCD18) & BM_LCD_WF18_BPFLCD18)

/*! @brief Set the BPFLCD18 field to a new value. */
#define BW_LCD_WF18_BPFLCD18(x, v) (BME_BFI8(HW_LCD_WF18_ADDR(x), ((uint8_t)(v) << BP_LCD_WF18_BPFLCD18), BP_LCD_WF18_BPFLCD18, 1))
/*@}*/

/*!
 * @name Register LCD_WF18, field BPGLCD18[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF18_BPGLCD18 (6U)          /*!< Bit position for LCD_WF18_BPGLCD18. */
#define BM_LCD_WF18_BPGLCD18 (0x40U)       /*!< Bit mask for LCD_WF18_BPGLCD18. */
#define BS_LCD_WF18_BPGLCD18 (1U)          /*!< Bit field size in bits for LCD_WF18_BPGLCD18. */

/*! @brief Read current value of the LCD_WF18_BPGLCD18 field. */
#define BR_LCD_WF18_BPGLCD18(x) (BME_UBFX8(HW_LCD_WF18_ADDR(x), BP_LCD_WF18_BPGLCD18, BS_LCD_WF18_BPGLCD18))

/*! @brief Format value for bitfield LCD_WF18_BPGLCD18. */
#define BF_LCD_WF18_BPGLCD18(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF18_BPGLCD18) & BM_LCD_WF18_BPGLCD18)

/*! @brief Set the BPGLCD18 field to a new value. */
#define BW_LCD_WF18_BPGLCD18(x, v) (BME_BFI8(HW_LCD_WF18_ADDR(x), ((uint8_t)(v) << BP_LCD_WF18_BPGLCD18), BP_LCD_WF18_BPGLCD18, 1))
/*@}*/

/*!
 * @name Register LCD_WF18, field BPHLCD18[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF18_BPHLCD18 (7U)          /*!< Bit position for LCD_WF18_BPHLCD18. */
#define BM_LCD_WF18_BPHLCD18 (0x80U)       /*!< Bit mask for LCD_WF18_BPHLCD18. */
#define BS_LCD_WF18_BPHLCD18 (1U)          /*!< Bit field size in bits for LCD_WF18_BPHLCD18. */

/*! @brief Read current value of the LCD_WF18_BPHLCD18 field. */
#define BR_LCD_WF18_BPHLCD18(x) (BME_UBFX8(HW_LCD_WF18_ADDR(x), BP_LCD_WF18_BPHLCD18, BS_LCD_WF18_BPHLCD18))

/*! @brief Format value for bitfield LCD_WF18_BPHLCD18. */
#define BF_LCD_WF18_BPHLCD18(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF18_BPHLCD18) & BM_LCD_WF18_BPHLCD18)

/*! @brief Set the BPHLCD18 field to a new value. */
#define BW_LCD_WF18_BPHLCD18(x, v) (BME_BFI8(HW_LCD_WF18_ADDR(x), ((uint8_t)(v) << BP_LCD_WF18_BPHLCD18), BP_LCD_WF18_BPHLCD18, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF19 - LCD Waveform Register 19.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF19 - LCD Waveform Register 19. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf19
{
    uint8_t U;
    struct _hw_lcd_wf19_bitfields
    {
        uint8_t BPALCD19 : 1;          /*!< [0]  */
        uint8_t BPBLCD19 : 1;          /*!< [1]  */
        uint8_t BPCLCD19 : 1;          /*!< [2]  */
        uint8_t BPDLCD19 : 1;          /*!< [3]  */
        uint8_t BPELCD19 : 1;          /*!< [4]  */
        uint8_t BPFLCD19 : 1;          /*!< [5]  */
        uint8_t BPGLCD19 : 1;          /*!< [6]  */
        uint8_t BPHLCD19 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf19_t;

/*!
 * @name Constants and macros for entire LCD_WF19 register
 */
/*@{*/
#define HW_LCD_WF19_ADDR(x)      ((x) + 0x33U)

#define HW_LCD_WF19(x)           (*(__IO hw_lcd_wf19_t *) HW_LCD_WF19_ADDR(x))
#define HW_LCD_WF19_RD(x)        (HW_LCD_WF19(x).U)
#define HW_LCD_WF19_WR(x, v)     (HW_LCD_WF19(x).U = (v))
#define HW_LCD_WF19_SET(x, v)    (BME_OR8(HW_LCD_WF19_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF19_CLR(x, v)    (BME_AND8(HW_LCD_WF19_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF19_TOG(x, v)    (BME_XOR8(HW_LCD_WF19_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF19 bitfields
 */

/*!
 * @name Register LCD_WF19, field BPALCD19[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF19_BPALCD19 (0U)          /*!< Bit position for LCD_WF19_BPALCD19. */
#define BM_LCD_WF19_BPALCD19 (0x01U)       /*!< Bit mask for LCD_WF19_BPALCD19. */
#define BS_LCD_WF19_BPALCD19 (1U)          /*!< Bit field size in bits for LCD_WF19_BPALCD19. */

/*! @brief Read current value of the LCD_WF19_BPALCD19 field. */
#define BR_LCD_WF19_BPALCD19(x) (BME_UBFX8(HW_LCD_WF19_ADDR(x), BP_LCD_WF19_BPALCD19, BS_LCD_WF19_BPALCD19))

/*! @brief Format value for bitfield LCD_WF19_BPALCD19. */
#define BF_LCD_WF19_BPALCD19(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF19_BPALCD19) & BM_LCD_WF19_BPALCD19)

/*! @brief Set the BPALCD19 field to a new value. */
#define BW_LCD_WF19_BPALCD19(x, v) (BME_BFI8(HW_LCD_WF19_ADDR(x), ((uint8_t)(v) << BP_LCD_WF19_BPALCD19), BP_LCD_WF19_BPALCD19, 1))
/*@}*/

/*!
 * @name Register LCD_WF19, field BPBLCD19[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF19_BPBLCD19 (1U)          /*!< Bit position for LCD_WF19_BPBLCD19. */
#define BM_LCD_WF19_BPBLCD19 (0x02U)       /*!< Bit mask for LCD_WF19_BPBLCD19. */
#define BS_LCD_WF19_BPBLCD19 (1U)          /*!< Bit field size in bits for LCD_WF19_BPBLCD19. */

/*! @brief Read current value of the LCD_WF19_BPBLCD19 field. */
#define BR_LCD_WF19_BPBLCD19(x) (BME_UBFX8(HW_LCD_WF19_ADDR(x), BP_LCD_WF19_BPBLCD19, BS_LCD_WF19_BPBLCD19))

/*! @brief Format value for bitfield LCD_WF19_BPBLCD19. */
#define BF_LCD_WF19_BPBLCD19(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF19_BPBLCD19) & BM_LCD_WF19_BPBLCD19)

/*! @brief Set the BPBLCD19 field to a new value. */
#define BW_LCD_WF19_BPBLCD19(x, v) (BME_BFI8(HW_LCD_WF19_ADDR(x), ((uint8_t)(v) << BP_LCD_WF19_BPBLCD19), BP_LCD_WF19_BPBLCD19, 1))
/*@}*/

/*!
 * @name Register LCD_WF19, field BPCLCD19[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF19_BPCLCD19 (2U)          /*!< Bit position for LCD_WF19_BPCLCD19. */
#define BM_LCD_WF19_BPCLCD19 (0x04U)       /*!< Bit mask for LCD_WF19_BPCLCD19. */
#define BS_LCD_WF19_BPCLCD19 (1U)          /*!< Bit field size in bits for LCD_WF19_BPCLCD19. */

/*! @brief Read current value of the LCD_WF19_BPCLCD19 field. */
#define BR_LCD_WF19_BPCLCD19(x) (BME_UBFX8(HW_LCD_WF19_ADDR(x), BP_LCD_WF19_BPCLCD19, BS_LCD_WF19_BPCLCD19))

/*! @brief Format value for bitfield LCD_WF19_BPCLCD19. */
#define BF_LCD_WF19_BPCLCD19(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF19_BPCLCD19) & BM_LCD_WF19_BPCLCD19)

/*! @brief Set the BPCLCD19 field to a new value. */
#define BW_LCD_WF19_BPCLCD19(x, v) (BME_BFI8(HW_LCD_WF19_ADDR(x), ((uint8_t)(v) << BP_LCD_WF19_BPCLCD19), BP_LCD_WF19_BPCLCD19, 1))
/*@}*/

/*!
 * @name Register LCD_WF19, field BPDLCD19[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF19_BPDLCD19 (3U)          /*!< Bit position for LCD_WF19_BPDLCD19. */
#define BM_LCD_WF19_BPDLCD19 (0x08U)       /*!< Bit mask for LCD_WF19_BPDLCD19. */
#define BS_LCD_WF19_BPDLCD19 (1U)          /*!< Bit field size in bits for LCD_WF19_BPDLCD19. */

/*! @brief Read current value of the LCD_WF19_BPDLCD19 field. */
#define BR_LCD_WF19_BPDLCD19(x) (BME_UBFX8(HW_LCD_WF19_ADDR(x), BP_LCD_WF19_BPDLCD19, BS_LCD_WF19_BPDLCD19))

/*! @brief Format value for bitfield LCD_WF19_BPDLCD19. */
#define BF_LCD_WF19_BPDLCD19(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF19_BPDLCD19) & BM_LCD_WF19_BPDLCD19)

/*! @brief Set the BPDLCD19 field to a new value. */
#define BW_LCD_WF19_BPDLCD19(x, v) (BME_BFI8(HW_LCD_WF19_ADDR(x), ((uint8_t)(v) << BP_LCD_WF19_BPDLCD19), BP_LCD_WF19_BPDLCD19, 1))
/*@}*/

/*!
 * @name Register LCD_WF19, field BPELCD19[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF19_BPELCD19 (4U)          /*!< Bit position for LCD_WF19_BPELCD19. */
#define BM_LCD_WF19_BPELCD19 (0x10U)       /*!< Bit mask for LCD_WF19_BPELCD19. */
#define BS_LCD_WF19_BPELCD19 (1U)          /*!< Bit field size in bits for LCD_WF19_BPELCD19. */

/*! @brief Read current value of the LCD_WF19_BPELCD19 field. */
#define BR_LCD_WF19_BPELCD19(x) (BME_UBFX8(HW_LCD_WF19_ADDR(x), BP_LCD_WF19_BPELCD19, BS_LCD_WF19_BPELCD19))

/*! @brief Format value for bitfield LCD_WF19_BPELCD19. */
#define BF_LCD_WF19_BPELCD19(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF19_BPELCD19) & BM_LCD_WF19_BPELCD19)

/*! @brief Set the BPELCD19 field to a new value. */
#define BW_LCD_WF19_BPELCD19(x, v) (BME_BFI8(HW_LCD_WF19_ADDR(x), ((uint8_t)(v) << BP_LCD_WF19_BPELCD19), BP_LCD_WF19_BPELCD19, 1))
/*@}*/

/*!
 * @name Register LCD_WF19, field BPFLCD19[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF19_BPFLCD19 (5U)          /*!< Bit position for LCD_WF19_BPFLCD19. */
#define BM_LCD_WF19_BPFLCD19 (0x20U)       /*!< Bit mask for LCD_WF19_BPFLCD19. */
#define BS_LCD_WF19_BPFLCD19 (1U)          /*!< Bit field size in bits for LCD_WF19_BPFLCD19. */

/*! @brief Read current value of the LCD_WF19_BPFLCD19 field. */
#define BR_LCD_WF19_BPFLCD19(x) (BME_UBFX8(HW_LCD_WF19_ADDR(x), BP_LCD_WF19_BPFLCD19, BS_LCD_WF19_BPFLCD19))

/*! @brief Format value for bitfield LCD_WF19_BPFLCD19. */
#define BF_LCD_WF19_BPFLCD19(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF19_BPFLCD19) & BM_LCD_WF19_BPFLCD19)

/*! @brief Set the BPFLCD19 field to a new value. */
#define BW_LCD_WF19_BPFLCD19(x, v) (BME_BFI8(HW_LCD_WF19_ADDR(x), ((uint8_t)(v) << BP_LCD_WF19_BPFLCD19), BP_LCD_WF19_BPFLCD19, 1))
/*@}*/

/*!
 * @name Register LCD_WF19, field BPGLCD19[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF19_BPGLCD19 (6U)          /*!< Bit position for LCD_WF19_BPGLCD19. */
#define BM_LCD_WF19_BPGLCD19 (0x40U)       /*!< Bit mask for LCD_WF19_BPGLCD19. */
#define BS_LCD_WF19_BPGLCD19 (1U)          /*!< Bit field size in bits for LCD_WF19_BPGLCD19. */

/*! @brief Read current value of the LCD_WF19_BPGLCD19 field. */
#define BR_LCD_WF19_BPGLCD19(x) (BME_UBFX8(HW_LCD_WF19_ADDR(x), BP_LCD_WF19_BPGLCD19, BS_LCD_WF19_BPGLCD19))

/*! @brief Format value for bitfield LCD_WF19_BPGLCD19. */
#define BF_LCD_WF19_BPGLCD19(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF19_BPGLCD19) & BM_LCD_WF19_BPGLCD19)

/*! @brief Set the BPGLCD19 field to a new value. */
#define BW_LCD_WF19_BPGLCD19(x, v) (BME_BFI8(HW_LCD_WF19_ADDR(x), ((uint8_t)(v) << BP_LCD_WF19_BPGLCD19), BP_LCD_WF19_BPGLCD19, 1))
/*@}*/

/*!
 * @name Register LCD_WF19, field BPHLCD19[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF19_BPHLCD19 (7U)          /*!< Bit position for LCD_WF19_BPHLCD19. */
#define BM_LCD_WF19_BPHLCD19 (0x80U)       /*!< Bit mask for LCD_WF19_BPHLCD19. */
#define BS_LCD_WF19_BPHLCD19 (1U)          /*!< Bit field size in bits for LCD_WF19_BPHLCD19. */

/*! @brief Read current value of the LCD_WF19_BPHLCD19 field. */
#define BR_LCD_WF19_BPHLCD19(x) (BME_UBFX8(HW_LCD_WF19_ADDR(x), BP_LCD_WF19_BPHLCD19, BS_LCD_WF19_BPHLCD19))

/*! @brief Format value for bitfield LCD_WF19_BPHLCD19. */
#define BF_LCD_WF19_BPHLCD19(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF19_BPHLCD19) & BM_LCD_WF19_BPHLCD19)

/*! @brief Set the BPHLCD19 field to a new value. */
#define BW_LCD_WF19_BPHLCD19(x, v) (BME_BFI8(HW_LCD_WF19_ADDR(x), ((uint8_t)(v) << BP_LCD_WF19_BPHLCD19), BP_LCD_WF19_BPHLCD19, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF20 - LCD Waveform Register 20.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF20 - LCD Waveform Register 20. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf20
{
    uint8_t U;
    struct _hw_lcd_wf20_bitfields
    {
        uint8_t BPALCD20 : 1;          /*!< [0]  */
        uint8_t BPBLCD20 : 1;          /*!< [1]  */
        uint8_t BPCLCD20 : 1;          /*!< [2]  */
        uint8_t BPDLCD20 : 1;          /*!< [3]  */
        uint8_t BPELCD20 : 1;          /*!< [4]  */
        uint8_t BPFLCD20 : 1;          /*!< [5]  */
        uint8_t BPGLCD20 : 1;          /*!< [6]  */
        uint8_t BPHLCD20 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf20_t;

/*!
 * @name Constants and macros for entire LCD_WF20 register
 */
/*@{*/
#define HW_LCD_WF20_ADDR(x)      ((x) + 0x34U)

#define HW_LCD_WF20(x)           (*(__IO hw_lcd_wf20_t *) HW_LCD_WF20_ADDR(x))
#define HW_LCD_WF20_RD(x)        (HW_LCD_WF20(x).U)
#define HW_LCD_WF20_WR(x, v)     (HW_LCD_WF20(x).U = (v))
#define HW_LCD_WF20_SET(x, v)    (BME_OR8(HW_LCD_WF20_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF20_CLR(x, v)    (BME_AND8(HW_LCD_WF20_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF20_TOG(x, v)    (BME_XOR8(HW_LCD_WF20_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF20 bitfields
 */

/*!
 * @name Register LCD_WF20, field BPALCD20[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF20_BPALCD20 (0U)          /*!< Bit position for LCD_WF20_BPALCD20. */
#define BM_LCD_WF20_BPALCD20 (0x01U)       /*!< Bit mask for LCD_WF20_BPALCD20. */
#define BS_LCD_WF20_BPALCD20 (1U)          /*!< Bit field size in bits for LCD_WF20_BPALCD20. */

/*! @brief Read current value of the LCD_WF20_BPALCD20 field. */
#define BR_LCD_WF20_BPALCD20(x) (BME_UBFX8(HW_LCD_WF20_ADDR(x), BP_LCD_WF20_BPALCD20, BS_LCD_WF20_BPALCD20))

/*! @brief Format value for bitfield LCD_WF20_BPALCD20. */
#define BF_LCD_WF20_BPALCD20(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF20_BPALCD20) & BM_LCD_WF20_BPALCD20)

/*! @brief Set the BPALCD20 field to a new value. */
#define BW_LCD_WF20_BPALCD20(x, v) (BME_BFI8(HW_LCD_WF20_ADDR(x), ((uint8_t)(v) << BP_LCD_WF20_BPALCD20), BP_LCD_WF20_BPALCD20, 1))
/*@}*/

/*!
 * @name Register LCD_WF20, field BPBLCD20[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF20_BPBLCD20 (1U)          /*!< Bit position for LCD_WF20_BPBLCD20. */
#define BM_LCD_WF20_BPBLCD20 (0x02U)       /*!< Bit mask for LCD_WF20_BPBLCD20. */
#define BS_LCD_WF20_BPBLCD20 (1U)          /*!< Bit field size in bits for LCD_WF20_BPBLCD20. */

/*! @brief Read current value of the LCD_WF20_BPBLCD20 field. */
#define BR_LCD_WF20_BPBLCD20(x) (BME_UBFX8(HW_LCD_WF20_ADDR(x), BP_LCD_WF20_BPBLCD20, BS_LCD_WF20_BPBLCD20))

/*! @brief Format value for bitfield LCD_WF20_BPBLCD20. */
#define BF_LCD_WF20_BPBLCD20(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF20_BPBLCD20) & BM_LCD_WF20_BPBLCD20)

/*! @brief Set the BPBLCD20 field to a new value. */
#define BW_LCD_WF20_BPBLCD20(x, v) (BME_BFI8(HW_LCD_WF20_ADDR(x), ((uint8_t)(v) << BP_LCD_WF20_BPBLCD20), BP_LCD_WF20_BPBLCD20, 1))
/*@}*/

/*!
 * @name Register LCD_WF20, field BPCLCD20[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF20_BPCLCD20 (2U)          /*!< Bit position for LCD_WF20_BPCLCD20. */
#define BM_LCD_WF20_BPCLCD20 (0x04U)       /*!< Bit mask for LCD_WF20_BPCLCD20. */
#define BS_LCD_WF20_BPCLCD20 (1U)          /*!< Bit field size in bits for LCD_WF20_BPCLCD20. */

/*! @brief Read current value of the LCD_WF20_BPCLCD20 field. */
#define BR_LCD_WF20_BPCLCD20(x) (BME_UBFX8(HW_LCD_WF20_ADDR(x), BP_LCD_WF20_BPCLCD20, BS_LCD_WF20_BPCLCD20))

/*! @brief Format value for bitfield LCD_WF20_BPCLCD20. */
#define BF_LCD_WF20_BPCLCD20(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF20_BPCLCD20) & BM_LCD_WF20_BPCLCD20)

/*! @brief Set the BPCLCD20 field to a new value. */
#define BW_LCD_WF20_BPCLCD20(x, v) (BME_BFI8(HW_LCD_WF20_ADDR(x), ((uint8_t)(v) << BP_LCD_WF20_BPCLCD20), BP_LCD_WF20_BPCLCD20, 1))
/*@}*/

/*!
 * @name Register LCD_WF20, field BPDLCD20[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF20_BPDLCD20 (3U)          /*!< Bit position for LCD_WF20_BPDLCD20. */
#define BM_LCD_WF20_BPDLCD20 (0x08U)       /*!< Bit mask for LCD_WF20_BPDLCD20. */
#define BS_LCD_WF20_BPDLCD20 (1U)          /*!< Bit field size in bits for LCD_WF20_BPDLCD20. */

/*! @brief Read current value of the LCD_WF20_BPDLCD20 field. */
#define BR_LCD_WF20_BPDLCD20(x) (BME_UBFX8(HW_LCD_WF20_ADDR(x), BP_LCD_WF20_BPDLCD20, BS_LCD_WF20_BPDLCD20))

/*! @brief Format value for bitfield LCD_WF20_BPDLCD20. */
#define BF_LCD_WF20_BPDLCD20(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF20_BPDLCD20) & BM_LCD_WF20_BPDLCD20)

/*! @brief Set the BPDLCD20 field to a new value. */
#define BW_LCD_WF20_BPDLCD20(x, v) (BME_BFI8(HW_LCD_WF20_ADDR(x), ((uint8_t)(v) << BP_LCD_WF20_BPDLCD20), BP_LCD_WF20_BPDLCD20, 1))
/*@}*/

/*!
 * @name Register LCD_WF20, field BPELCD20[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF20_BPELCD20 (4U)          /*!< Bit position for LCD_WF20_BPELCD20. */
#define BM_LCD_WF20_BPELCD20 (0x10U)       /*!< Bit mask for LCD_WF20_BPELCD20. */
#define BS_LCD_WF20_BPELCD20 (1U)          /*!< Bit field size in bits for LCD_WF20_BPELCD20. */

/*! @brief Read current value of the LCD_WF20_BPELCD20 field. */
#define BR_LCD_WF20_BPELCD20(x) (BME_UBFX8(HW_LCD_WF20_ADDR(x), BP_LCD_WF20_BPELCD20, BS_LCD_WF20_BPELCD20))

/*! @brief Format value for bitfield LCD_WF20_BPELCD20. */
#define BF_LCD_WF20_BPELCD20(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF20_BPELCD20) & BM_LCD_WF20_BPELCD20)

/*! @brief Set the BPELCD20 field to a new value. */
#define BW_LCD_WF20_BPELCD20(x, v) (BME_BFI8(HW_LCD_WF20_ADDR(x), ((uint8_t)(v) << BP_LCD_WF20_BPELCD20), BP_LCD_WF20_BPELCD20, 1))
/*@}*/

/*!
 * @name Register LCD_WF20, field BPFLCD20[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF20_BPFLCD20 (5U)          /*!< Bit position for LCD_WF20_BPFLCD20. */
#define BM_LCD_WF20_BPFLCD20 (0x20U)       /*!< Bit mask for LCD_WF20_BPFLCD20. */
#define BS_LCD_WF20_BPFLCD20 (1U)          /*!< Bit field size in bits for LCD_WF20_BPFLCD20. */

/*! @brief Read current value of the LCD_WF20_BPFLCD20 field. */
#define BR_LCD_WF20_BPFLCD20(x) (BME_UBFX8(HW_LCD_WF20_ADDR(x), BP_LCD_WF20_BPFLCD20, BS_LCD_WF20_BPFLCD20))

/*! @brief Format value for bitfield LCD_WF20_BPFLCD20. */
#define BF_LCD_WF20_BPFLCD20(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF20_BPFLCD20) & BM_LCD_WF20_BPFLCD20)

/*! @brief Set the BPFLCD20 field to a new value. */
#define BW_LCD_WF20_BPFLCD20(x, v) (BME_BFI8(HW_LCD_WF20_ADDR(x), ((uint8_t)(v) << BP_LCD_WF20_BPFLCD20), BP_LCD_WF20_BPFLCD20, 1))
/*@}*/

/*!
 * @name Register LCD_WF20, field BPGLCD20[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF20_BPGLCD20 (6U)          /*!< Bit position for LCD_WF20_BPGLCD20. */
#define BM_LCD_WF20_BPGLCD20 (0x40U)       /*!< Bit mask for LCD_WF20_BPGLCD20. */
#define BS_LCD_WF20_BPGLCD20 (1U)          /*!< Bit field size in bits for LCD_WF20_BPGLCD20. */

/*! @brief Read current value of the LCD_WF20_BPGLCD20 field. */
#define BR_LCD_WF20_BPGLCD20(x) (BME_UBFX8(HW_LCD_WF20_ADDR(x), BP_LCD_WF20_BPGLCD20, BS_LCD_WF20_BPGLCD20))

/*! @brief Format value for bitfield LCD_WF20_BPGLCD20. */
#define BF_LCD_WF20_BPGLCD20(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF20_BPGLCD20) & BM_LCD_WF20_BPGLCD20)

/*! @brief Set the BPGLCD20 field to a new value. */
#define BW_LCD_WF20_BPGLCD20(x, v) (BME_BFI8(HW_LCD_WF20_ADDR(x), ((uint8_t)(v) << BP_LCD_WF20_BPGLCD20), BP_LCD_WF20_BPGLCD20, 1))
/*@}*/

/*!
 * @name Register LCD_WF20, field BPHLCD20[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF20_BPHLCD20 (7U)          /*!< Bit position for LCD_WF20_BPHLCD20. */
#define BM_LCD_WF20_BPHLCD20 (0x80U)       /*!< Bit mask for LCD_WF20_BPHLCD20. */
#define BS_LCD_WF20_BPHLCD20 (1U)          /*!< Bit field size in bits for LCD_WF20_BPHLCD20. */

/*! @brief Read current value of the LCD_WF20_BPHLCD20 field. */
#define BR_LCD_WF20_BPHLCD20(x) (BME_UBFX8(HW_LCD_WF20_ADDR(x), BP_LCD_WF20_BPHLCD20, BS_LCD_WF20_BPHLCD20))

/*! @brief Format value for bitfield LCD_WF20_BPHLCD20. */
#define BF_LCD_WF20_BPHLCD20(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF20_BPHLCD20) & BM_LCD_WF20_BPHLCD20)

/*! @brief Set the BPHLCD20 field to a new value. */
#define BW_LCD_WF20_BPHLCD20(x, v) (BME_BFI8(HW_LCD_WF20_ADDR(x), ((uint8_t)(v) << BP_LCD_WF20_BPHLCD20), BP_LCD_WF20_BPHLCD20, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF21 - LCD Waveform Register 21.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF21 - LCD Waveform Register 21. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf21
{
    uint8_t U;
    struct _hw_lcd_wf21_bitfields
    {
        uint8_t BPALCD21 : 1;          /*!< [0]  */
        uint8_t BPBLCD21 : 1;          /*!< [1]  */
        uint8_t BPCLCD21 : 1;          /*!< [2]  */
        uint8_t BPDLCD21 : 1;          /*!< [3]  */
        uint8_t BPELCD21 : 1;          /*!< [4]  */
        uint8_t BPFLCD21 : 1;          /*!< [5]  */
        uint8_t BPGLCD21 : 1;          /*!< [6]  */
        uint8_t BPHLCD21 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf21_t;

/*!
 * @name Constants and macros for entire LCD_WF21 register
 */
/*@{*/
#define HW_LCD_WF21_ADDR(x)      ((x) + 0x35U)

#define HW_LCD_WF21(x)           (*(__IO hw_lcd_wf21_t *) HW_LCD_WF21_ADDR(x))
#define HW_LCD_WF21_RD(x)        (HW_LCD_WF21(x).U)
#define HW_LCD_WF21_WR(x, v)     (HW_LCD_WF21(x).U = (v))
#define HW_LCD_WF21_SET(x, v)    (BME_OR8(HW_LCD_WF21_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF21_CLR(x, v)    (BME_AND8(HW_LCD_WF21_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF21_TOG(x, v)    (BME_XOR8(HW_LCD_WF21_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF21 bitfields
 */

/*!
 * @name Register LCD_WF21, field BPALCD21[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF21_BPALCD21 (0U)          /*!< Bit position for LCD_WF21_BPALCD21. */
#define BM_LCD_WF21_BPALCD21 (0x01U)       /*!< Bit mask for LCD_WF21_BPALCD21. */
#define BS_LCD_WF21_BPALCD21 (1U)          /*!< Bit field size in bits for LCD_WF21_BPALCD21. */

/*! @brief Read current value of the LCD_WF21_BPALCD21 field. */
#define BR_LCD_WF21_BPALCD21(x) (BME_UBFX8(HW_LCD_WF21_ADDR(x), BP_LCD_WF21_BPALCD21, BS_LCD_WF21_BPALCD21))

/*! @brief Format value for bitfield LCD_WF21_BPALCD21. */
#define BF_LCD_WF21_BPALCD21(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF21_BPALCD21) & BM_LCD_WF21_BPALCD21)

/*! @brief Set the BPALCD21 field to a new value. */
#define BW_LCD_WF21_BPALCD21(x, v) (BME_BFI8(HW_LCD_WF21_ADDR(x), ((uint8_t)(v) << BP_LCD_WF21_BPALCD21), BP_LCD_WF21_BPALCD21, 1))
/*@}*/

/*!
 * @name Register LCD_WF21, field BPBLCD21[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF21_BPBLCD21 (1U)          /*!< Bit position for LCD_WF21_BPBLCD21. */
#define BM_LCD_WF21_BPBLCD21 (0x02U)       /*!< Bit mask for LCD_WF21_BPBLCD21. */
#define BS_LCD_WF21_BPBLCD21 (1U)          /*!< Bit field size in bits for LCD_WF21_BPBLCD21. */

/*! @brief Read current value of the LCD_WF21_BPBLCD21 field. */
#define BR_LCD_WF21_BPBLCD21(x) (BME_UBFX8(HW_LCD_WF21_ADDR(x), BP_LCD_WF21_BPBLCD21, BS_LCD_WF21_BPBLCD21))

/*! @brief Format value for bitfield LCD_WF21_BPBLCD21. */
#define BF_LCD_WF21_BPBLCD21(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF21_BPBLCD21) & BM_LCD_WF21_BPBLCD21)

/*! @brief Set the BPBLCD21 field to a new value. */
#define BW_LCD_WF21_BPBLCD21(x, v) (BME_BFI8(HW_LCD_WF21_ADDR(x), ((uint8_t)(v) << BP_LCD_WF21_BPBLCD21), BP_LCD_WF21_BPBLCD21, 1))
/*@}*/

/*!
 * @name Register LCD_WF21, field BPCLCD21[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF21_BPCLCD21 (2U)          /*!< Bit position for LCD_WF21_BPCLCD21. */
#define BM_LCD_WF21_BPCLCD21 (0x04U)       /*!< Bit mask for LCD_WF21_BPCLCD21. */
#define BS_LCD_WF21_BPCLCD21 (1U)          /*!< Bit field size in bits for LCD_WF21_BPCLCD21. */

/*! @brief Read current value of the LCD_WF21_BPCLCD21 field. */
#define BR_LCD_WF21_BPCLCD21(x) (BME_UBFX8(HW_LCD_WF21_ADDR(x), BP_LCD_WF21_BPCLCD21, BS_LCD_WF21_BPCLCD21))

/*! @brief Format value for bitfield LCD_WF21_BPCLCD21. */
#define BF_LCD_WF21_BPCLCD21(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF21_BPCLCD21) & BM_LCD_WF21_BPCLCD21)

/*! @brief Set the BPCLCD21 field to a new value. */
#define BW_LCD_WF21_BPCLCD21(x, v) (BME_BFI8(HW_LCD_WF21_ADDR(x), ((uint8_t)(v) << BP_LCD_WF21_BPCLCD21), BP_LCD_WF21_BPCLCD21, 1))
/*@}*/

/*!
 * @name Register LCD_WF21, field BPDLCD21[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF21_BPDLCD21 (3U)          /*!< Bit position for LCD_WF21_BPDLCD21. */
#define BM_LCD_WF21_BPDLCD21 (0x08U)       /*!< Bit mask for LCD_WF21_BPDLCD21. */
#define BS_LCD_WF21_BPDLCD21 (1U)          /*!< Bit field size in bits for LCD_WF21_BPDLCD21. */

/*! @brief Read current value of the LCD_WF21_BPDLCD21 field. */
#define BR_LCD_WF21_BPDLCD21(x) (BME_UBFX8(HW_LCD_WF21_ADDR(x), BP_LCD_WF21_BPDLCD21, BS_LCD_WF21_BPDLCD21))

/*! @brief Format value for bitfield LCD_WF21_BPDLCD21. */
#define BF_LCD_WF21_BPDLCD21(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF21_BPDLCD21) & BM_LCD_WF21_BPDLCD21)

/*! @brief Set the BPDLCD21 field to a new value. */
#define BW_LCD_WF21_BPDLCD21(x, v) (BME_BFI8(HW_LCD_WF21_ADDR(x), ((uint8_t)(v) << BP_LCD_WF21_BPDLCD21), BP_LCD_WF21_BPDLCD21, 1))
/*@}*/

/*!
 * @name Register LCD_WF21, field BPELCD21[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF21_BPELCD21 (4U)          /*!< Bit position for LCD_WF21_BPELCD21. */
#define BM_LCD_WF21_BPELCD21 (0x10U)       /*!< Bit mask for LCD_WF21_BPELCD21. */
#define BS_LCD_WF21_BPELCD21 (1U)          /*!< Bit field size in bits for LCD_WF21_BPELCD21. */

/*! @brief Read current value of the LCD_WF21_BPELCD21 field. */
#define BR_LCD_WF21_BPELCD21(x) (BME_UBFX8(HW_LCD_WF21_ADDR(x), BP_LCD_WF21_BPELCD21, BS_LCD_WF21_BPELCD21))

/*! @brief Format value for bitfield LCD_WF21_BPELCD21. */
#define BF_LCD_WF21_BPELCD21(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF21_BPELCD21) & BM_LCD_WF21_BPELCD21)

/*! @brief Set the BPELCD21 field to a new value. */
#define BW_LCD_WF21_BPELCD21(x, v) (BME_BFI8(HW_LCD_WF21_ADDR(x), ((uint8_t)(v) << BP_LCD_WF21_BPELCD21), BP_LCD_WF21_BPELCD21, 1))
/*@}*/

/*!
 * @name Register LCD_WF21, field BPFLCD21[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF21_BPFLCD21 (5U)          /*!< Bit position for LCD_WF21_BPFLCD21. */
#define BM_LCD_WF21_BPFLCD21 (0x20U)       /*!< Bit mask for LCD_WF21_BPFLCD21. */
#define BS_LCD_WF21_BPFLCD21 (1U)          /*!< Bit field size in bits for LCD_WF21_BPFLCD21. */

/*! @brief Read current value of the LCD_WF21_BPFLCD21 field. */
#define BR_LCD_WF21_BPFLCD21(x) (BME_UBFX8(HW_LCD_WF21_ADDR(x), BP_LCD_WF21_BPFLCD21, BS_LCD_WF21_BPFLCD21))

/*! @brief Format value for bitfield LCD_WF21_BPFLCD21. */
#define BF_LCD_WF21_BPFLCD21(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF21_BPFLCD21) & BM_LCD_WF21_BPFLCD21)

/*! @brief Set the BPFLCD21 field to a new value. */
#define BW_LCD_WF21_BPFLCD21(x, v) (BME_BFI8(HW_LCD_WF21_ADDR(x), ((uint8_t)(v) << BP_LCD_WF21_BPFLCD21), BP_LCD_WF21_BPFLCD21, 1))
/*@}*/

/*!
 * @name Register LCD_WF21, field BPGLCD21[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF21_BPGLCD21 (6U)          /*!< Bit position for LCD_WF21_BPGLCD21. */
#define BM_LCD_WF21_BPGLCD21 (0x40U)       /*!< Bit mask for LCD_WF21_BPGLCD21. */
#define BS_LCD_WF21_BPGLCD21 (1U)          /*!< Bit field size in bits for LCD_WF21_BPGLCD21. */

/*! @brief Read current value of the LCD_WF21_BPGLCD21 field. */
#define BR_LCD_WF21_BPGLCD21(x) (BME_UBFX8(HW_LCD_WF21_ADDR(x), BP_LCD_WF21_BPGLCD21, BS_LCD_WF21_BPGLCD21))

/*! @brief Format value for bitfield LCD_WF21_BPGLCD21. */
#define BF_LCD_WF21_BPGLCD21(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF21_BPGLCD21) & BM_LCD_WF21_BPGLCD21)

/*! @brief Set the BPGLCD21 field to a new value. */
#define BW_LCD_WF21_BPGLCD21(x, v) (BME_BFI8(HW_LCD_WF21_ADDR(x), ((uint8_t)(v) << BP_LCD_WF21_BPGLCD21), BP_LCD_WF21_BPGLCD21, 1))
/*@}*/

/*!
 * @name Register LCD_WF21, field BPHLCD21[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF21_BPHLCD21 (7U)          /*!< Bit position for LCD_WF21_BPHLCD21. */
#define BM_LCD_WF21_BPHLCD21 (0x80U)       /*!< Bit mask for LCD_WF21_BPHLCD21. */
#define BS_LCD_WF21_BPHLCD21 (1U)          /*!< Bit field size in bits for LCD_WF21_BPHLCD21. */

/*! @brief Read current value of the LCD_WF21_BPHLCD21 field. */
#define BR_LCD_WF21_BPHLCD21(x) (BME_UBFX8(HW_LCD_WF21_ADDR(x), BP_LCD_WF21_BPHLCD21, BS_LCD_WF21_BPHLCD21))

/*! @brief Format value for bitfield LCD_WF21_BPHLCD21. */
#define BF_LCD_WF21_BPHLCD21(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF21_BPHLCD21) & BM_LCD_WF21_BPHLCD21)

/*! @brief Set the BPHLCD21 field to a new value. */
#define BW_LCD_WF21_BPHLCD21(x, v) (BME_BFI8(HW_LCD_WF21_ADDR(x), ((uint8_t)(v) << BP_LCD_WF21_BPHLCD21), BP_LCD_WF21_BPHLCD21, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF22 - LCD Waveform Register 22.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF22 - LCD Waveform Register 22. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf22
{
    uint8_t U;
    struct _hw_lcd_wf22_bitfields
    {
        uint8_t BPALCD22 : 1;          /*!< [0]  */
        uint8_t BPBLCD22 : 1;          /*!< [1]  */
        uint8_t BPCLCD22 : 1;          /*!< [2]  */
        uint8_t BPDLCD22 : 1;          /*!< [3]  */
        uint8_t BPELCD22 : 1;          /*!< [4]  */
        uint8_t BPFLCD22 : 1;          /*!< [5]  */
        uint8_t BPGLCD22 : 1;          /*!< [6]  */
        uint8_t BPHLCD22 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf22_t;

/*!
 * @name Constants and macros for entire LCD_WF22 register
 */
/*@{*/
#define HW_LCD_WF22_ADDR(x)      ((x) + 0x36U)

#define HW_LCD_WF22(x)           (*(__IO hw_lcd_wf22_t *) HW_LCD_WF22_ADDR(x))
#define HW_LCD_WF22_RD(x)        (HW_LCD_WF22(x).U)
#define HW_LCD_WF22_WR(x, v)     (HW_LCD_WF22(x).U = (v))
#define HW_LCD_WF22_SET(x, v)    (BME_OR8(HW_LCD_WF22_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF22_CLR(x, v)    (BME_AND8(HW_LCD_WF22_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF22_TOG(x, v)    (BME_XOR8(HW_LCD_WF22_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF22 bitfields
 */

/*!
 * @name Register LCD_WF22, field BPALCD22[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF22_BPALCD22 (0U)          /*!< Bit position for LCD_WF22_BPALCD22. */
#define BM_LCD_WF22_BPALCD22 (0x01U)       /*!< Bit mask for LCD_WF22_BPALCD22. */
#define BS_LCD_WF22_BPALCD22 (1U)          /*!< Bit field size in bits for LCD_WF22_BPALCD22. */

/*! @brief Read current value of the LCD_WF22_BPALCD22 field. */
#define BR_LCD_WF22_BPALCD22(x) (BME_UBFX8(HW_LCD_WF22_ADDR(x), BP_LCD_WF22_BPALCD22, BS_LCD_WF22_BPALCD22))

/*! @brief Format value for bitfield LCD_WF22_BPALCD22. */
#define BF_LCD_WF22_BPALCD22(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF22_BPALCD22) & BM_LCD_WF22_BPALCD22)

/*! @brief Set the BPALCD22 field to a new value. */
#define BW_LCD_WF22_BPALCD22(x, v) (BME_BFI8(HW_LCD_WF22_ADDR(x), ((uint8_t)(v) << BP_LCD_WF22_BPALCD22), BP_LCD_WF22_BPALCD22, 1))
/*@}*/

/*!
 * @name Register LCD_WF22, field BPBLCD22[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF22_BPBLCD22 (1U)          /*!< Bit position for LCD_WF22_BPBLCD22. */
#define BM_LCD_WF22_BPBLCD22 (0x02U)       /*!< Bit mask for LCD_WF22_BPBLCD22. */
#define BS_LCD_WF22_BPBLCD22 (1U)          /*!< Bit field size in bits for LCD_WF22_BPBLCD22. */

/*! @brief Read current value of the LCD_WF22_BPBLCD22 field. */
#define BR_LCD_WF22_BPBLCD22(x) (BME_UBFX8(HW_LCD_WF22_ADDR(x), BP_LCD_WF22_BPBLCD22, BS_LCD_WF22_BPBLCD22))

/*! @brief Format value for bitfield LCD_WF22_BPBLCD22. */
#define BF_LCD_WF22_BPBLCD22(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF22_BPBLCD22) & BM_LCD_WF22_BPBLCD22)

/*! @brief Set the BPBLCD22 field to a new value. */
#define BW_LCD_WF22_BPBLCD22(x, v) (BME_BFI8(HW_LCD_WF22_ADDR(x), ((uint8_t)(v) << BP_LCD_WF22_BPBLCD22), BP_LCD_WF22_BPBLCD22, 1))
/*@}*/

/*!
 * @name Register LCD_WF22, field BPCLCD22[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF22_BPCLCD22 (2U)          /*!< Bit position for LCD_WF22_BPCLCD22. */
#define BM_LCD_WF22_BPCLCD22 (0x04U)       /*!< Bit mask for LCD_WF22_BPCLCD22. */
#define BS_LCD_WF22_BPCLCD22 (1U)          /*!< Bit field size in bits for LCD_WF22_BPCLCD22. */

/*! @brief Read current value of the LCD_WF22_BPCLCD22 field. */
#define BR_LCD_WF22_BPCLCD22(x) (BME_UBFX8(HW_LCD_WF22_ADDR(x), BP_LCD_WF22_BPCLCD22, BS_LCD_WF22_BPCLCD22))

/*! @brief Format value for bitfield LCD_WF22_BPCLCD22. */
#define BF_LCD_WF22_BPCLCD22(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF22_BPCLCD22) & BM_LCD_WF22_BPCLCD22)

/*! @brief Set the BPCLCD22 field to a new value. */
#define BW_LCD_WF22_BPCLCD22(x, v) (BME_BFI8(HW_LCD_WF22_ADDR(x), ((uint8_t)(v) << BP_LCD_WF22_BPCLCD22), BP_LCD_WF22_BPCLCD22, 1))
/*@}*/

/*!
 * @name Register LCD_WF22, field BPDLCD22[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF22_BPDLCD22 (3U)          /*!< Bit position for LCD_WF22_BPDLCD22. */
#define BM_LCD_WF22_BPDLCD22 (0x08U)       /*!< Bit mask for LCD_WF22_BPDLCD22. */
#define BS_LCD_WF22_BPDLCD22 (1U)          /*!< Bit field size in bits for LCD_WF22_BPDLCD22. */

/*! @brief Read current value of the LCD_WF22_BPDLCD22 field. */
#define BR_LCD_WF22_BPDLCD22(x) (BME_UBFX8(HW_LCD_WF22_ADDR(x), BP_LCD_WF22_BPDLCD22, BS_LCD_WF22_BPDLCD22))

/*! @brief Format value for bitfield LCD_WF22_BPDLCD22. */
#define BF_LCD_WF22_BPDLCD22(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF22_BPDLCD22) & BM_LCD_WF22_BPDLCD22)

/*! @brief Set the BPDLCD22 field to a new value. */
#define BW_LCD_WF22_BPDLCD22(x, v) (BME_BFI8(HW_LCD_WF22_ADDR(x), ((uint8_t)(v) << BP_LCD_WF22_BPDLCD22), BP_LCD_WF22_BPDLCD22, 1))
/*@}*/

/*!
 * @name Register LCD_WF22, field BPELCD22[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF22_BPELCD22 (4U)          /*!< Bit position for LCD_WF22_BPELCD22. */
#define BM_LCD_WF22_BPELCD22 (0x10U)       /*!< Bit mask for LCD_WF22_BPELCD22. */
#define BS_LCD_WF22_BPELCD22 (1U)          /*!< Bit field size in bits for LCD_WF22_BPELCD22. */

/*! @brief Read current value of the LCD_WF22_BPELCD22 field. */
#define BR_LCD_WF22_BPELCD22(x) (BME_UBFX8(HW_LCD_WF22_ADDR(x), BP_LCD_WF22_BPELCD22, BS_LCD_WF22_BPELCD22))

/*! @brief Format value for bitfield LCD_WF22_BPELCD22. */
#define BF_LCD_WF22_BPELCD22(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF22_BPELCD22) & BM_LCD_WF22_BPELCD22)

/*! @brief Set the BPELCD22 field to a new value. */
#define BW_LCD_WF22_BPELCD22(x, v) (BME_BFI8(HW_LCD_WF22_ADDR(x), ((uint8_t)(v) << BP_LCD_WF22_BPELCD22), BP_LCD_WF22_BPELCD22, 1))
/*@}*/

/*!
 * @name Register LCD_WF22, field BPFLCD22[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF22_BPFLCD22 (5U)          /*!< Bit position for LCD_WF22_BPFLCD22. */
#define BM_LCD_WF22_BPFLCD22 (0x20U)       /*!< Bit mask for LCD_WF22_BPFLCD22. */
#define BS_LCD_WF22_BPFLCD22 (1U)          /*!< Bit field size in bits for LCD_WF22_BPFLCD22. */

/*! @brief Read current value of the LCD_WF22_BPFLCD22 field. */
#define BR_LCD_WF22_BPFLCD22(x) (BME_UBFX8(HW_LCD_WF22_ADDR(x), BP_LCD_WF22_BPFLCD22, BS_LCD_WF22_BPFLCD22))

/*! @brief Format value for bitfield LCD_WF22_BPFLCD22. */
#define BF_LCD_WF22_BPFLCD22(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF22_BPFLCD22) & BM_LCD_WF22_BPFLCD22)

/*! @brief Set the BPFLCD22 field to a new value. */
#define BW_LCD_WF22_BPFLCD22(x, v) (BME_BFI8(HW_LCD_WF22_ADDR(x), ((uint8_t)(v) << BP_LCD_WF22_BPFLCD22), BP_LCD_WF22_BPFLCD22, 1))
/*@}*/

/*!
 * @name Register LCD_WF22, field BPGLCD22[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF22_BPGLCD22 (6U)          /*!< Bit position for LCD_WF22_BPGLCD22. */
#define BM_LCD_WF22_BPGLCD22 (0x40U)       /*!< Bit mask for LCD_WF22_BPGLCD22. */
#define BS_LCD_WF22_BPGLCD22 (1U)          /*!< Bit field size in bits for LCD_WF22_BPGLCD22. */

/*! @brief Read current value of the LCD_WF22_BPGLCD22 field. */
#define BR_LCD_WF22_BPGLCD22(x) (BME_UBFX8(HW_LCD_WF22_ADDR(x), BP_LCD_WF22_BPGLCD22, BS_LCD_WF22_BPGLCD22))

/*! @brief Format value for bitfield LCD_WF22_BPGLCD22. */
#define BF_LCD_WF22_BPGLCD22(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF22_BPGLCD22) & BM_LCD_WF22_BPGLCD22)

/*! @brief Set the BPGLCD22 field to a new value. */
#define BW_LCD_WF22_BPGLCD22(x, v) (BME_BFI8(HW_LCD_WF22_ADDR(x), ((uint8_t)(v) << BP_LCD_WF22_BPGLCD22), BP_LCD_WF22_BPGLCD22, 1))
/*@}*/

/*!
 * @name Register LCD_WF22, field BPHLCD22[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF22_BPHLCD22 (7U)          /*!< Bit position for LCD_WF22_BPHLCD22. */
#define BM_LCD_WF22_BPHLCD22 (0x80U)       /*!< Bit mask for LCD_WF22_BPHLCD22. */
#define BS_LCD_WF22_BPHLCD22 (1U)          /*!< Bit field size in bits for LCD_WF22_BPHLCD22. */

/*! @brief Read current value of the LCD_WF22_BPHLCD22 field. */
#define BR_LCD_WF22_BPHLCD22(x) (BME_UBFX8(HW_LCD_WF22_ADDR(x), BP_LCD_WF22_BPHLCD22, BS_LCD_WF22_BPHLCD22))

/*! @brief Format value for bitfield LCD_WF22_BPHLCD22. */
#define BF_LCD_WF22_BPHLCD22(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF22_BPHLCD22) & BM_LCD_WF22_BPHLCD22)

/*! @brief Set the BPHLCD22 field to a new value. */
#define BW_LCD_WF22_BPHLCD22(x, v) (BME_BFI8(HW_LCD_WF22_ADDR(x), ((uint8_t)(v) << BP_LCD_WF22_BPHLCD22), BP_LCD_WF22_BPHLCD22, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF23 - LCD Waveform Register 23.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF23 - LCD Waveform Register 23. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf23
{
    uint8_t U;
    struct _hw_lcd_wf23_bitfields
    {
        uint8_t BPALCD23 : 1;          /*!< [0]  */
        uint8_t BPBLCD23 : 1;          /*!< [1]  */
        uint8_t BPCLCD23 : 1;          /*!< [2]  */
        uint8_t BPDLCD23 : 1;          /*!< [3]  */
        uint8_t BPELCD23 : 1;          /*!< [4]  */
        uint8_t BPFLCD23 : 1;          /*!< [5]  */
        uint8_t BPGLCD23 : 1;          /*!< [6]  */
        uint8_t BPHLCD23 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf23_t;

/*!
 * @name Constants and macros for entire LCD_WF23 register
 */
/*@{*/
#define HW_LCD_WF23_ADDR(x)      ((x) + 0x37U)

#define HW_LCD_WF23(x)           (*(__IO hw_lcd_wf23_t *) HW_LCD_WF23_ADDR(x))
#define HW_LCD_WF23_RD(x)        (HW_LCD_WF23(x).U)
#define HW_LCD_WF23_WR(x, v)     (HW_LCD_WF23(x).U = (v))
#define HW_LCD_WF23_SET(x, v)    (BME_OR8(HW_LCD_WF23_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF23_CLR(x, v)    (BME_AND8(HW_LCD_WF23_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF23_TOG(x, v)    (BME_XOR8(HW_LCD_WF23_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF23 bitfields
 */

/*!
 * @name Register LCD_WF23, field BPALCD23[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF23_BPALCD23 (0U)          /*!< Bit position for LCD_WF23_BPALCD23. */
#define BM_LCD_WF23_BPALCD23 (0x01U)       /*!< Bit mask for LCD_WF23_BPALCD23. */
#define BS_LCD_WF23_BPALCD23 (1U)          /*!< Bit field size in bits for LCD_WF23_BPALCD23. */

/*! @brief Read current value of the LCD_WF23_BPALCD23 field. */
#define BR_LCD_WF23_BPALCD23(x) (BME_UBFX8(HW_LCD_WF23_ADDR(x), BP_LCD_WF23_BPALCD23, BS_LCD_WF23_BPALCD23))

/*! @brief Format value for bitfield LCD_WF23_BPALCD23. */
#define BF_LCD_WF23_BPALCD23(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF23_BPALCD23) & BM_LCD_WF23_BPALCD23)

/*! @brief Set the BPALCD23 field to a new value. */
#define BW_LCD_WF23_BPALCD23(x, v) (BME_BFI8(HW_LCD_WF23_ADDR(x), ((uint8_t)(v) << BP_LCD_WF23_BPALCD23), BP_LCD_WF23_BPALCD23, 1))
/*@}*/

/*!
 * @name Register LCD_WF23, field BPBLCD23[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF23_BPBLCD23 (1U)          /*!< Bit position for LCD_WF23_BPBLCD23. */
#define BM_LCD_WF23_BPBLCD23 (0x02U)       /*!< Bit mask for LCD_WF23_BPBLCD23. */
#define BS_LCD_WF23_BPBLCD23 (1U)          /*!< Bit field size in bits for LCD_WF23_BPBLCD23. */

/*! @brief Read current value of the LCD_WF23_BPBLCD23 field. */
#define BR_LCD_WF23_BPBLCD23(x) (BME_UBFX8(HW_LCD_WF23_ADDR(x), BP_LCD_WF23_BPBLCD23, BS_LCD_WF23_BPBLCD23))

/*! @brief Format value for bitfield LCD_WF23_BPBLCD23. */
#define BF_LCD_WF23_BPBLCD23(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF23_BPBLCD23) & BM_LCD_WF23_BPBLCD23)

/*! @brief Set the BPBLCD23 field to a new value. */
#define BW_LCD_WF23_BPBLCD23(x, v) (BME_BFI8(HW_LCD_WF23_ADDR(x), ((uint8_t)(v) << BP_LCD_WF23_BPBLCD23), BP_LCD_WF23_BPBLCD23, 1))
/*@}*/

/*!
 * @name Register LCD_WF23, field BPCLCD23[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF23_BPCLCD23 (2U)          /*!< Bit position for LCD_WF23_BPCLCD23. */
#define BM_LCD_WF23_BPCLCD23 (0x04U)       /*!< Bit mask for LCD_WF23_BPCLCD23. */
#define BS_LCD_WF23_BPCLCD23 (1U)          /*!< Bit field size in bits for LCD_WF23_BPCLCD23. */

/*! @brief Read current value of the LCD_WF23_BPCLCD23 field. */
#define BR_LCD_WF23_BPCLCD23(x) (BME_UBFX8(HW_LCD_WF23_ADDR(x), BP_LCD_WF23_BPCLCD23, BS_LCD_WF23_BPCLCD23))

/*! @brief Format value for bitfield LCD_WF23_BPCLCD23. */
#define BF_LCD_WF23_BPCLCD23(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF23_BPCLCD23) & BM_LCD_WF23_BPCLCD23)

/*! @brief Set the BPCLCD23 field to a new value. */
#define BW_LCD_WF23_BPCLCD23(x, v) (BME_BFI8(HW_LCD_WF23_ADDR(x), ((uint8_t)(v) << BP_LCD_WF23_BPCLCD23), BP_LCD_WF23_BPCLCD23, 1))
/*@}*/

/*!
 * @name Register LCD_WF23, field BPDLCD23[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF23_BPDLCD23 (3U)          /*!< Bit position for LCD_WF23_BPDLCD23. */
#define BM_LCD_WF23_BPDLCD23 (0x08U)       /*!< Bit mask for LCD_WF23_BPDLCD23. */
#define BS_LCD_WF23_BPDLCD23 (1U)          /*!< Bit field size in bits for LCD_WF23_BPDLCD23. */

/*! @brief Read current value of the LCD_WF23_BPDLCD23 field. */
#define BR_LCD_WF23_BPDLCD23(x) (BME_UBFX8(HW_LCD_WF23_ADDR(x), BP_LCD_WF23_BPDLCD23, BS_LCD_WF23_BPDLCD23))

/*! @brief Format value for bitfield LCD_WF23_BPDLCD23. */
#define BF_LCD_WF23_BPDLCD23(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF23_BPDLCD23) & BM_LCD_WF23_BPDLCD23)

/*! @brief Set the BPDLCD23 field to a new value. */
#define BW_LCD_WF23_BPDLCD23(x, v) (BME_BFI8(HW_LCD_WF23_ADDR(x), ((uint8_t)(v) << BP_LCD_WF23_BPDLCD23), BP_LCD_WF23_BPDLCD23, 1))
/*@}*/

/*!
 * @name Register LCD_WF23, field BPELCD23[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF23_BPELCD23 (4U)          /*!< Bit position for LCD_WF23_BPELCD23. */
#define BM_LCD_WF23_BPELCD23 (0x10U)       /*!< Bit mask for LCD_WF23_BPELCD23. */
#define BS_LCD_WF23_BPELCD23 (1U)          /*!< Bit field size in bits for LCD_WF23_BPELCD23. */

/*! @brief Read current value of the LCD_WF23_BPELCD23 field. */
#define BR_LCD_WF23_BPELCD23(x) (BME_UBFX8(HW_LCD_WF23_ADDR(x), BP_LCD_WF23_BPELCD23, BS_LCD_WF23_BPELCD23))

/*! @brief Format value for bitfield LCD_WF23_BPELCD23. */
#define BF_LCD_WF23_BPELCD23(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF23_BPELCD23) & BM_LCD_WF23_BPELCD23)

/*! @brief Set the BPELCD23 field to a new value. */
#define BW_LCD_WF23_BPELCD23(x, v) (BME_BFI8(HW_LCD_WF23_ADDR(x), ((uint8_t)(v) << BP_LCD_WF23_BPELCD23), BP_LCD_WF23_BPELCD23, 1))
/*@}*/

/*!
 * @name Register LCD_WF23, field BPFLCD23[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF23_BPFLCD23 (5U)          /*!< Bit position for LCD_WF23_BPFLCD23. */
#define BM_LCD_WF23_BPFLCD23 (0x20U)       /*!< Bit mask for LCD_WF23_BPFLCD23. */
#define BS_LCD_WF23_BPFLCD23 (1U)          /*!< Bit field size in bits for LCD_WF23_BPFLCD23. */

/*! @brief Read current value of the LCD_WF23_BPFLCD23 field. */
#define BR_LCD_WF23_BPFLCD23(x) (BME_UBFX8(HW_LCD_WF23_ADDR(x), BP_LCD_WF23_BPFLCD23, BS_LCD_WF23_BPFLCD23))

/*! @brief Format value for bitfield LCD_WF23_BPFLCD23. */
#define BF_LCD_WF23_BPFLCD23(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF23_BPFLCD23) & BM_LCD_WF23_BPFLCD23)

/*! @brief Set the BPFLCD23 field to a new value. */
#define BW_LCD_WF23_BPFLCD23(x, v) (BME_BFI8(HW_LCD_WF23_ADDR(x), ((uint8_t)(v) << BP_LCD_WF23_BPFLCD23), BP_LCD_WF23_BPFLCD23, 1))
/*@}*/

/*!
 * @name Register LCD_WF23, field BPGLCD23[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF23_BPGLCD23 (6U)          /*!< Bit position for LCD_WF23_BPGLCD23. */
#define BM_LCD_WF23_BPGLCD23 (0x40U)       /*!< Bit mask for LCD_WF23_BPGLCD23. */
#define BS_LCD_WF23_BPGLCD23 (1U)          /*!< Bit field size in bits for LCD_WF23_BPGLCD23. */

/*! @brief Read current value of the LCD_WF23_BPGLCD23 field. */
#define BR_LCD_WF23_BPGLCD23(x) (BME_UBFX8(HW_LCD_WF23_ADDR(x), BP_LCD_WF23_BPGLCD23, BS_LCD_WF23_BPGLCD23))

/*! @brief Format value for bitfield LCD_WF23_BPGLCD23. */
#define BF_LCD_WF23_BPGLCD23(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF23_BPGLCD23) & BM_LCD_WF23_BPGLCD23)

/*! @brief Set the BPGLCD23 field to a new value. */
#define BW_LCD_WF23_BPGLCD23(x, v) (BME_BFI8(HW_LCD_WF23_ADDR(x), ((uint8_t)(v) << BP_LCD_WF23_BPGLCD23), BP_LCD_WF23_BPGLCD23, 1))
/*@}*/

/*!
 * @name Register LCD_WF23, field BPHLCD23[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF23_BPHLCD23 (7U)          /*!< Bit position for LCD_WF23_BPHLCD23. */
#define BM_LCD_WF23_BPHLCD23 (0x80U)       /*!< Bit mask for LCD_WF23_BPHLCD23. */
#define BS_LCD_WF23_BPHLCD23 (1U)          /*!< Bit field size in bits for LCD_WF23_BPHLCD23. */

/*! @brief Read current value of the LCD_WF23_BPHLCD23 field. */
#define BR_LCD_WF23_BPHLCD23(x) (BME_UBFX8(HW_LCD_WF23_ADDR(x), BP_LCD_WF23_BPHLCD23, BS_LCD_WF23_BPHLCD23))

/*! @brief Format value for bitfield LCD_WF23_BPHLCD23. */
#define BF_LCD_WF23_BPHLCD23(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF23_BPHLCD23) & BM_LCD_WF23_BPHLCD23)

/*! @brief Set the BPHLCD23 field to a new value. */
#define BW_LCD_WF23_BPHLCD23(x, v) (BME_BFI8(HW_LCD_WF23_ADDR(x), ((uint8_t)(v) << BP_LCD_WF23_BPHLCD23), BP_LCD_WF23_BPHLCD23, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF24 - LCD Waveform Register 24.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF24 - LCD Waveform Register 24. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf24
{
    uint8_t U;
    struct _hw_lcd_wf24_bitfields
    {
        uint8_t BPALCD24 : 1;          /*!< [0]  */
        uint8_t BPBLCD24 : 1;          /*!< [1]  */
        uint8_t BPCLCD24 : 1;          /*!< [2]  */
        uint8_t BPDLCD24 : 1;          /*!< [3]  */
        uint8_t BPELCD24 : 1;          /*!< [4]  */
        uint8_t BPFLCD24 : 1;          /*!< [5]  */
        uint8_t BPGLCD24 : 1;          /*!< [6]  */
        uint8_t BPHLCD24 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf24_t;

/*!
 * @name Constants and macros for entire LCD_WF24 register
 */
/*@{*/
#define HW_LCD_WF24_ADDR(x)      ((x) + 0x38U)

#define HW_LCD_WF24(x)           (*(__IO hw_lcd_wf24_t *) HW_LCD_WF24_ADDR(x))
#define HW_LCD_WF24_RD(x)        (HW_LCD_WF24(x).U)
#define HW_LCD_WF24_WR(x, v)     (HW_LCD_WF24(x).U = (v))
#define HW_LCD_WF24_SET(x, v)    (BME_OR8(HW_LCD_WF24_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF24_CLR(x, v)    (BME_AND8(HW_LCD_WF24_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF24_TOG(x, v)    (BME_XOR8(HW_LCD_WF24_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF24 bitfields
 */

/*!
 * @name Register LCD_WF24, field BPALCD24[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF24_BPALCD24 (0U)          /*!< Bit position for LCD_WF24_BPALCD24. */
#define BM_LCD_WF24_BPALCD24 (0x01U)       /*!< Bit mask for LCD_WF24_BPALCD24. */
#define BS_LCD_WF24_BPALCD24 (1U)          /*!< Bit field size in bits for LCD_WF24_BPALCD24. */

/*! @brief Read current value of the LCD_WF24_BPALCD24 field. */
#define BR_LCD_WF24_BPALCD24(x) (BME_UBFX8(HW_LCD_WF24_ADDR(x), BP_LCD_WF24_BPALCD24, BS_LCD_WF24_BPALCD24))

/*! @brief Format value for bitfield LCD_WF24_BPALCD24. */
#define BF_LCD_WF24_BPALCD24(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF24_BPALCD24) & BM_LCD_WF24_BPALCD24)

/*! @brief Set the BPALCD24 field to a new value. */
#define BW_LCD_WF24_BPALCD24(x, v) (BME_BFI8(HW_LCD_WF24_ADDR(x), ((uint8_t)(v) << BP_LCD_WF24_BPALCD24), BP_LCD_WF24_BPALCD24, 1))
/*@}*/

/*!
 * @name Register LCD_WF24, field BPBLCD24[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF24_BPBLCD24 (1U)          /*!< Bit position for LCD_WF24_BPBLCD24. */
#define BM_LCD_WF24_BPBLCD24 (0x02U)       /*!< Bit mask for LCD_WF24_BPBLCD24. */
#define BS_LCD_WF24_BPBLCD24 (1U)          /*!< Bit field size in bits for LCD_WF24_BPBLCD24. */

/*! @brief Read current value of the LCD_WF24_BPBLCD24 field. */
#define BR_LCD_WF24_BPBLCD24(x) (BME_UBFX8(HW_LCD_WF24_ADDR(x), BP_LCD_WF24_BPBLCD24, BS_LCD_WF24_BPBLCD24))

/*! @brief Format value for bitfield LCD_WF24_BPBLCD24. */
#define BF_LCD_WF24_BPBLCD24(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF24_BPBLCD24) & BM_LCD_WF24_BPBLCD24)

/*! @brief Set the BPBLCD24 field to a new value. */
#define BW_LCD_WF24_BPBLCD24(x, v) (BME_BFI8(HW_LCD_WF24_ADDR(x), ((uint8_t)(v) << BP_LCD_WF24_BPBLCD24), BP_LCD_WF24_BPBLCD24, 1))
/*@}*/

/*!
 * @name Register LCD_WF24, field BPCLCD24[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF24_BPCLCD24 (2U)          /*!< Bit position for LCD_WF24_BPCLCD24. */
#define BM_LCD_WF24_BPCLCD24 (0x04U)       /*!< Bit mask for LCD_WF24_BPCLCD24. */
#define BS_LCD_WF24_BPCLCD24 (1U)          /*!< Bit field size in bits for LCD_WF24_BPCLCD24. */

/*! @brief Read current value of the LCD_WF24_BPCLCD24 field. */
#define BR_LCD_WF24_BPCLCD24(x) (BME_UBFX8(HW_LCD_WF24_ADDR(x), BP_LCD_WF24_BPCLCD24, BS_LCD_WF24_BPCLCD24))

/*! @brief Format value for bitfield LCD_WF24_BPCLCD24. */
#define BF_LCD_WF24_BPCLCD24(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF24_BPCLCD24) & BM_LCD_WF24_BPCLCD24)

/*! @brief Set the BPCLCD24 field to a new value. */
#define BW_LCD_WF24_BPCLCD24(x, v) (BME_BFI8(HW_LCD_WF24_ADDR(x), ((uint8_t)(v) << BP_LCD_WF24_BPCLCD24), BP_LCD_WF24_BPCLCD24, 1))
/*@}*/

/*!
 * @name Register LCD_WF24, field BPDLCD24[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF24_BPDLCD24 (3U)          /*!< Bit position for LCD_WF24_BPDLCD24. */
#define BM_LCD_WF24_BPDLCD24 (0x08U)       /*!< Bit mask for LCD_WF24_BPDLCD24. */
#define BS_LCD_WF24_BPDLCD24 (1U)          /*!< Bit field size in bits for LCD_WF24_BPDLCD24. */

/*! @brief Read current value of the LCD_WF24_BPDLCD24 field. */
#define BR_LCD_WF24_BPDLCD24(x) (BME_UBFX8(HW_LCD_WF24_ADDR(x), BP_LCD_WF24_BPDLCD24, BS_LCD_WF24_BPDLCD24))

/*! @brief Format value for bitfield LCD_WF24_BPDLCD24. */
#define BF_LCD_WF24_BPDLCD24(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF24_BPDLCD24) & BM_LCD_WF24_BPDLCD24)

/*! @brief Set the BPDLCD24 field to a new value. */
#define BW_LCD_WF24_BPDLCD24(x, v) (BME_BFI8(HW_LCD_WF24_ADDR(x), ((uint8_t)(v) << BP_LCD_WF24_BPDLCD24), BP_LCD_WF24_BPDLCD24, 1))
/*@}*/

/*!
 * @name Register LCD_WF24, field BPELCD24[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF24_BPELCD24 (4U)          /*!< Bit position for LCD_WF24_BPELCD24. */
#define BM_LCD_WF24_BPELCD24 (0x10U)       /*!< Bit mask for LCD_WF24_BPELCD24. */
#define BS_LCD_WF24_BPELCD24 (1U)          /*!< Bit field size in bits for LCD_WF24_BPELCD24. */

/*! @brief Read current value of the LCD_WF24_BPELCD24 field. */
#define BR_LCD_WF24_BPELCD24(x) (BME_UBFX8(HW_LCD_WF24_ADDR(x), BP_LCD_WF24_BPELCD24, BS_LCD_WF24_BPELCD24))

/*! @brief Format value for bitfield LCD_WF24_BPELCD24. */
#define BF_LCD_WF24_BPELCD24(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF24_BPELCD24) & BM_LCD_WF24_BPELCD24)

/*! @brief Set the BPELCD24 field to a new value. */
#define BW_LCD_WF24_BPELCD24(x, v) (BME_BFI8(HW_LCD_WF24_ADDR(x), ((uint8_t)(v) << BP_LCD_WF24_BPELCD24), BP_LCD_WF24_BPELCD24, 1))
/*@}*/

/*!
 * @name Register LCD_WF24, field BPFLCD24[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF24_BPFLCD24 (5U)          /*!< Bit position for LCD_WF24_BPFLCD24. */
#define BM_LCD_WF24_BPFLCD24 (0x20U)       /*!< Bit mask for LCD_WF24_BPFLCD24. */
#define BS_LCD_WF24_BPFLCD24 (1U)          /*!< Bit field size in bits for LCD_WF24_BPFLCD24. */

/*! @brief Read current value of the LCD_WF24_BPFLCD24 field. */
#define BR_LCD_WF24_BPFLCD24(x) (BME_UBFX8(HW_LCD_WF24_ADDR(x), BP_LCD_WF24_BPFLCD24, BS_LCD_WF24_BPFLCD24))

/*! @brief Format value for bitfield LCD_WF24_BPFLCD24. */
#define BF_LCD_WF24_BPFLCD24(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF24_BPFLCD24) & BM_LCD_WF24_BPFLCD24)

/*! @brief Set the BPFLCD24 field to a new value. */
#define BW_LCD_WF24_BPFLCD24(x, v) (BME_BFI8(HW_LCD_WF24_ADDR(x), ((uint8_t)(v) << BP_LCD_WF24_BPFLCD24), BP_LCD_WF24_BPFLCD24, 1))
/*@}*/

/*!
 * @name Register LCD_WF24, field BPGLCD24[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF24_BPGLCD24 (6U)          /*!< Bit position for LCD_WF24_BPGLCD24. */
#define BM_LCD_WF24_BPGLCD24 (0x40U)       /*!< Bit mask for LCD_WF24_BPGLCD24. */
#define BS_LCD_WF24_BPGLCD24 (1U)          /*!< Bit field size in bits for LCD_WF24_BPGLCD24. */

/*! @brief Read current value of the LCD_WF24_BPGLCD24 field. */
#define BR_LCD_WF24_BPGLCD24(x) (BME_UBFX8(HW_LCD_WF24_ADDR(x), BP_LCD_WF24_BPGLCD24, BS_LCD_WF24_BPGLCD24))

/*! @brief Format value for bitfield LCD_WF24_BPGLCD24. */
#define BF_LCD_WF24_BPGLCD24(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF24_BPGLCD24) & BM_LCD_WF24_BPGLCD24)

/*! @brief Set the BPGLCD24 field to a new value. */
#define BW_LCD_WF24_BPGLCD24(x, v) (BME_BFI8(HW_LCD_WF24_ADDR(x), ((uint8_t)(v) << BP_LCD_WF24_BPGLCD24), BP_LCD_WF24_BPGLCD24, 1))
/*@}*/

/*!
 * @name Register LCD_WF24, field BPHLCD24[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF24_BPHLCD24 (7U)          /*!< Bit position for LCD_WF24_BPHLCD24. */
#define BM_LCD_WF24_BPHLCD24 (0x80U)       /*!< Bit mask for LCD_WF24_BPHLCD24. */
#define BS_LCD_WF24_BPHLCD24 (1U)          /*!< Bit field size in bits for LCD_WF24_BPHLCD24. */

/*! @brief Read current value of the LCD_WF24_BPHLCD24 field. */
#define BR_LCD_WF24_BPHLCD24(x) (BME_UBFX8(HW_LCD_WF24_ADDR(x), BP_LCD_WF24_BPHLCD24, BS_LCD_WF24_BPHLCD24))

/*! @brief Format value for bitfield LCD_WF24_BPHLCD24. */
#define BF_LCD_WF24_BPHLCD24(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF24_BPHLCD24) & BM_LCD_WF24_BPHLCD24)

/*! @brief Set the BPHLCD24 field to a new value. */
#define BW_LCD_WF24_BPHLCD24(x, v) (BME_BFI8(HW_LCD_WF24_ADDR(x), ((uint8_t)(v) << BP_LCD_WF24_BPHLCD24), BP_LCD_WF24_BPHLCD24, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF25 - LCD Waveform Register 25.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF25 - LCD Waveform Register 25. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf25
{
    uint8_t U;
    struct _hw_lcd_wf25_bitfields
    {
        uint8_t BPALCD25 : 1;          /*!< [0]  */
        uint8_t BPBLCD25 : 1;          /*!< [1]  */
        uint8_t BPCLCD25 : 1;          /*!< [2]  */
        uint8_t BPDLCD25 : 1;          /*!< [3]  */
        uint8_t BPELCD25 : 1;          /*!< [4]  */
        uint8_t BPFLCD25 : 1;          /*!< [5]  */
        uint8_t BPGLCD25 : 1;          /*!< [6]  */
        uint8_t BPHLCD25 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf25_t;

/*!
 * @name Constants and macros for entire LCD_WF25 register
 */
/*@{*/
#define HW_LCD_WF25_ADDR(x)      ((x) + 0x39U)

#define HW_LCD_WF25(x)           (*(__IO hw_lcd_wf25_t *) HW_LCD_WF25_ADDR(x))
#define HW_LCD_WF25_RD(x)        (HW_LCD_WF25(x).U)
#define HW_LCD_WF25_WR(x, v)     (HW_LCD_WF25(x).U = (v))
#define HW_LCD_WF25_SET(x, v)    (BME_OR8(HW_LCD_WF25_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF25_CLR(x, v)    (BME_AND8(HW_LCD_WF25_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF25_TOG(x, v)    (BME_XOR8(HW_LCD_WF25_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF25 bitfields
 */

/*!
 * @name Register LCD_WF25, field BPALCD25[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF25_BPALCD25 (0U)          /*!< Bit position for LCD_WF25_BPALCD25. */
#define BM_LCD_WF25_BPALCD25 (0x01U)       /*!< Bit mask for LCD_WF25_BPALCD25. */
#define BS_LCD_WF25_BPALCD25 (1U)          /*!< Bit field size in bits for LCD_WF25_BPALCD25. */

/*! @brief Read current value of the LCD_WF25_BPALCD25 field. */
#define BR_LCD_WF25_BPALCD25(x) (BME_UBFX8(HW_LCD_WF25_ADDR(x), BP_LCD_WF25_BPALCD25, BS_LCD_WF25_BPALCD25))

/*! @brief Format value for bitfield LCD_WF25_BPALCD25. */
#define BF_LCD_WF25_BPALCD25(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF25_BPALCD25) & BM_LCD_WF25_BPALCD25)

/*! @brief Set the BPALCD25 field to a new value. */
#define BW_LCD_WF25_BPALCD25(x, v) (BME_BFI8(HW_LCD_WF25_ADDR(x), ((uint8_t)(v) << BP_LCD_WF25_BPALCD25), BP_LCD_WF25_BPALCD25, 1))
/*@}*/

/*!
 * @name Register LCD_WF25, field BPBLCD25[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF25_BPBLCD25 (1U)          /*!< Bit position for LCD_WF25_BPBLCD25. */
#define BM_LCD_WF25_BPBLCD25 (0x02U)       /*!< Bit mask for LCD_WF25_BPBLCD25. */
#define BS_LCD_WF25_BPBLCD25 (1U)          /*!< Bit field size in bits for LCD_WF25_BPBLCD25. */

/*! @brief Read current value of the LCD_WF25_BPBLCD25 field. */
#define BR_LCD_WF25_BPBLCD25(x) (BME_UBFX8(HW_LCD_WF25_ADDR(x), BP_LCD_WF25_BPBLCD25, BS_LCD_WF25_BPBLCD25))

/*! @brief Format value for bitfield LCD_WF25_BPBLCD25. */
#define BF_LCD_WF25_BPBLCD25(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF25_BPBLCD25) & BM_LCD_WF25_BPBLCD25)

/*! @brief Set the BPBLCD25 field to a new value. */
#define BW_LCD_WF25_BPBLCD25(x, v) (BME_BFI8(HW_LCD_WF25_ADDR(x), ((uint8_t)(v) << BP_LCD_WF25_BPBLCD25), BP_LCD_WF25_BPBLCD25, 1))
/*@}*/

/*!
 * @name Register LCD_WF25, field BPCLCD25[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF25_BPCLCD25 (2U)          /*!< Bit position for LCD_WF25_BPCLCD25. */
#define BM_LCD_WF25_BPCLCD25 (0x04U)       /*!< Bit mask for LCD_WF25_BPCLCD25. */
#define BS_LCD_WF25_BPCLCD25 (1U)          /*!< Bit field size in bits for LCD_WF25_BPCLCD25. */

/*! @brief Read current value of the LCD_WF25_BPCLCD25 field. */
#define BR_LCD_WF25_BPCLCD25(x) (BME_UBFX8(HW_LCD_WF25_ADDR(x), BP_LCD_WF25_BPCLCD25, BS_LCD_WF25_BPCLCD25))

/*! @brief Format value for bitfield LCD_WF25_BPCLCD25. */
#define BF_LCD_WF25_BPCLCD25(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF25_BPCLCD25) & BM_LCD_WF25_BPCLCD25)

/*! @brief Set the BPCLCD25 field to a new value. */
#define BW_LCD_WF25_BPCLCD25(x, v) (BME_BFI8(HW_LCD_WF25_ADDR(x), ((uint8_t)(v) << BP_LCD_WF25_BPCLCD25), BP_LCD_WF25_BPCLCD25, 1))
/*@}*/

/*!
 * @name Register LCD_WF25, field BPDLCD25[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF25_BPDLCD25 (3U)          /*!< Bit position for LCD_WF25_BPDLCD25. */
#define BM_LCD_WF25_BPDLCD25 (0x08U)       /*!< Bit mask for LCD_WF25_BPDLCD25. */
#define BS_LCD_WF25_BPDLCD25 (1U)          /*!< Bit field size in bits for LCD_WF25_BPDLCD25. */

/*! @brief Read current value of the LCD_WF25_BPDLCD25 field. */
#define BR_LCD_WF25_BPDLCD25(x) (BME_UBFX8(HW_LCD_WF25_ADDR(x), BP_LCD_WF25_BPDLCD25, BS_LCD_WF25_BPDLCD25))

/*! @brief Format value for bitfield LCD_WF25_BPDLCD25. */
#define BF_LCD_WF25_BPDLCD25(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF25_BPDLCD25) & BM_LCD_WF25_BPDLCD25)

/*! @brief Set the BPDLCD25 field to a new value. */
#define BW_LCD_WF25_BPDLCD25(x, v) (BME_BFI8(HW_LCD_WF25_ADDR(x), ((uint8_t)(v) << BP_LCD_WF25_BPDLCD25), BP_LCD_WF25_BPDLCD25, 1))
/*@}*/

/*!
 * @name Register LCD_WF25, field BPELCD25[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF25_BPELCD25 (4U)          /*!< Bit position for LCD_WF25_BPELCD25. */
#define BM_LCD_WF25_BPELCD25 (0x10U)       /*!< Bit mask for LCD_WF25_BPELCD25. */
#define BS_LCD_WF25_BPELCD25 (1U)          /*!< Bit field size in bits for LCD_WF25_BPELCD25. */

/*! @brief Read current value of the LCD_WF25_BPELCD25 field. */
#define BR_LCD_WF25_BPELCD25(x) (BME_UBFX8(HW_LCD_WF25_ADDR(x), BP_LCD_WF25_BPELCD25, BS_LCD_WF25_BPELCD25))

/*! @brief Format value for bitfield LCD_WF25_BPELCD25. */
#define BF_LCD_WF25_BPELCD25(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF25_BPELCD25) & BM_LCD_WF25_BPELCD25)

/*! @brief Set the BPELCD25 field to a new value. */
#define BW_LCD_WF25_BPELCD25(x, v) (BME_BFI8(HW_LCD_WF25_ADDR(x), ((uint8_t)(v) << BP_LCD_WF25_BPELCD25), BP_LCD_WF25_BPELCD25, 1))
/*@}*/

/*!
 * @name Register LCD_WF25, field BPFLCD25[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF25_BPFLCD25 (5U)          /*!< Bit position for LCD_WF25_BPFLCD25. */
#define BM_LCD_WF25_BPFLCD25 (0x20U)       /*!< Bit mask for LCD_WF25_BPFLCD25. */
#define BS_LCD_WF25_BPFLCD25 (1U)          /*!< Bit field size in bits for LCD_WF25_BPFLCD25. */

/*! @brief Read current value of the LCD_WF25_BPFLCD25 field. */
#define BR_LCD_WF25_BPFLCD25(x) (BME_UBFX8(HW_LCD_WF25_ADDR(x), BP_LCD_WF25_BPFLCD25, BS_LCD_WF25_BPFLCD25))

/*! @brief Format value for bitfield LCD_WF25_BPFLCD25. */
#define BF_LCD_WF25_BPFLCD25(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF25_BPFLCD25) & BM_LCD_WF25_BPFLCD25)

/*! @brief Set the BPFLCD25 field to a new value. */
#define BW_LCD_WF25_BPFLCD25(x, v) (BME_BFI8(HW_LCD_WF25_ADDR(x), ((uint8_t)(v) << BP_LCD_WF25_BPFLCD25), BP_LCD_WF25_BPFLCD25, 1))
/*@}*/

/*!
 * @name Register LCD_WF25, field BPGLCD25[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF25_BPGLCD25 (6U)          /*!< Bit position for LCD_WF25_BPGLCD25. */
#define BM_LCD_WF25_BPGLCD25 (0x40U)       /*!< Bit mask for LCD_WF25_BPGLCD25. */
#define BS_LCD_WF25_BPGLCD25 (1U)          /*!< Bit field size in bits for LCD_WF25_BPGLCD25. */

/*! @brief Read current value of the LCD_WF25_BPGLCD25 field. */
#define BR_LCD_WF25_BPGLCD25(x) (BME_UBFX8(HW_LCD_WF25_ADDR(x), BP_LCD_WF25_BPGLCD25, BS_LCD_WF25_BPGLCD25))

/*! @brief Format value for bitfield LCD_WF25_BPGLCD25. */
#define BF_LCD_WF25_BPGLCD25(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF25_BPGLCD25) & BM_LCD_WF25_BPGLCD25)

/*! @brief Set the BPGLCD25 field to a new value. */
#define BW_LCD_WF25_BPGLCD25(x, v) (BME_BFI8(HW_LCD_WF25_ADDR(x), ((uint8_t)(v) << BP_LCD_WF25_BPGLCD25), BP_LCD_WF25_BPGLCD25, 1))
/*@}*/

/*!
 * @name Register LCD_WF25, field BPHLCD25[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF25_BPHLCD25 (7U)          /*!< Bit position for LCD_WF25_BPHLCD25. */
#define BM_LCD_WF25_BPHLCD25 (0x80U)       /*!< Bit mask for LCD_WF25_BPHLCD25. */
#define BS_LCD_WF25_BPHLCD25 (1U)          /*!< Bit field size in bits for LCD_WF25_BPHLCD25. */

/*! @brief Read current value of the LCD_WF25_BPHLCD25 field. */
#define BR_LCD_WF25_BPHLCD25(x) (BME_UBFX8(HW_LCD_WF25_ADDR(x), BP_LCD_WF25_BPHLCD25, BS_LCD_WF25_BPHLCD25))

/*! @brief Format value for bitfield LCD_WF25_BPHLCD25. */
#define BF_LCD_WF25_BPHLCD25(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF25_BPHLCD25) & BM_LCD_WF25_BPHLCD25)

/*! @brief Set the BPHLCD25 field to a new value. */
#define BW_LCD_WF25_BPHLCD25(x, v) (BME_BFI8(HW_LCD_WF25_ADDR(x), ((uint8_t)(v) << BP_LCD_WF25_BPHLCD25), BP_LCD_WF25_BPHLCD25, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF26 - LCD Waveform Register 26.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF26 - LCD Waveform Register 26. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf26
{
    uint8_t U;
    struct _hw_lcd_wf26_bitfields
    {
        uint8_t BPALCD26 : 1;          /*!< [0]  */
        uint8_t BPBLCD26 : 1;          /*!< [1]  */
        uint8_t BPCLCD26 : 1;          /*!< [2]  */
        uint8_t BPDLCD26 : 1;          /*!< [3]  */
        uint8_t BPELCD26 : 1;          /*!< [4]  */
        uint8_t BPFLCD26 : 1;          /*!< [5]  */
        uint8_t BPGLCD26 : 1;          /*!< [6]  */
        uint8_t BPHLCD26 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf26_t;

/*!
 * @name Constants and macros for entire LCD_WF26 register
 */
/*@{*/
#define HW_LCD_WF26_ADDR(x)      ((x) + 0x3AU)

#define HW_LCD_WF26(x)           (*(__IO hw_lcd_wf26_t *) HW_LCD_WF26_ADDR(x))
#define HW_LCD_WF26_RD(x)        (HW_LCD_WF26(x).U)
#define HW_LCD_WF26_WR(x, v)     (HW_LCD_WF26(x).U = (v))
#define HW_LCD_WF26_SET(x, v)    (BME_OR8(HW_LCD_WF26_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF26_CLR(x, v)    (BME_AND8(HW_LCD_WF26_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF26_TOG(x, v)    (BME_XOR8(HW_LCD_WF26_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF26 bitfields
 */

/*!
 * @name Register LCD_WF26, field BPALCD26[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF26_BPALCD26 (0U)          /*!< Bit position for LCD_WF26_BPALCD26. */
#define BM_LCD_WF26_BPALCD26 (0x01U)       /*!< Bit mask for LCD_WF26_BPALCD26. */
#define BS_LCD_WF26_BPALCD26 (1U)          /*!< Bit field size in bits for LCD_WF26_BPALCD26. */

/*! @brief Read current value of the LCD_WF26_BPALCD26 field. */
#define BR_LCD_WF26_BPALCD26(x) (BME_UBFX8(HW_LCD_WF26_ADDR(x), BP_LCD_WF26_BPALCD26, BS_LCD_WF26_BPALCD26))

/*! @brief Format value for bitfield LCD_WF26_BPALCD26. */
#define BF_LCD_WF26_BPALCD26(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF26_BPALCD26) & BM_LCD_WF26_BPALCD26)

/*! @brief Set the BPALCD26 field to a new value. */
#define BW_LCD_WF26_BPALCD26(x, v) (BME_BFI8(HW_LCD_WF26_ADDR(x), ((uint8_t)(v) << BP_LCD_WF26_BPALCD26), BP_LCD_WF26_BPALCD26, 1))
/*@}*/

/*!
 * @name Register LCD_WF26, field BPBLCD26[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF26_BPBLCD26 (1U)          /*!< Bit position for LCD_WF26_BPBLCD26. */
#define BM_LCD_WF26_BPBLCD26 (0x02U)       /*!< Bit mask for LCD_WF26_BPBLCD26. */
#define BS_LCD_WF26_BPBLCD26 (1U)          /*!< Bit field size in bits for LCD_WF26_BPBLCD26. */

/*! @brief Read current value of the LCD_WF26_BPBLCD26 field. */
#define BR_LCD_WF26_BPBLCD26(x) (BME_UBFX8(HW_LCD_WF26_ADDR(x), BP_LCD_WF26_BPBLCD26, BS_LCD_WF26_BPBLCD26))

/*! @brief Format value for bitfield LCD_WF26_BPBLCD26. */
#define BF_LCD_WF26_BPBLCD26(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF26_BPBLCD26) & BM_LCD_WF26_BPBLCD26)

/*! @brief Set the BPBLCD26 field to a new value. */
#define BW_LCD_WF26_BPBLCD26(x, v) (BME_BFI8(HW_LCD_WF26_ADDR(x), ((uint8_t)(v) << BP_LCD_WF26_BPBLCD26), BP_LCD_WF26_BPBLCD26, 1))
/*@}*/

/*!
 * @name Register LCD_WF26, field BPCLCD26[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF26_BPCLCD26 (2U)          /*!< Bit position for LCD_WF26_BPCLCD26. */
#define BM_LCD_WF26_BPCLCD26 (0x04U)       /*!< Bit mask for LCD_WF26_BPCLCD26. */
#define BS_LCD_WF26_BPCLCD26 (1U)          /*!< Bit field size in bits for LCD_WF26_BPCLCD26. */

/*! @brief Read current value of the LCD_WF26_BPCLCD26 field. */
#define BR_LCD_WF26_BPCLCD26(x) (BME_UBFX8(HW_LCD_WF26_ADDR(x), BP_LCD_WF26_BPCLCD26, BS_LCD_WF26_BPCLCD26))

/*! @brief Format value for bitfield LCD_WF26_BPCLCD26. */
#define BF_LCD_WF26_BPCLCD26(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF26_BPCLCD26) & BM_LCD_WF26_BPCLCD26)

/*! @brief Set the BPCLCD26 field to a new value. */
#define BW_LCD_WF26_BPCLCD26(x, v) (BME_BFI8(HW_LCD_WF26_ADDR(x), ((uint8_t)(v) << BP_LCD_WF26_BPCLCD26), BP_LCD_WF26_BPCLCD26, 1))
/*@}*/

/*!
 * @name Register LCD_WF26, field BPDLCD26[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF26_BPDLCD26 (3U)          /*!< Bit position for LCD_WF26_BPDLCD26. */
#define BM_LCD_WF26_BPDLCD26 (0x08U)       /*!< Bit mask for LCD_WF26_BPDLCD26. */
#define BS_LCD_WF26_BPDLCD26 (1U)          /*!< Bit field size in bits for LCD_WF26_BPDLCD26. */

/*! @brief Read current value of the LCD_WF26_BPDLCD26 field. */
#define BR_LCD_WF26_BPDLCD26(x) (BME_UBFX8(HW_LCD_WF26_ADDR(x), BP_LCD_WF26_BPDLCD26, BS_LCD_WF26_BPDLCD26))

/*! @brief Format value for bitfield LCD_WF26_BPDLCD26. */
#define BF_LCD_WF26_BPDLCD26(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF26_BPDLCD26) & BM_LCD_WF26_BPDLCD26)

/*! @brief Set the BPDLCD26 field to a new value. */
#define BW_LCD_WF26_BPDLCD26(x, v) (BME_BFI8(HW_LCD_WF26_ADDR(x), ((uint8_t)(v) << BP_LCD_WF26_BPDLCD26), BP_LCD_WF26_BPDLCD26, 1))
/*@}*/

/*!
 * @name Register LCD_WF26, field BPELCD26[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF26_BPELCD26 (4U)          /*!< Bit position for LCD_WF26_BPELCD26. */
#define BM_LCD_WF26_BPELCD26 (0x10U)       /*!< Bit mask for LCD_WF26_BPELCD26. */
#define BS_LCD_WF26_BPELCD26 (1U)          /*!< Bit field size in bits for LCD_WF26_BPELCD26. */

/*! @brief Read current value of the LCD_WF26_BPELCD26 field. */
#define BR_LCD_WF26_BPELCD26(x) (BME_UBFX8(HW_LCD_WF26_ADDR(x), BP_LCD_WF26_BPELCD26, BS_LCD_WF26_BPELCD26))

/*! @brief Format value for bitfield LCD_WF26_BPELCD26. */
#define BF_LCD_WF26_BPELCD26(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF26_BPELCD26) & BM_LCD_WF26_BPELCD26)

/*! @brief Set the BPELCD26 field to a new value. */
#define BW_LCD_WF26_BPELCD26(x, v) (BME_BFI8(HW_LCD_WF26_ADDR(x), ((uint8_t)(v) << BP_LCD_WF26_BPELCD26), BP_LCD_WF26_BPELCD26, 1))
/*@}*/

/*!
 * @name Register LCD_WF26, field BPFLCD26[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF26_BPFLCD26 (5U)          /*!< Bit position for LCD_WF26_BPFLCD26. */
#define BM_LCD_WF26_BPFLCD26 (0x20U)       /*!< Bit mask for LCD_WF26_BPFLCD26. */
#define BS_LCD_WF26_BPFLCD26 (1U)          /*!< Bit field size in bits for LCD_WF26_BPFLCD26. */

/*! @brief Read current value of the LCD_WF26_BPFLCD26 field. */
#define BR_LCD_WF26_BPFLCD26(x) (BME_UBFX8(HW_LCD_WF26_ADDR(x), BP_LCD_WF26_BPFLCD26, BS_LCD_WF26_BPFLCD26))

/*! @brief Format value for bitfield LCD_WF26_BPFLCD26. */
#define BF_LCD_WF26_BPFLCD26(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF26_BPFLCD26) & BM_LCD_WF26_BPFLCD26)

/*! @brief Set the BPFLCD26 field to a new value. */
#define BW_LCD_WF26_BPFLCD26(x, v) (BME_BFI8(HW_LCD_WF26_ADDR(x), ((uint8_t)(v) << BP_LCD_WF26_BPFLCD26), BP_LCD_WF26_BPFLCD26, 1))
/*@}*/

/*!
 * @name Register LCD_WF26, field BPGLCD26[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF26_BPGLCD26 (6U)          /*!< Bit position for LCD_WF26_BPGLCD26. */
#define BM_LCD_WF26_BPGLCD26 (0x40U)       /*!< Bit mask for LCD_WF26_BPGLCD26. */
#define BS_LCD_WF26_BPGLCD26 (1U)          /*!< Bit field size in bits for LCD_WF26_BPGLCD26. */

/*! @brief Read current value of the LCD_WF26_BPGLCD26 field. */
#define BR_LCD_WF26_BPGLCD26(x) (BME_UBFX8(HW_LCD_WF26_ADDR(x), BP_LCD_WF26_BPGLCD26, BS_LCD_WF26_BPGLCD26))

/*! @brief Format value for bitfield LCD_WF26_BPGLCD26. */
#define BF_LCD_WF26_BPGLCD26(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF26_BPGLCD26) & BM_LCD_WF26_BPGLCD26)

/*! @brief Set the BPGLCD26 field to a new value. */
#define BW_LCD_WF26_BPGLCD26(x, v) (BME_BFI8(HW_LCD_WF26_ADDR(x), ((uint8_t)(v) << BP_LCD_WF26_BPGLCD26), BP_LCD_WF26_BPGLCD26, 1))
/*@}*/

/*!
 * @name Register LCD_WF26, field BPHLCD26[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF26_BPHLCD26 (7U)          /*!< Bit position for LCD_WF26_BPHLCD26. */
#define BM_LCD_WF26_BPHLCD26 (0x80U)       /*!< Bit mask for LCD_WF26_BPHLCD26. */
#define BS_LCD_WF26_BPHLCD26 (1U)          /*!< Bit field size in bits for LCD_WF26_BPHLCD26. */

/*! @brief Read current value of the LCD_WF26_BPHLCD26 field. */
#define BR_LCD_WF26_BPHLCD26(x) (BME_UBFX8(HW_LCD_WF26_ADDR(x), BP_LCD_WF26_BPHLCD26, BS_LCD_WF26_BPHLCD26))

/*! @brief Format value for bitfield LCD_WF26_BPHLCD26. */
#define BF_LCD_WF26_BPHLCD26(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF26_BPHLCD26) & BM_LCD_WF26_BPHLCD26)

/*! @brief Set the BPHLCD26 field to a new value. */
#define BW_LCD_WF26_BPHLCD26(x, v) (BME_BFI8(HW_LCD_WF26_ADDR(x), ((uint8_t)(v) << BP_LCD_WF26_BPHLCD26), BP_LCD_WF26_BPHLCD26, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF27 - LCD Waveform Register 27.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF27 - LCD Waveform Register 27. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf27
{
    uint8_t U;
    struct _hw_lcd_wf27_bitfields
    {
        uint8_t BPALCD27 : 1;          /*!< [0]  */
        uint8_t BPBLCD27 : 1;          /*!< [1]  */
        uint8_t BPCLCD27 : 1;          /*!< [2]  */
        uint8_t BPDLCD27 : 1;          /*!< [3]  */
        uint8_t BPELCD27 : 1;          /*!< [4]  */
        uint8_t BPFLCD27 : 1;          /*!< [5]  */
        uint8_t BPGLCD27 : 1;          /*!< [6]  */
        uint8_t BPHLCD27 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf27_t;

/*!
 * @name Constants and macros for entire LCD_WF27 register
 */
/*@{*/
#define HW_LCD_WF27_ADDR(x)      ((x) + 0x3BU)

#define HW_LCD_WF27(x)           (*(__IO hw_lcd_wf27_t *) HW_LCD_WF27_ADDR(x))
#define HW_LCD_WF27_RD(x)        (HW_LCD_WF27(x).U)
#define HW_LCD_WF27_WR(x, v)     (HW_LCD_WF27(x).U = (v))
#define HW_LCD_WF27_SET(x, v)    (BME_OR8(HW_LCD_WF27_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF27_CLR(x, v)    (BME_AND8(HW_LCD_WF27_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF27_TOG(x, v)    (BME_XOR8(HW_LCD_WF27_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF27 bitfields
 */

/*!
 * @name Register LCD_WF27, field BPALCD27[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF27_BPALCD27 (0U)          /*!< Bit position for LCD_WF27_BPALCD27. */
#define BM_LCD_WF27_BPALCD27 (0x01U)       /*!< Bit mask for LCD_WF27_BPALCD27. */
#define BS_LCD_WF27_BPALCD27 (1U)          /*!< Bit field size in bits for LCD_WF27_BPALCD27. */

/*! @brief Read current value of the LCD_WF27_BPALCD27 field. */
#define BR_LCD_WF27_BPALCD27(x) (BME_UBFX8(HW_LCD_WF27_ADDR(x), BP_LCD_WF27_BPALCD27, BS_LCD_WF27_BPALCD27))

/*! @brief Format value for bitfield LCD_WF27_BPALCD27. */
#define BF_LCD_WF27_BPALCD27(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF27_BPALCD27) & BM_LCD_WF27_BPALCD27)

/*! @brief Set the BPALCD27 field to a new value. */
#define BW_LCD_WF27_BPALCD27(x, v) (BME_BFI8(HW_LCD_WF27_ADDR(x), ((uint8_t)(v) << BP_LCD_WF27_BPALCD27), BP_LCD_WF27_BPALCD27, 1))
/*@}*/

/*!
 * @name Register LCD_WF27, field BPBLCD27[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF27_BPBLCD27 (1U)          /*!< Bit position for LCD_WF27_BPBLCD27. */
#define BM_LCD_WF27_BPBLCD27 (0x02U)       /*!< Bit mask for LCD_WF27_BPBLCD27. */
#define BS_LCD_WF27_BPBLCD27 (1U)          /*!< Bit field size in bits for LCD_WF27_BPBLCD27. */

/*! @brief Read current value of the LCD_WF27_BPBLCD27 field. */
#define BR_LCD_WF27_BPBLCD27(x) (BME_UBFX8(HW_LCD_WF27_ADDR(x), BP_LCD_WF27_BPBLCD27, BS_LCD_WF27_BPBLCD27))

/*! @brief Format value for bitfield LCD_WF27_BPBLCD27. */
#define BF_LCD_WF27_BPBLCD27(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF27_BPBLCD27) & BM_LCD_WF27_BPBLCD27)

/*! @brief Set the BPBLCD27 field to a new value. */
#define BW_LCD_WF27_BPBLCD27(x, v) (BME_BFI8(HW_LCD_WF27_ADDR(x), ((uint8_t)(v) << BP_LCD_WF27_BPBLCD27), BP_LCD_WF27_BPBLCD27, 1))
/*@}*/

/*!
 * @name Register LCD_WF27, field BPCLCD27[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF27_BPCLCD27 (2U)          /*!< Bit position for LCD_WF27_BPCLCD27. */
#define BM_LCD_WF27_BPCLCD27 (0x04U)       /*!< Bit mask for LCD_WF27_BPCLCD27. */
#define BS_LCD_WF27_BPCLCD27 (1U)          /*!< Bit field size in bits for LCD_WF27_BPCLCD27. */

/*! @brief Read current value of the LCD_WF27_BPCLCD27 field. */
#define BR_LCD_WF27_BPCLCD27(x) (BME_UBFX8(HW_LCD_WF27_ADDR(x), BP_LCD_WF27_BPCLCD27, BS_LCD_WF27_BPCLCD27))

/*! @brief Format value for bitfield LCD_WF27_BPCLCD27. */
#define BF_LCD_WF27_BPCLCD27(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF27_BPCLCD27) & BM_LCD_WF27_BPCLCD27)

/*! @brief Set the BPCLCD27 field to a new value. */
#define BW_LCD_WF27_BPCLCD27(x, v) (BME_BFI8(HW_LCD_WF27_ADDR(x), ((uint8_t)(v) << BP_LCD_WF27_BPCLCD27), BP_LCD_WF27_BPCLCD27, 1))
/*@}*/

/*!
 * @name Register LCD_WF27, field BPDLCD27[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF27_BPDLCD27 (3U)          /*!< Bit position for LCD_WF27_BPDLCD27. */
#define BM_LCD_WF27_BPDLCD27 (0x08U)       /*!< Bit mask for LCD_WF27_BPDLCD27. */
#define BS_LCD_WF27_BPDLCD27 (1U)          /*!< Bit field size in bits for LCD_WF27_BPDLCD27. */

/*! @brief Read current value of the LCD_WF27_BPDLCD27 field. */
#define BR_LCD_WF27_BPDLCD27(x) (BME_UBFX8(HW_LCD_WF27_ADDR(x), BP_LCD_WF27_BPDLCD27, BS_LCD_WF27_BPDLCD27))

/*! @brief Format value for bitfield LCD_WF27_BPDLCD27. */
#define BF_LCD_WF27_BPDLCD27(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF27_BPDLCD27) & BM_LCD_WF27_BPDLCD27)

/*! @brief Set the BPDLCD27 field to a new value. */
#define BW_LCD_WF27_BPDLCD27(x, v) (BME_BFI8(HW_LCD_WF27_ADDR(x), ((uint8_t)(v) << BP_LCD_WF27_BPDLCD27), BP_LCD_WF27_BPDLCD27, 1))
/*@}*/

/*!
 * @name Register LCD_WF27, field BPELCD27[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF27_BPELCD27 (4U)          /*!< Bit position for LCD_WF27_BPELCD27. */
#define BM_LCD_WF27_BPELCD27 (0x10U)       /*!< Bit mask for LCD_WF27_BPELCD27. */
#define BS_LCD_WF27_BPELCD27 (1U)          /*!< Bit field size in bits for LCD_WF27_BPELCD27. */

/*! @brief Read current value of the LCD_WF27_BPELCD27 field. */
#define BR_LCD_WF27_BPELCD27(x) (BME_UBFX8(HW_LCD_WF27_ADDR(x), BP_LCD_WF27_BPELCD27, BS_LCD_WF27_BPELCD27))

/*! @brief Format value for bitfield LCD_WF27_BPELCD27. */
#define BF_LCD_WF27_BPELCD27(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF27_BPELCD27) & BM_LCD_WF27_BPELCD27)

/*! @brief Set the BPELCD27 field to a new value. */
#define BW_LCD_WF27_BPELCD27(x, v) (BME_BFI8(HW_LCD_WF27_ADDR(x), ((uint8_t)(v) << BP_LCD_WF27_BPELCD27), BP_LCD_WF27_BPELCD27, 1))
/*@}*/

/*!
 * @name Register LCD_WF27, field BPFLCD27[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF27_BPFLCD27 (5U)          /*!< Bit position for LCD_WF27_BPFLCD27. */
#define BM_LCD_WF27_BPFLCD27 (0x20U)       /*!< Bit mask for LCD_WF27_BPFLCD27. */
#define BS_LCD_WF27_BPFLCD27 (1U)          /*!< Bit field size in bits for LCD_WF27_BPFLCD27. */

/*! @brief Read current value of the LCD_WF27_BPFLCD27 field. */
#define BR_LCD_WF27_BPFLCD27(x) (BME_UBFX8(HW_LCD_WF27_ADDR(x), BP_LCD_WF27_BPFLCD27, BS_LCD_WF27_BPFLCD27))

/*! @brief Format value for bitfield LCD_WF27_BPFLCD27. */
#define BF_LCD_WF27_BPFLCD27(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF27_BPFLCD27) & BM_LCD_WF27_BPFLCD27)

/*! @brief Set the BPFLCD27 field to a new value. */
#define BW_LCD_WF27_BPFLCD27(x, v) (BME_BFI8(HW_LCD_WF27_ADDR(x), ((uint8_t)(v) << BP_LCD_WF27_BPFLCD27), BP_LCD_WF27_BPFLCD27, 1))
/*@}*/

/*!
 * @name Register LCD_WF27, field BPGLCD27[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF27_BPGLCD27 (6U)          /*!< Bit position for LCD_WF27_BPGLCD27. */
#define BM_LCD_WF27_BPGLCD27 (0x40U)       /*!< Bit mask for LCD_WF27_BPGLCD27. */
#define BS_LCD_WF27_BPGLCD27 (1U)          /*!< Bit field size in bits for LCD_WF27_BPGLCD27. */

/*! @brief Read current value of the LCD_WF27_BPGLCD27 field. */
#define BR_LCD_WF27_BPGLCD27(x) (BME_UBFX8(HW_LCD_WF27_ADDR(x), BP_LCD_WF27_BPGLCD27, BS_LCD_WF27_BPGLCD27))

/*! @brief Format value for bitfield LCD_WF27_BPGLCD27. */
#define BF_LCD_WF27_BPGLCD27(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF27_BPGLCD27) & BM_LCD_WF27_BPGLCD27)

/*! @brief Set the BPGLCD27 field to a new value. */
#define BW_LCD_WF27_BPGLCD27(x, v) (BME_BFI8(HW_LCD_WF27_ADDR(x), ((uint8_t)(v) << BP_LCD_WF27_BPGLCD27), BP_LCD_WF27_BPGLCD27, 1))
/*@}*/

/*!
 * @name Register LCD_WF27, field BPHLCD27[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF27_BPHLCD27 (7U)          /*!< Bit position for LCD_WF27_BPHLCD27. */
#define BM_LCD_WF27_BPHLCD27 (0x80U)       /*!< Bit mask for LCD_WF27_BPHLCD27. */
#define BS_LCD_WF27_BPHLCD27 (1U)          /*!< Bit field size in bits for LCD_WF27_BPHLCD27. */

/*! @brief Read current value of the LCD_WF27_BPHLCD27 field. */
#define BR_LCD_WF27_BPHLCD27(x) (BME_UBFX8(HW_LCD_WF27_ADDR(x), BP_LCD_WF27_BPHLCD27, BS_LCD_WF27_BPHLCD27))

/*! @brief Format value for bitfield LCD_WF27_BPHLCD27. */
#define BF_LCD_WF27_BPHLCD27(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF27_BPHLCD27) & BM_LCD_WF27_BPHLCD27)

/*! @brief Set the BPHLCD27 field to a new value. */
#define BW_LCD_WF27_BPHLCD27(x, v) (BME_BFI8(HW_LCD_WF27_ADDR(x), ((uint8_t)(v) << BP_LCD_WF27_BPHLCD27), BP_LCD_WF27_BPHLCD27, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF28 - LCD Waveform Register 28.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF28 - LCD Waveform Register 28. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf28
{
    uint8_t U;
    struct _hw_lcd_wf28_bitfields
    {
        uint8_t BPALCD28 : 1;          /*!< [0]  */
        uint8_t BPBLCD28 : 1;          /*!< [1]  */
        uint8_t BPCLCD28 : 1;          /*!< [2]  */
        uint8_t BPDLCD28 : 1;          /*!< [3]  */
        uint8_t BPELCD28 : 1;          /*!< [4]  */
        uint8_t BPFLCD28 : 1;          /*!< [5]  */
        uint8_t BPGLCD28 : 1;          /*!< [6]  */
        uint8_t BPHLCD28 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf28_t;

/*!
 * @name Constants and macros for entire LCD_WF28 register
 */
/*@{*/
#define HW_LCD_WF28_ADDR(x)      ((x) + 0x3CU)

#define HW_LCD_WF28(x)           (*(__IO hw_lcd_wf28_t *) HW_LCD_WF28_ADDR(x))
#define HW_LCD_WF28_RD(x)        (HW_LCD_WF28(x).U)
#define HW_LCD_WF28_WR(x, v)     (HW_LCD_WF28(x).U = (v))
#define HW_LCD_WF28_SET(x, v)    (BME_OR8(HW_LCD_WF28_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF28_CLR(x, v)    (BME_AND8(HW_LCD_WF28_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF28_TOG(x, v)    (BME_XOR8(HW_LCD_WF28_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF28 bitfields
 */

/*!
 * @name Register LCD_WF28, field BPALCD28[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF28_BPALCD28 (0U)          /*!< Bit position for LCD_WF28_BPALCD28. */
#define BM_LCD_WF28_BPALCD28 (0x01U)       /*!< Bit mask for LCD_WF28_BPALCD28. */
#define BS_LCD_WF28_BPALCD28 (1U)          /*!< Bit field size in bits for LCD_WF28_BPALCD28. */

/*! @brief Read current value of the LCD_WF28_BPALCD28 field. */
#define BR_LCD_WF28_BPALCD28(x) (BME_UBFX8(HW_LCD_WF28_ADDR(x), BP_LCD_WF28_BPALCD28, BS_LCD_WF28_BPALCD28))

/*! @brief Format value for bitfield LCD_WF28_BPALCD28. */
#define BF_LCD_WF28_BPALCD28(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF28_BPALCD28) & BM_LCD_WF28_BPALCD28)

/*! @brief Set the BPALCD28 field to a new value. */
#define BW_LCD_WF28_BPALCD28(x, v) (BME_BFI8(HW_LCD_WF28_ADDR(x), ((uint8_t)(v) << BP_LCD_WF28_BPALCD28), BP_LCD_WF28_BPALCD28, 1))
/*@}*/

/*!
 * @name Register LCD_WF28, field BPBLCD28[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF28_BPBLCD28 (1U)          /*!< Bit position for LCD_WF28_BPBLCD28. */
#define BM_LCD_WF28_BPBLCD28 (0x02U)       /*!< Bit mask for LCD_WF28_BPBLCD28. */
#define BS_LCD_WF28_BPBLCD28 (1U)          /*!< Bit field size in bits for LCD_WF28_BPBLCD28. */

/*! @brief Read current value of the LCD_WF28_BPBLCD28 field. */
#define BR_LCD_WF28_BPBLCD28(x) (BME_UBFX8(HW_LCD_WF28_ADDR(x), BP_LCD_WF28_BPBLCD28, BS_LCD_WF28_BPBLCD28))

/*! @brief Format value for bitfield LCD_WF28_BPBLCD28. */
#define BF_LCD_WF28_BPBLCD28(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF28_BPBLCD28) & BM_LCD_WF28_BPBLCD28)

/*! @brief Set the BPBLCD28 field to a new value. */
#define BW_LCD_WF28_BPBLCD28(x, v) (BME_BFI8(HW_LCD_WF28_ADDR(x), ((uint8_t)(v) << BP_LCD_WF28_BPBLCD28), BP_LCD_WF28_BPBLCD28, 1))
/*@}*/

/*!
 * @name Register LCD_WF28, field BPCLCD28[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF28_BPCLCD28 (2U)          /*!< Bit position for LCD_WF28_BPCLCD28. */
#define BM_LCD_WF28_BPCLCD28 (0x04U)       /*!< Bit mask for LCD_WF28_BPCLCD28. */
#define BS_LCD_WF28_BPCLCD28 (1U)          /*!< Bit field size in bits for LCD_WF28_BPCLCD28. */

/*! @brief Read current value of the LCD_WF28_BPCLCD28 field. */
#define BR_LCD_WF28_BPCLCD28(x) (BME_UBFX8(HW_LCD_WF28_ADDR(x), BP_LCD_WF28_BPCLCD28, BS_LCD_WF28_BPCLCD28))

/*! @brief Format value for bitfield LCD_WF28_BPCLCD28. */
#define BF_LCD_WF28_BPCLCD28(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF28_BPCLCD28) & BM_LCD_WF28_BPCLCD28)

/*! @brief Set the BPCLCD28 field to a new value. */
#define BW_LCD_WF28_BPCLCD28(x, v) (BME_BFI8(HW_LCD_WF28_ADDR(x), ((uint8_t)(v) << BP_LCD_WF28_BPCLCD28), BP_LCD_WF28_BPCLCD28, 1))
/*@}*/

/*!
 * @name Register LCD_WF28, field BPDLCD28[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF28_BPDLCD28 (3U)          /*!< Bit position for LCD_WF28_BPDLCD28. */
#define BM_LCD_WF28_BPDLCD28 (0x08U)       /*!< Bit mask for LCD_WF28_BPDLCD28. */
#define BS_LCD_WF28_BPDLCD28 (1U)          /*!< Bit field size in bits for LCD_WF28_BPDLCD28. */

/*! @brief Read current value of the LCD_WF28_BPDLCD28 field. */
#define BR_LCD_WF28_BPDLCD28(x) (BME_UBFX8(HW_LCD_WF28_ADDR(x), BP_LCD_WF28_BPDLCD28, BS_LCD_WF28_BPDLCD28))

/*! @brief Format value for bitfield LCD_WF28_BPDLCD28. */
#define BF_LCD_WF28_BPDLCD28(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF28_BPDLCD28) & BM_LCD_WF28_BPDLCD28)

/*! @brief Set the BPDLCD28 field to a new value. */
#define BW_LCD_WF28_BPDLCD28(x, v) (BME_BFI8(HW_LCD_WF28_ADDR(x), ((uint8_t)(v) << BP_LCD_WF28_BPDLCD28), BP_LCD_WF28_BPDLCD28, 1))
/*@}*/

/*!
 * @name Register LCD_WF28, field BPELCD28[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF28_BPELCD28 (4U)          /*!< Bit position for LCD_WF28_BPELCD28. */
#define BM_LCD_WF28_BPELCD28 (0x10U)       /*!< Bit mask for LCD_WF28_BPELCD28. */
#define BS_LCD_WF28_BPELCD28 (1U)          /*!< Bit field size in bits for LCD_WF28_BPELCD28. */

/*! @brief Read current value of the LCD_WF28_BPELCD28 field. */
#define BR_LCD_WF28_BPELCD28(x) (BME_UBFX8(HW_LCD_WF28_ADDR(x), BP_LCD_WF28_BPELCD28, BS_LCD_WF28_BPELCD28))

/*! @brief Format value for bitfield LCD_WF28_BPELCD28. */
#define BF_LCD_WF28_BPELCD28(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF28_BPELCD28) & BM_LCD_WF28_BPELCD28)

/*! @brief Set the BPELCD28 field to a new value. */
#define BW_LCD_WF28_BPELCD28(x, v) (BME_BFI8(HW_LCD_WF28_ADDR(x), ((uint8_t)(v) << BP_LCD_WF28_BPELCD28), BP_LCD_WF28_BPELCD28, 1))
/*@}*/

/*!
 * @name Register LCD_WF28, field BPFLCD28[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF28_BPFLCD28 (5U)          /*!< Bit position for LCD_WF28_BPFLCD28. */
#define BM_LCD_WF28_BPFLCD28 (0x20U)       /*!< Bit mask for LCD_WF28_BPFLCD28. */
#define BS_LCD_WF28_BPFLCD28 (1U)          /*!< Bit field size in bits for LCD_WF28_BPFLCD28. */

/*! @brief Read current value of the LCD_WF28_BPFLCD28 field. */
#define BR_LCD_WF28_BPFLCD28(x) (BME_UBFX8(HW_LCD_WF28_ADDR(x), BP_LCD_WF28_BPFLCD28, BS_LCD_WF28_BPFLCD28))

/*! @brief Format value for bitfield LCD_WF28_BPFLCD28. */
#define BF_LCD_WF28_BPFLCD28(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF28_BPFLCD28) & BM_LCD_WF28_BPFLCD28)

/*! @brief Set the BPFLCD28 field to a new value. */
#define BW_LCD_WF28_BPFLCD28(x, v) (BME_BFI8(HW_LCD_WF28_ADDR(x), ((uint8_t)(v) << BP_LCD_WF28_BPFLCD28), BP_LCD_WF28_BPFLCD28, 1))
/*@}*/

/*!
 * @name Register LCD_WF28, field BPGLCD28[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF28_BPGLCD28 (6U)          /*!< Bit position for LCD_WF28_BPGLCD28. */
#define BM_LCD_WF28_BPGLCD28 (0x40U)       /*!< Bit mask for LCD_WF28_BPGLCD28. */
#define BS_LCD_WF28_BPGLCD28 (1U)          /*!< Bit field size in bits for LCD_WF28_BPGLCD28. */

/*! @brief Read current value of the LCD_WF28_BPGLCD28 field. */
#define BR_LCD_WF28_BPGLCD28(x) (BME_UBFX8(HW_LCD_WF28_ADDR(x), BP_LCD_WF28_BPGLCD28, BS_LCD_WF28_BPGLCD28))

/*! @brief Format value for bitfield LCD_WF28_BPGLCD28. */
#define BF_LCD_WF28_BPGLCD28(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF28_BPGLCD28) & BM_LCD_WF28_BPGLCD28)

/*! @brief Set the BPGLCD28 field to a new value. */
#define BW_LCD_WF28_BPGLCD28(x, v) (BME_BFI8(HW_LCD_WF28_ADDR(x), ((uint8_t)(v) << BP_LCD_WF28_BPGLCD28), BP_LCD_WF28_BPGLCD28, 1))
/*@}*/

/*!
 * @name Register LCD_WF28, field BPHLCD28[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF28_BPHLCD28 (7U)          /*!< Bit position for LCD_WF28_BPHLCD28. */
#define BM_LCD_WF28_BPHLCD28 (0x80U)       /*!< Bit mask for LCD_WF28_BPHLCD28. */
#define BS_LCD_WF28_BPHLCD28 (1U)          /*!< Bit field size in bits for LCD_WF28_BPHLCD28. */

/*! @brief Read current value of the LCD_WF28_BPHLCD28 field. */
#define BR_LCD_WF28_BPHLCD28(x) (BME_UBFX8(HW_LCD_WF28_ADDR(x), BP_LCD_WF28_BPHLCD28, BS_LCD_WF28_BPHLCD28))

/*! @brief Format value for bitfield LCD_WF28_BPHLCD28. */
#define BF_LCD_WF28_BPHLCD28(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF28_BPHLCD28) & BM_LCD_WF28_BPHLCD28)

/*! @brief Set the BPHLCD28 field to a new value. */
#define BW_LCD_WF28_BPHLCD28(x, v) (BME_BFI8(HW_LCD_WF28_ADDR(x), ((uint8_t)(v) << BP_LCD_WF28_BPHLCD28), BP_LCD_WF28_BPHLCD28, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF29 - LCD Waveform Register 29.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF29 - LCD Waveform Register 29. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf29
{
    uint8_t U;
    struct _hw_lcd_wf29_bitfields
    {
        uint8_t BPALCD29 : 1;          /*!< [0]  */
        uint8_t BPBLCD29 : 1;          /*!< [1]  */
        uint8_t BPCLCD29 : 1;          /*!< [2]  */
        uint8_t BPDLCD29 : 1;          /*!< [3]  */
        uint8_t BPELCD29 : 1;          /*!< [4]  */
        uint8_t BPFLCD29 : 1;          /*!< [5]  */
        uint8_t BPGLCD29 : 1;          /*!< [6]  */
        uint8_t BPHLCD29 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf29_t;

/*!
 * @name Constants and macros for entire LCD_WF29 register
 */
/*@{*/
#define HW_LCD_WF29_ADDR(x)      ((x) + 0x3DU)

#define HW_LCD_WF29(x)           (*(__IO hw_lcd_wf29_t *) HW_LCD_WF29_ADDR(x))
#define HW_LCD_WF29_RD(x)        (HW_LCD_WF29(x).U)
#define HW_LCD_WF29_WR(x, v)     (HW_LCD_WF29(x).U = (v))
#define HW_LCD_WF29_SET(x, v)    (BME_OR8(HW_LCD_WF29_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF29_CLR(x, v)    (BME_AND8(HW_LCD_WF29_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF29_TOG(x, v)    (BME_XOR8(HW_LCD_WF29_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF29 bitfields
 */

/*!
 * @name Register LCD_WF29, field BPALCD29[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF29_BPALCD29 (0U)          /*!< Bit position for LCD_WF29_BPALCD29. */
#define BM_LCD_WF29_BPALCD29 (0x01U)       /*!< Bit mask for LCD_WF29_BPALCD29. */
#define BS_LCD_WF29_BPALCD29 (1U)          /*!< Bit field size in bits for LCD_WF29_BPALCD29. */

/*! @brief Read current value of the LCD_WF29_BPALCD29 field. */
#define BR_LCD_WF29_BPALCD29(x) (BME_UBFX8(HW_LCD_WF29_ADDR(x), BP_LCD_WF29_BPALCD29, BS_LCD_WF29_BPALCD29))

/*! @brief Format value for bitfield LCD_WF29_BPALCD29. */
#define BF_LCD_WF29_BPALCD29(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF29_BPALCD29) & BM_LCD_WF29_BPALCD29)

/*! @brief Set the BPALCD29 field to a new value. */
#define BW_LCD_WF29_BPALCD29(x, v) (BME_BFI8(HW_LCD_WF29_ADDR(x), ((uint8_t)(v) << BP_LCD_WF29_BPALCD29), BP_LCD_WF29_BPALCD29, 1))
/*@}*/

/*!
 * @name Register LCD_WF29, field BPBLCD29[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF29_BPBLCD29 (1U)          /*!< Bit position for LCD_WF29_BPBLCD29. */
#define BM_LCD_WF29_BPBLCD29 (0x02U)       /*!< Bit mask for LCD_WF29_BPBLCD29. */
#define BS_LCD_WF29_BPBLCD29 (1U)          /*!< Bit field size in bits for LCD_WF29_BPBLCD29. */

/*! @brief Read current value of the LCD_WF29_BPBLCD29 field. */
#define BR_LCD_WF29_BPBLCD29(x) (BME_UBFX8(HW_LCD_WF29_ADDR(x), BP_LCD_WF29_BPBLCD29, BS_LCD_WF29_BPBLCD29))

/*! @brief Format value for bitfield LCD_WF29_BPBLCD29. */
#define BF_LCD_WF29_BPBLCD29(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF29_BPBLCD29) & BM_LCD_WF29_BPBLCD29)

/*! @brief Set the BPBLCD29 field to a new value. */
#define BW_LCD_WF29_BPBLCD29(x, v) (BME_BFI8(HW_LCD_WF29_ADDR(x), ((uint8_t)(v) << BP_LCD_WF29_BPBLCD29), BP_LCD_WF29_BPBLCD29, 1))
/*@}*/

/*!
 * @name Register LCD_WF29, field BPCLCD29[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF29_BPCLCD29 (2U)          /*!< Bit position for LCD_WF29_BPCLCD29. */
#define BM_LCD_WF29_BPCLCD29 (0x04U)       /*!< Bit mask for LCD_WF29_BPCLCD29. */
#define BS_LCD_WF29_BPCLCD29 (1U)          /*!< Bit field size in bits for LCD_WF29_BPCLCD29. */

/*! @brief Read current value of the LCD_WF29_BPCLCD29 field. */
#define BR_LCD_WF29_BPCLCD29(x) (BME_UBFX8(HW_LCD_WF29_ADDR(x), BP_LCD_WF29_BPCLCD29, BS_LCD_WF29_BPCLCD29))

/*! @brief Format value for bitfield LCD_WF29_BPCLCD29. */
#define BF_LCD_WF29_BPCLCD29(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF29_BPCLCD29) & BM_LCD_WF29_BPCLCD29)

/*! @brief Set the BPCLCD29 field to a new value. */
#define BW_LCD_WF29_BPCLCD29(x, v) (BME_BFI8(HW_LCD_WF29_ADDR(x), ((uint8_t)(v) << BP_LCD_WF29_BPCLCD29), BP_LCD_WF29_BPCLCD29, 1))
/*@}*/

/*!
 * @name Register LCD_WF29, field BPDLCD29[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF29_BPDLCD29 (3U)          /*!< Bit position for LCD_WF29_BPDLCD29. */
#define BM_LCD_WF29_BPDLCD29 (0x08U)       /*!< Bit mask for LCD_WF29_BPDLCD29. */
#define BS_LCD_WF29_BPDLCD29 (1U)          /*!< Bit field size in bits for LCD_WF29_BPDLCD29. */

/*! @brief Read current value of the LCD_WF29_BPDLCD29 field. */
#define BR_LCD_WF29_BPDLCD29(x) (BME_UBFX8(HW_LCD_WF29_ADDR(x), BP_LCD_WF29_BPDLCD29, BS_LCD_WF29_BPDLCD29))

/*! @brief Format value for bitfield LCD_WF29_BPDLCD29. */
#define BF_LCD_WF29_BPDLCD29(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF29_BPDLCD29) & BM_LCD_WF29_BPDLCD29)

/*! @brief Set the BPDLCD29 field to a new value. */
#define BW_LCD_WF29_BPDLCD29(x, v) (BME_BFI8(HW_LCD_WF29_ADDR(x), ((uint8_t)(v) << BP_LCD_WF29_BPDLCD29), BP_LCD_WF29_BPDLCD29, 1))
/*@}*/

/*!
 * @name Register LCD_WF29, field BPELCD29[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF29_BPELCD29 (4U)          /*!< Bit position for LCD_WF29_BPELCD29. */
#define BM_LCD_WF29_BPELCD29 (0x10U)       /*!< Bit mask for LCD_WF29_BPELCD29. */
#define BS_LCD_WF29_BPELCD29 (1U)          /*!< Bit field size in bits for LCD_WF29_BPELCD29. */

/*! @brief Read current value of the LCD_WF29_BPELCD29 field. */
#define BR_LCD_WF29_BPELCD29(x) (BME_UBFX8(HW_LCD_WF29_ADDR(x), BP_LCD_WF29_BPELCD29, BS_LCD_WF29_BPELCD29))

/*! @brief Format value for bitfield LCD_WF29_BPELCD29. */
#define BF_LCD_WF29_BPELCD29(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF29_BPELCD29) & BM_LCD_WF29_BPELCD29)

/*! @brief Set the BPELCD29 field to a new value. */
#define BW_LCD_WF29_BPELCD29(x, v) (BME_BFI8(HW_LCD_WF29_ADDR(x), ((uint8_t)(v) << BP_LCD_WF29_BPELCD29), BP_LCD_WF29_BPELCD29, 1))
/*@}*/

/*!
 * @name Register LCD_WF29, field BPFLCD29[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF29_BPFLCD29 (5U)          /*!< Bit position for LCD_WF29_BPFLCD29. */
#define BM_LCD_WF29_BPFLCD29 (0x20U)       /*!< Bit mask for LCD_WF29_BPFLCD29. */
#define BS_LCD_WF29_BPFLCD29 (1U)          /*!< Bit field size in bits for LCD_WF29_BPFLCD29. */

/*! @brief Read current value of the LCD_WF29_BPFLCD29 field. */
#define BR_LCD_WF29_BPFLCD29(x) (BME_UBFX8(HW_LCD_WF29_ADDR(x), BP_LCD_WF29_BPFLCD29, BS_LCD_WF29_BPFLCD29))

/*! @brief Format value for bitfield LCD_WF29_BPFLCD29. */
#define BF_LCD_WF29_BPFLCD29(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF29_BPFLCD29) & BM_LCD_WF29_BPFLCD29)

/*! @brief Set the BPFLCD29 field to a new value. */
#define BW_LCD_WF29_BPFLCD29(x, v) (BME_BFI8(HW_LCD_WF29_ADDR(x), ((uint8_t)(v) << BP_LCD_WF29_BPFLCD29), BP_LCD_WF29_BPFLCD29, 1))
/*@}*/

/*!
 * @name Register LCD_WF29, field BPGLCD29[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF29_BPGLCD29 (6U)          /*!< Bit position for LCD_WF29_BPGLCD29. */
#define BM_LCD_WF29_BPGLCD29 (0x40U)       /*!< Bit mask for LCD_WF29_BPGLCD29. */
#define BS_LCD_WF29_BPGLCD29 (1U)          /*!< Bit field size in bits for LCD_WF29_BPGLCD29. */

/*! @brief Read current value of the LCD_WF29_BPGLCD29 field. */
#define BR_LCD_WF29_BPGLCD29(x) (BME_UBFX8(HW_LCD_WF29_ADDR(x), BP_LCD_WF29_BPGLCD29, BS_LCD_WF29_BPGLCD29))

/*! @brief Format value for bitfield LCD_WF29_BPGLCD29. */
#define BF_LCD_WF29_BPGLCD29(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF29_BPGLCD29) & BM_LCD_WF29_BPGLCD29)

/*! @brief Set the BPGLCD29 field to a new value. */
#define BW_LCD_WF29_BPGLCD29(x, v) (BME_BFI8(HW_LCD_WF29_ADDR(x), ((uint8_t)(v) << BP_LCD_WF29_BPGLCD29), BP_LCD_WF29_BPGLCD29, 1))
/*@}*/

/*!
 * @name Register LCD_WF29, field BPHLCD29[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF29_BPHLCD29 (7U)          /*!< Bit position for LCD_WF29_BPHLCD29. */
#define BM_LCD_WF29_BPHLCD29 (0x80U)       /*!< Bit mask for LCD_WF29_BPHLCD29. */
#define BS_LCD_WF29_BPHLCD29 (1U)          /*!< Bit field size in bits for LCD_WF29_BPHLCD29. */

/*! @brief Read current value of the LCD_WF29_BPHLCD29 field. */
#define BR_LCD_WF29_BPHLCD29(x) (BME_UBFX8(HW_LCD_WF29_ADDR(x), BP_LCD_WF29_BPHLCD29, BS_LCD_WF29_BPHLCD29))

/*! @brief Format value for bitfield LCD_WF29_BPHLCD29. */
#define BF_LCD_WF29_BPHLCD29(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF29_BPHLCD29) & BM_LCD_WF29_BPHLCD29)

/*! @brief Set the BPHLCD29 field to a new value. */
#define BW_LCD_WF29_BPHLCD29(x, v) (BME_BFI8(HW_LCD_WF29_ADDR(x), ((uint8_t)(v) << BP_LCD_WF29_BPHLCD29), BP_LCD_WF29_BPHLCD29, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF30 - LCD Waveform Register 30.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF30 - LCD Waveform Register 30. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf30
{
    uint8_t U;
    struct _hw_lcd_wf30_bitfields
    {
        uint8_t BPALCD30 : 1;          /*!< [0]  */
        uint8_t BPBLCD30 : 1;          /*!< [1]  */
        uint8_t BPCLCD30 : 1;          /*!< [2]  */
        uint8_t BPDLCD30 : 1;          /*!< [3]  */
        uint8_t BPELCD30 : 1;          /*!< [4]  */
        uint8_t BPFLCD30 : 1;          /*!< [5]  */
        uint8_t BPGLCD30 : 1;          /*!< [6]  */
        uint8_t BPHLCD30 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf30_t;

/*!
 * @name Constants and macros for entire LCD_WF30 register
 */
/*@{*/
#define HW_LCD_WF30_ADDR(x)      ((x) + 0x3EU)

#define HW_LCD_WF30(x)           (*(__IO hw_lcd_wf30_t *) HW_LCD_WF30_ADDR(x))
#define HW_LCD_WF30_RD(x)        (HW_LCD_WF30(x).U)
#define HW_LCD_WF30_WR(x, v)     (HW_LCD_WF30(x).U = (v))
#define HW_LCD_WF30_SET(x, v)    (BME_OR8(HW_LCD_WF30_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF30_CLR(x, v)    (BME_AND8(HW_LCD_WF30_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF30_TOG(x, v)    (BME_XOR8(HW_LCD_WF30_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF30 bitfields
 */

/*!
 * @name Register LCD_WF30, field BPALCD30[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF30_BPALCD30 (0U)          /*!< Bit position for LCD_WF30_BPALCD30. */
#define BM_LCD_WF30_BPALCD30 (0x01U)       /*!< Bit mask for LCD_WF30_BPALCD30. */
#define BS_LCD_WF30_BPALCD30 (1U)          /*!< Bit field size in bits for LCD_WF30_BPALCD30. */

/*! @brief Read current value of the LCD_WF30_BPALCD30 field. */
#define BR_LCD_WF30_BPALCD30(x) (BME_UBFX8(HW_LCD_WF30_ADDR(x), BP_LCD_WF30_BPALCD30, BS_LCD_WF30_BPALCD30))

/*! @brief Format value for bitfield LCD_WF30_BPALCD30. */
#define BF_LCD_WF30_BPALCD30(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF30_BPALCD30) & BM_LCD_WF30_BPALCD30)

/*! @brief Set the BPALCD30 field to a new value. */
#define BW_LCD_WF30_BPALCD30(x, v) (BME_BFI8(HW_LCD_WF30_ADDR(x), ((uint8_t)(v) << BP_LCD_WF30_BPALCD30), BP_LCD_WF30_BPALCD30, 1))
/*@}*/

/*!
 * @name Register LCD_WF30, field BPBLCD30[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF30_BPBLCD30 (1U)          /*!< Bit position for LCD_WF30_BPBLCD30. */
#define BM_LCD_WF30_BPBLCD30 (0x02U)       /*!< Bit mask for LCD_WF30_BPBLCD30. */
#define BS_LCD_WF30_BPBLCD30 (1U)          /*!< Bit field size in bits for LCD_WF30_BPBLCD30. */

/*! @brief Read current value of the LCD_WF30_BPBLCD30 field. */
#define BR_LCD_WF30_BPBLCD30(x) (BME_UBFX8(HW_LCD_WF30_ADDR(x), BP_LCD_WF30_BPBLCD30, BS_LCD_WF30_BPBLCD30))

/*! @brief Format value for bitfield LCD_WF30_BPBLCD30. */
#define BF_LCD_WF30_BPBLCD30(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF30_BPBLCD30) & BM_LCD_WF30_BPBLCD30)

/*! @brief Set the BPBLCD30 field to a new value. */
#define BW_LCD_WF30_BPBLCD30(x, v) (BME_BFI8(HW_LCD_WF30_ADDR(x), ((uint8_t)(v) << BP_LCD_WF30_BPBLCD30), BP_LCD_WF30_BPBLCD30, 1))
/*@}*/

/*!
 * @name Register LCD_WF30, field BPCLCD30[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF30_BPCLCD30 (2U)          /*!< Bit position for LCD_WF30_BPCLCD30. */
#define BM_LCD_WF30_BPCLCD30 (0x04U)       /*!< Bit mask for LCD_WF30_BPCLCD30. */
#define BS_LCD_WF30_BPCLCD30 (1U)          /*!< Bit field size in bits for LCD_WF30_BPCLCD30. */

/*! @brief Read current value of the LCD_WF30_BPCLCD30 field. */
#define BR_LCD_WF30_BPCLCD30(x) (BME_UBFX8(HW_LCD_WF30_ADDR(x), BP_LCD_WF30_BPCLCD30, BS_LCD_WF30_BPCLCD30))

/*! @brief Format value for bitfield LCD_WF30_BPCLCD30. */
#define BF_LCD_WF30_BPCLCD30(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF30_BPCLCD30) & BM_LCD_WF30_BPCLCD30)

/*! @brief Set the BPCLCD30 field to a new value. */
#define BW_LCD_WF30_BPCLCD30(x, v) (BME_BFI8(HW_LCD_WF30_ADDR(x), ((uint8_t)(v) << BP_LCD_WF30_BPCLCD30), BP_LCD_WF30_BPCLCD30, 1))
/*@}*/

/*!
 * @name Register LCD_WF30, field BPDLCD30[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF30_BPDLCD30 (3U)          /*!< Bit position for LCD_WF30_BPDLCD30. */
#define BM_LCD_WF30_BPDLCD30 (0x08U)       /*!< Bit mask for LCD_WF30_BPDLCD30. */
#define BS_LCD_WF30_BPDLCD30 (1U)          /*!< Bit field size in bits for LCD_WF30_BPDLCD30. */

/*! @brief Read current value of the LCD_WF30_BPDLCD30 field. */
#define BR_LCD_WF30_BPDLCD30(x) (BME_UBFX8(HW_LCD_WF30_ADDR(x), BP_LCD_WF30_BPDLCD30, BS_LCD_WF30_BPDLCD30))

/*! @brief Format value for bitfield LCD_WF30_BPDLCD30. */
#define BF_LCD_WF30_BPDLCD30(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF30_BPDLCD30) & BM_LCD_WF30_BPDLCD30)

/*! @brief Set the BPDLCD30 field to a new value. */
#define BW_LCD_WF30_BPDLCD30(x, v) (BME_BFI8(HW_LCD_WF30_ADDR(x), ((uint8_t)(v) << BP_LCD_WF30_BPDLCD30), BP_LCD_WF30_BPDLCD30, 1))
/*@}*/

/*!
 * @name Register LCD_WF30, field BPELCD30[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF30_BPELCD30 (4U)          /*!< Bit position for LCD_WF30_BPELCD30. */
#define BM_LCD_WF30_BPELCD30 (0x10U)       /*!< Bit mask for LCD_WF30_BPELCD30. */
#define BS_LCD_WF30_BPELCD30 (1U)          /*!< Bit field size in bits for LCD_WF30_BPELCD30. */

/*! @brief Read current value of the LCD_WF30_BPELCD30 field. */
#define BR_LCD_WF30_BPELCD30(x) (BME_UBFX8(HW_LCD_WF30_ADDR(x), BP_LCD_WF30_BPELCD30, BS_LCD_WF30_BPELCD30))

/*! @brief Format value for bitfield LCD_WF30_BPELCD30. */
#define BF_LCD_WF30_BPELCD30(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF30_BPELCD30) & BM_LCD_WF30_BPELCD30)

/*! @brief Set the BPELCD30 field to a new value. */
#define BW_LCD_WF30_BPELCD30(x, v) (BME_BFI8(HW_LCD_WF30_ADDR(x), ((uint8_t)(v) << BP_LCD_WF30_BPELCD30), BP_LCD_WF30_BPELCD30, 1))
/*@}*/

/*!
 * @name Register LCD_WF30, field BPFLCD30[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF30_BPFLCD30 (5U)          /*!< Bit position for LCD_WF30_BPFLCD30. */
#define BM_LCD_WF30_BPFLCD30 (0x20U)       /*!< Bit mask for LCD_WF30_BPFLCD30. */
#define BS_LCD_WF30_BPFLCD30 (1U)          /*!< Bit field size in bits for LCD_WF30_BPFLCD30. */

/*! @brief Read current value of the LCD_WF30_BPFLCD30 field. */
#define BR_LCD_WF30_BPFLCD30(x) (BME_UBFX8(HW_LCD_WF30_ADDR(x), BP_LCD_WF30_BPFLCD30, BS_LCD_WF30_BPFLCD30))

/*! @brief Format value for bitfield LCD_WF30_BPFLCD30. */
#define BF_LCD_WF30_BPFLCD30(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF30_BPFLCD30) & BM_LCD_WF30_BPFLCD30)

/*! @brief Set the BPFLCD30 field to a new value. */
#define BW_LCD_WF30_BPFLCD30(x, v) (BME_BFI8(HW_LCD_WF30_ADDR(x), ((uint8_t)(v) << BP_LCD_WF30_BPFLCD30), BP_LCD_WF30_BPFLCD30, 1))
/*@}*/

/*!
 * @name Register LCD_WF30, field BPGLCD30[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF30_BPGLCD30 (6U)          /*!< Bit position for LCD_WF30_BPGLCD30. */
#define BM_LCD_WF30_BPGLCD30 (0x40U)       /*!< Bit mask for LCD_WF30_BPGLCD30. */
#define BS_LCD_WF30_BPGLCD30 (1U)          /*!< Bit field size in bits for LCD_WF30_BPGLCD30. */

/*! @brief Read current value of the LCD_WF30_BPGLCD30 field. */
#define BR_LCD_WF30_BPGLCD30(x) (BME_UBFX8(HW_LCD_WF30_ADDR(x), BP_LCD_WF30_BPGLCD30, BS_LCD_WF30_BPGLCD30))

/*! @brief Format value for bitfield LCD_WF30_BPGLCD30. */
#define BF_LCD_WF30_BPGLCD30(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF30_BPGLCD30) & BM_LCD_WF30_BPGLCD30)

/*! @brief Set the BPGLCD30 field to a new value. */
#define BW_LCD_WF30_BPGLCD30(x, v) (BME_BFI8(HW_LCD_WF30_ADDR(x), ((uint8_t)(v) << BP_LCD_WF30_BPGLCD30), BP_LCD_WF30_BPGLCD30, 1))
/*@}*/

/*!
 * @name Register LCD_WF30, field BPHLCD30[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF30_BPHLCD30 (7U)          /*!< Bit position for LCD_WF30_BPHLCD30. */
#define BM_LCD_WF30_BPHLCD30 (0x80U)       /*!< Bit mask for LCD_WF30_BPHLCD30. */
#define BS_LCD_WF30_BPHLCD30 (1U)          /*!< Bit field size in bits for LCD_WF30_BPHLCD30. */

/*! @brief Read current value of the LCD_WF30_BPHLCD30 field. */
#define BR_LCD_WF30_BPHLCD30(x) (BME_UBFX8(HW_LCD_WF30_ADDR(x), BP_LCD_WF30_BPHLCD30, BS_LCD_WF30_BPHLCD30))

/*! @brief Format value for bitfield LCD_WF30_BPHLCD30. */
#define BF_LCD_WF30_BPHLCD30(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF30_BPHLCD30) & BM_LCD_WF30_BPHLCD30)

/*! @brief Set the BPHLCD30 field to a new value. */
#define BW_LCD_WF30_BPHLCD30(x, v) (BME_BFI8(HW_LCD_WF30_ADDR(x), ((uint8_t)(v) << BP_LCD_WF30_BPHLCD30), BP_LCD_WF30_BPHLCD30, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF31 - LCD Waveform Register 31.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF31 - LCD Waveform Register 31. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf31
{
    uint8_t U;
    struct _hw_lcd_wf31_bitfields
    {
        uint8_t BPALCD31 : 1;          /*!< [0]  */
        uint8_t BPBLCD31 : 1;          /*!< [1]  */
        uint8_t BPCLCD31 : 1;          /*!< [2]  */
        uint8_t BPDLCD31 : 1;          /*!< [3]  */
        uint8_t BPELCD31 : 1;          /*!< [4]  */
        uint8_t BPFLCD31 : 1;          /*!< [5]  */
        uint8_t BPGLCD31 : 1;          /*!< [6]  */
        uint8_t BPHLCD31 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf31_t;

/*!
 * @name Constants and macros for entire LCD_WF31 register
 */
/*@{*/
#define HW_LCD_WF31_ADDR(x)      ((x) + 0x3FU)

#define HW_LCD_WF31(x)           (*(__IO hw_lcd_wf31_t *) HW_LCD_WF31_ADDR(x))
#define HW_LCD_WF31_RD(x)        (HW_LCD_WF31(x).U)
#define HW_LCD_WF31_WR(x, v)     (HW_LCD_WF31(x).U = (v))
#define HW_LCD_WF31_SET(x, v)    (BME_OR8(HW_LCD_WF31_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF31_CLR(x, v)    (BME_AND8(HW_LCD_WF31_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF31_TOG(x, v)    (BME_XOR8(HW_LCD_WF31_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF31 bitfields
 */

/*!
 * @name Register LCD_WF31, field BPALCD31[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF31_BPALCD31 (0U)          /*!< Bit position for LCD_WF31_BPALCD31. */
#define BM_LCD_WF31_BPALCD31 (0x01U)       /*!< Bit mask for LCD_WF31_BPALCD31. */
#define BS_LCD_WF31_BPALCD31 (1U)          /*!< Bit field size in bits for LCD_WF31_BPALCD31. */

/*! @brief Read current value of the LCD_WF31_BPALCD31 field. */
#define BR_LCD_WF31_BPALCD31(x) (BME_UBFX8(HW_LCD_WF31_ADDR(x), BP_LCD_WF31_BPALCD31, BS_LCD_WF31_BPALCD31))

/*! @brief Format value for bitfield LCD_WF31_BPALCD31. */
#define BF_LCD_WF31_BPALCD31(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF31_BPALCD31) & BM_LCD_WF31_BPALCD31)

/*! @brief Set the BPALCD31 field to a new value. */
#define BW_LCD_WF31_BPALCD31(x, v) (BME_BFI8(HW_LCD_WF31_ADDR(x), ((uint8_t)(v) << BP_LCD_WF31_BPALCD31), BP_LCD_WF31_BPALCD31, 1))
/*@}*/

/*!
 * @name Register LCD_WF31, field BPBLCD31[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF31_BPBLCD31 (1U)          /*!< Bit position for LCD_WF31_BPBLCD31. */
#define BM_LCD_WF31_BPBLCD31 (0x02U)       /*!< Bit mask for LCD_WF31_BPBLCD31. */
#define BS_LCD_WF31_BPBLCD31 (1U)          /*!< Bit field size in bits for LCD_WF31_BPBLCD31. */

/*! @brief Read current value of the LCD_WF31_BPBLCD31 field. */
#define BR_LCD_WF31_BPBLCD31(x) (BME_UBFX8(HW_LCD_WF31_ADDR(x), BP_LCD_WF31_BPBLCD31, BS_LCD_WF31_BPBLCD31))

/*! @brief Format value for bitfield LCD_WF31_BPBLCD31. */
#define BF_LCD_WF31_BPBLCD31(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF31_BPBLCD31) & BM_LCD_WF31_BPBLCD31)

/*! @brief Set the BPBLCD31 field to a new value. */
#define BW_LCD_WF31_BPBLCD31(x, v) (BME_BFI8(HW_LCD_WF31_ADDR(x), ((uint8_t)(v) << BP_LCD_WF31_BPBLCD31), BP_LCD_WF31_BPBLCD31, 1))
/*@}*/

/*!
 * @name Register LCD_WF31, field BPCLCD31[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF31_BPCLCD31 (2U)          /*!< Bit position for LCD_WF31_BPCLCD31. */
#define BM_LCD_WF31_BPCLCD31 (0x04U)       /*!< Bit mask for LCD_WF31_BPCLCD31. */
#define BS_LCD_WF31_BPCLCD31 (1U)          /*!< Bit field size in bits for LCD_WF31_BPCLCD31. */

/*! @brief Read current value of the LCD_WF31_BPCLCD31 field. */
#define BR_LCD_WF31_BPCLCD31(x) (BME_UBFX8(HW_LCD_WF31_ADDR(x), BP_LCD_WF31_BPCLCD31, BS_LCD_WF31_BPCLCD31))

/*! @brief Format value for bitfield LCD_WF31_BPCLCD31. */
#define BF_LCD_WF31_BPCLCD31(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF31_BPCLCD31) & BM_LCD_WF31_BPCLCD31)

/*! @brief Set the BPCLCD31 field to a new value. */
#define BW_LCD_WF31_BPCLCD31(x, v) (BME_BFI8(HW_LCD_WF31_ADDR(x), ((uint8_t)(v) << BP_LCD_WF31_BPCLCD31), BP_LCD_WF31_BPCLCD31, 1))
/*@}*/

/*!
 * @name Register LCD_WF31, field BPDLCD31[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF31_BPDLCD31 (3U)          /*!< Bit position for LCD_WF31_BPDLCD31. */
#define BM_LCD_WF31_BPDLCD31 (0x08U)       /*!< Bit mask for LCD_WF31_BPDLCD31. */
#define BS_LCD_WF31_BPDLCD31 (1U)          /*!< Bit field size in bits for LCD_WF31_BPDLCD31. */

/*! @brief Read current value of the LCD_WF31_BPDLCD31 field. */
#define BR_LCD_WF31_BPDLCD31(x) (BME_UBFX8(HW_LCD_WF31_ADDR(x), BP_LCD_WF31_BPDLCD31, BS_LCD_WF31_BPDLCD31))

/*! @brief Format value for bitfield LCD_WF31_BPDLCD31. */
#define BF_LCD_WF31_BPDLCD31(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF31_BPDLCD31) & BM_LCD_WF31_BPDLCD31)

/*! @brief Set the BPDLCD31 field to a new value. */
#define BW_LCD_WF31_BPDLCD31(x, v) (BME_BFI8(HW_LCD_WF31_ADDR(x), ((uint8_t)(v) << BP_LCD_WF31_BPDLCD31), BP_LCD_WF31_BPDLCD31, 1))
/*@}*/

/*!
 * @name Register LCD_WF31, field BPELCD31[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF31_BPELCD31 (4U)          /*!< Bit position for LCD_WF31_BPELCD31. */
#define BM_LCD_WF31_BPELCD31 (0x10U)       /*!< Bit mask for LCD_WF31_BPELCD31. */
#define BS_LCD_WF31_BPELCD31 (1U)          /*!< Bit field size in bits for LCD_WF31_BPELCD31. */

/*! @brief Read current value of the LCD_WF31_BPELCD31 field. */
#define BR_LCD_WF31_BPELCD31(x) (BME_UBFX8(HW_LCD_WF31_ADDR(x), BP_LCD_WF31_BPELCD31, BS_LCD_WF31_BPELCD31))

/*! @brief Format value for bitfield LCD_WF31_BPELCD31. */
#define BF_LCD_WF31_BPELCD31(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF31_BPELCD31) & BM_LCD_WF31_BPELCD31)

/*! @brief Set the BPELCD31 field to a new value. */
#define BW_LCD_WF31_BPELCD31(x, v) (BME_BFI8(HW_LCD_WF31_ADDR(x), ((uint8_t)(v) << BP_LCD_WF31_BPELCD31), BP_LCD_WF31_BPELCD31, 1))
/*@}*/

/*!
 * @name Register LCD_WF31, field BPFLCD31[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF31_BPFLCD31 (5U)          /*!< Bit position for LCD_WF31_BPFLCD31. */
#define BM_LCD_WF31_BPFLCD31 (0x20U)       /*!< Bit mask for LCD_WF31_BPFLCD31. */
#define BS_LCD_WF31_BPFLCD31 (1U)          /*!< Bit field size in bits for LCD_WF31_BPFLCD31. */

/*! @brief Read current value of the LCD_WF31_BPFLCD31 field. */
#define BR_LCD_WF31_BPFLCD31(x) (BME_UBFX8(HW_LCD_WF31_ADDR(x), BP_LCD_WF31_BPFLCD31, BS_LCD_WF31_BPFLCD31))

/*! @brief Format value for bitfield LCD_WF31_BPFLCD31. */
#define BF_LCD_WF31_BPFLCD31(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF31_BPFLCD31) & BM_LCD_WF31_BPFLCD31)

/*! @brief Set the BPFLCD31 field to a new value. */
#define BW_LCD_WF31_BPFLCD31(x, v) (BME_BFI8(HW_LCD_WF31_ADDR(x), ((uint8_t)(v) << BP_LCD_WF31_BPFLCD31), BP_LCD_WF31_BPFLCD31, 1))
/*@}*/

/*!
 * @name Register LCD_WF31, field BPGLCD31[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF31_BPGLCD31 (6U)          /*!< Bit position for LCD_WF31_BPGLCD31. */
#define BM_LCD_WF31_BPGLCD31 (0x40U)       /*!< Bit mask for LCD_WF31_BPGLCD31. */
#define BS_LCD_WF31_BPGLCD31 (1U)          /*!< Bit field size in bits for LCD_WF31_BPGLCD31. */

/*! @brief Read current value of the LCD_WF31_BPGLCD31 field. */
#define BR_LCD_WF31_BPGLCD31(x) (BME_UBFX8(HW_LCD_WF31_ADDR(x), BP_LCD_WF31_BPGLCD31, BS_LCD_WF31_BPGLCD31))

/*! @brief Format value for bitfield LCD_WF31_BPGLCD31. */
#define BF_LCD_WF31_BPGLCD31(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF31_BPGLCD31) & BM_LCD_WF31_BPGLCD31)

/*! @brief Set the BPGLCD31 field to a new value. */
#define BW_LCD_WF31_BPGLCD31(x, v) (BME_BFI8(HW_LCD_WF31_ADDR(x), ((uint8_t)(v) << BP_LCD_WF31_BPGLCD31), BP_LCD_WF31_BPGLCD31, 1))
/*@}*/

/*!
 * @name Register LCD_WF31, field BPHLCD31[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF31_BPHLCD31 (7U)          /*!< Bit position for LCD_WF31_BPHLCD31. */
#define BM_LCD_WF31_BPHLCD31 (0x80U)       /*!< Bit mask for LCD_WF31_BPHLCD31. */
#define BS_LCD_WF31_BPHLCD31 (1U)          /*!< Bit field size in bits for LCD_WF31_BPHLCD31. */

/*! @brief Read current value of the LCD_WF31_BPHLCD31 field. */
#define BR_LCD_WF31_BPHLCD31(x) (BME_UBFX8(HW_LCD_WF31_ADDR(x), BP_LCD_WF31_BPHLCD31, BS_LCD_WF31_BPHLCD31))

/*! @brief Format value for bitfield LCD_WF31_BPHLCD31. */
#define BF_LCD_WF31_BPHLCD31(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF31_BPHLCD31) & BM_LCD_WF31_BPHLCD31)

/*! @brief Set the BPHLCD31 field to a new value. */
#define BW_LCD_WF31_BPHLCD31(x, v) (BME_BFI8(HW_LCD_WF31_ADDR(x), ((uint8_t)(v) << BP_LCD_WF31_BPHLCD31), BP_LCD_WF31_BPHLCD31, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF32 - LCD Waveform Register 32.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF32 - LCD Waveform Register 32. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf32
{
    uint8_t U;
    struct _hw_lcd_wf32_bitfields
    {
        uint8_t BPALCD32 : 1;          /*!< [0]  */
        uint8_t BPBLCD32 : 1;          /*!< [1]  */
        uint8_t BPCLCD32 : 1;          /*!< [2]  */
        uint8_t BPDLCD32 : 1;          /*!< [3]  */
        uint8_t BPELCD32 : 1;          /*!< [4]  */
        uint8_t BPFLCD32 : 1;          /*!< [5]  */
        uint8_t BPGLCD32 : 1;          /*!< [6]  */
        uint8_t BPHLCD32 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf32_t;

/*!
 * @name Constants and macros for entire LCD_WF32 register
 */
/*@{*/
#define HW_LCD_WF32_ADDR(x)      ((x) + 0x40U)

#define HW_LCD_WF32(x)           (*(__IO hw_lcd_wf32_t *) HW_LCD_WF32_ADDR(x))
#define HW_LCD_WF32_RD(x)        (HW_LCD_WF32(x).U)
#define HW_LCD_WF32_WR(x, v)     (HW_LCD_WF32(x).U = (v))
#define HW_LCD_WF32_SET(x, v)    (BME_OR8(HW_LCD_WF32_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF32_CLR(x, v)    (BME_AND8(HW_LCD_WF32_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF32_TOG(x, v)    (BME_XOR8(HW_LCD_WF32_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF32 bitfields
 */

/*!
 * @name Register LCD_WF32, field BPALCD32[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF32_BPALCD32 (0U)          /*!< Bit position for LCD_WF32_BPALCD32. */
#define BM_LCD_WF32_BPALCD32 (0x01U)       /*!< Bit mask for LCD_WF32_BPALCD32. */
#define BS_LCD_WF32_BPALCD32 (1U)          /*!< Bit field size in bits for LCD_WF32_BPALCD32. */

/*! @brief Read current value of the LCD_WF32_BPALCD32 field. */
#define BR_LCD_WF32_BPALCD32(x) (BME_UBFX8(HW_LCD_WF32_ADDR(x), BP_LCD_WF32_BPALCD32, BS_LCD_WF32_BPALCD32))

/*! @brief Format value for bitfield LCD_WF32_BPALCD32. */
#define BF_LCD_WF32_BPALCD32(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF32_BPALCD32) & BM_LCD_WF32_BPALCD32)

/*! @brief Set the BPALCD32 field to a new value. */
#define BW_LCD_WF32_BPALCD32(x, v) (BME_BFI8(HW_LCD_WF32_ADDR(x), ((uint8_t)(v) << BP_LCD_WF32_BPALCD32), BP_LCD_WF32_BPALCD32, 1))
/*@}*/

/*!
 * @name Register LCD_WF32, field BPBLCD32[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF32_BPBLCD32 (1U)          /*!< Bit position for LCD_WF32_BPBLCD32. */
#define BM_LCD_WF32_BPBLCD32 (0x02U)       /*!< Bit mask for LCD_WF32_BPBLCD32. */
#define BS_LCD_WF32_BPBLCD32 (1U)          /*!< Bit field size in bits for LCD_WF32_BPBLCD32. */

/*! @brief Read current value of the LCD_WF32_BPBLCD32 field. */
#define BR_LCD_WF32_BPBLCD32(x) (BME_UBFX8(HW_LCD_WF32_ADDR(x), BP_LCD_WF32_BPBLCD32, BS_LCD_WF32_BPBLCD32))

/*! @brief Format value for bitfield LCD_WF32_BPBLCD32. */
#define BF_LCD_WF32_BPBLCD32(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF32_BPBLCD32) & BM_LCD_WF32_BPBLCD32)

/*! @brief Set the BPBLCD32 field to a new value. */
#define BW_LCD_WF32_BPBLCD32(x, v) (BME_BFI8(HW_LCD_WF32_ADDR(x), ((uint8_t)(v) << BP_LCD_WF32_BPBLCD32), BP_LCD_WF32_BPBLCD32, 1))
/*@}*/

/*!
 * @name Register LCD_WF32, field BPCLCD32[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF32_BPCLCD32 (2U)          /*!< Bit position for LCD_WF32_BPCLCD32. */
#define BM_LCD_WF32_BPCLCD32 (0x04U)       /*!< Bit mask for LCD_WF32_BPCLCD32. */
#define BS_LCD_WF32_BPCLCD32 (1U)          /*!< Bit field size in bits for LCD_WF32_BPCLCD32. */

/*! @brief Read current value of the LCD_WF32_BPCLCD32 field. */
#define BR_LCD_WF32_BPCLCD32(x) (BME_UBFX8(HW_LCD_WF32_ADDR(x), BP_LCD_WF32_BPCLCD32, BS_LCD_WF32_BPCLCD32))

/*! @brief Format value for bitfield LCD_WF32_BPCLCD32. */
#define BF_LCD_WF32_BPCLCD32(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF32_BPCLCD32) & BM_LCD_WF32_BPCLCD32)

/*! @brief Set the BPCLCD32 field to a new value. */
#define BW_LCD_WF32_BPCLCD32(x, v) (BME_BFI8(HW_LCD_WF32_ADDR(x), ((uint8_t)(v) << BP_LCD_WF32_BPCLCD32), BP_LCD_WF32_BPCLCD32, 1))
/*@}*/

/*!
 * @name Register LCD_WF32, field BPDLCD32[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF32_BPDLCD32 (3U)          /*!< Bit position for LCD_WF32_BPDLCD32. */
#define BM_LCD_WF32_BPDLCD32 (0x08U)       /*!< Bit mask for LCD_WF32_BPDLCD32. */
#define BS_LCD_WF32_BPDLCD32 (1U)          /*!< Bit field size in bits for LCD_WF32_BPDLCD32. */

/*! @brief Read current value of the LCD_WF32_BPDLCD32 field. */
#define BR_LCD_WF32_BPDLCD32(x) (BME_UBFX8(HW_LCD_WF32_ADDR(x), BP_LCD_WF32_BPDLCD32, BS_LCD_WF32_BPDLCD32))

/*! @brief Format value for bitfield LCD_WF32_BPDLCD32. */
#define BF_LCD_WF32_BPDLCD32(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF32_BPDLCD32) & BM_LCD_WF32_BPDLCD32)

/*! @brief Set the BPDLCD32 field to a new value. */
#define BW_LCD_WF32_BPDLCD32(x, v) (BME_BFI8(HW_LCD_WF32_ADDR(x), ((uint8_t)(v) << BP_LCD_WF32_BPDLCD32), BP_LCD_WF32_BPDLCD32, 1))
/*@}*/

/*!
 * @name Register LCD_WF32, field BPELCD32[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF32_BPELCD32 (4U)          /*!< Bit position for LCD_WF32_BPELCD32. */
#define BM_LCD_WF32_BPELCD32 (0x10U)       /*!< Bit mask for LCD_WF32_BPELCD32. */
#define BS_LCD_WF32_BPELCD32 (1U)          /*!< Bit field size in bits for LCD_WF32_BPELCD32. */

/*! @brief Read current value of the LCD_WF32_BPELCD32 field. */
#define BR_LCD_WF32_BPELCD32(x) (BME_UBFX8(HW_LCD_WF32_ADDR(x), BP_LCD_WF32_BPELCD32, BS_LCD_WF32_BPELCD32))

/*! @brief Format value for bitfield LCD_WF32_BPELCD32. */
#define BF_LCD_WF32_BPELCD32(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF32_BPELCD32) & BM_LCD_WF32_BPELCD32)

/*! @brief Set the BPELCD32 field to a new value. */
#define BW_LCD_WF32_BPELCD32(x, v) (BME_BFI8(HW_LCD_WF32_ADDR(x), ((uint8_t)(v) << BP_LCD_WF32_BPELCD32), BP_LCD_WF32_BPELCD32, 1))
/*@}*/

/*!
 * @name Register LCD_WF32, field BPFLCD32[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF32_BPFLCD32 (5U)          /*!< Bit position for LCD_WF32_BPFLCD32. */
#define BM_LCD_WF32_BPFLCD32 (0x20U)       /*!< Bit mask for LCD_WF32_BPFLCD32. */
#define BS_LCD_WF32_BPFLCD32 (1U)          /*!< Bit field size in bits for LCD_WF32_BPFLCD32. */

/*! @brief Read current value of the LCD_WF32_BPFLCD32 field. */
#define BR_LCD_WF32_BPFLCD32(x) (BME_UBFX8(HW_LCD_WF32_ADDR(x), BP_LCD_WF32_BPFLCD32, BS_LCD_WF32_BPFLCD32))

/*! @brief Format value for bitfield LCD_WF32_BPFLCD32. */
#define BF_LCD_WF32_BPFLCD32(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF32_BPFLCD32) & BM_LCD_WF32_BPFLCD32)

/*! @brief Set the BPFLCD32 field to a new value. */
#define BW_LCD_WF32_BPFLCD32(x, v) (BME_BFI8(HW_LCD_WF32_ADDR(x), ((uint8_t)(v) << BP_LCD_WF32_BPFLCD32), BP_LCD_WF32_BPFLCD32, 1))
/*@}*/

/*!
 * @name Register LCD_WF32, field BPGLCD32[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF32_BPGLCD32 (6U)          /*!< Bit position for LCD_WF32_BPGLCD32. */
#define BM_LCD_WF32_BPGLCD32 (0x40U)       /*!< Bit mask for LCD_WF32_BPGLCD32. */
#define BS_LCD_WF32_BPGLCD32 (1U)          /*!< Bit field size in bits for LCD_WF32_BPGLCD32. */

/*! @brief Read current value of the LCD_WF32_BPGLCD32 field. */
#define BR_LCD_WF32_BPGLCD32(x) (BME_UBFX8(HW_LCD_WF32_ADDR(x), BP_LCD_WF32_BPGLCD32, BS_LCD_WF32_BPGLCD32))

/*! @brief Format value for bitfield LCD_WF32_BPGLCD32. */
#define BF_LCD_WF32_BPGLCD32(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF32_BPGLCD32) & BM_LCD_WF32_BPGLCD32)

/*! @brief Set the BPGLCD32 field to a new value. */
#define BW_LCD_WF32_BPGLCD32(x, v) (BME_BFI8(HW_LCD_WF32_ADDR(x), ((uint8_t)(v) << BP_LCD_WF32_BPGLCD32), BP_LCD_WF32_BPGLCD32, 1))
/*@}*/

/*!
 * @name Register LCD_WF32, field BPHLCD32[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF32_BPHLCD32 (7U)          /*!< Bit position for LCD_WF32_BPHLCD32. */
#define BM_LCD_WF32_BPHLCD32 (0x80U)       /*!< Bit mask for LCD_WF32_BPHLCD32. */
#define BS_LCD_WF32_BPHLCD32 (1U)          /*!< Bit field size in bits for LCD_WF32_BPHLCD32. */

/*! @brief Read current value of the LCD_WF32_BPHLCD32 field. */
#define BR_LCD_WF32_BPHLCD32(x) (BME_UBFX8(HW_LCD_WF32_ADDR(x), BP_LCD_WF32_BPHLCD32, BS_LCD_WF32_BPHLCD32))

/*! @brief Format value for bitfield LCD_WF32_BPHLCD32. */
#define BF_LCD_WF32_BPHLCD32(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF32_BPHLCD32) & BM_LCD_WF32_BPHLCD32)

/*! @brief Set the BPHLCD32 field to a new value. */
#define BW_LCD_WF32_BPHLCD32(x, v) (BME_BFI8(HW_LCD_WF32_ADDR(x), ((uint8_t)(v) << BP_LCD_WF32_BPHLCD32), BP_LCD_WF32_BPHLCD32, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF33 - LCD Waveform Register 33.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF33 - LCD Waveform Register 33. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf33
{
    uint8_t U;
    struct _hw_lcd_wf33_bitfields
    {
        uint8_t BPALCD33 : 1;          /*!< [0]  */
        uint8_t BPBLCD33 : 1;          /*!< [1]  */
        uint8_t BPCLCD33 : 1;          /*!< [2]  */
        uint8_t BPDLCD33 : 1;          /*!< [3]  */
        uint8_t BPELCD33 : 1;          /*!< [4]  */
        uint8_t BPFLCD33 : 1;          /*!< [5]  */
        uint8_t BPGLCD33 : 1;          /*!< [6]  */
        uint8_t BPHLCD33 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf33_t;

/*!
 * @name Constants and macros for entire LCD_WF33 register
 */
/*@{*/
#define HW_LCD_WF33_ADDR(x)      ((x) + 0x41U)

#define HW_LCD_WF33(x)           (*(__IO hw_lcd_wf33_t *) HW_LCD_WF33_ADDR(x))
#define HW_LCD_WF33_RD(x)        (HW_LCD_WF33(x).U)
#define HW_LCD_WF33_WR(x, v)     (HW_LCD_WF33(x).U = (v))
#define HW_LCD_WF33_SET(x, v)    (BME_OR8(HW_LCD_WF33_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF33_CLR(x, v)    (BME_AND8(HW_LCD_WF33_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF33_TOG(x, v)    (BME_XOR8(HW_LCD_WF33_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF33 bitfields
 */

/*!
 * @name Register LCD_WF33, field BPALCD33[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF33_BPALCD33 (0U)          /*!< Bit position for LCD_WF33_BPALCD33. */
#define BM_LCD_WF33_BPALCD33 (0x01U)       /*!< Bit mask for LCD_WF33_BPALCD33. */
#define BS_LCD_WF33_BPALCD33 (1U)          /*!< Bit field size in bits for LCD_WF33_BPALCD33. */

/*! @brief Read current value of the LCD_WF33_BPALCD33 field. */
#define BR_LCD_WF33_BPALCD33(x) (BME_UBFX8(HW_LCD_WF33_ADDR(x), BP_LCD_WF33_BPALCD33, BS_LCD_WF33_BPALCD33))

/*! @brief Format value for bitfield LCD_WF33_BPALCD33. */
#define BF_LCD_WF33_BPALCD33(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF33_BPALCD33) & BM_LCD_WF33_BPALCD33)

/*! @brief Set the BPALCD33 field to a new value. */
#define BW_LCD_WF33_BPALCD33(x, v) (BME_BFI8(HW_LCD_WF33_ADDR(x), ((uint8_t)(v) << BP_LCD_WF33_BPALCD33), BP_LCD_WF33_BPALCD33, 1))
/*@}*/

/*!
 * @name Register LCD_WF33, field BPBLCD33[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF33_BPBLCD33 (1U)          /*!< Bit position for LCD_WF33_BPBLCD33. */
#define BM_LCD_WF33_BPBLCD33 (0x02U)       /*!< Bit mask for LCD_WF33_BPBLCD33. */
#define BS_LCD_WF33_BPBLCD33 (1U)          /*!< Bit field size in bits for LCD_WF33_BPBLCD33. */

/*! @brief Read current value of the LCD_WF33_BPBLCD33 field. */
#define BR_LCD_WF33_BPBLCD33(x) (BME_UBFX8(HW_LCD_WF33_ADDR(x), BP_LCD_WF33_BPBLCD33, BS_LCD_WF33_BPBLCD33))

/*! @brief Format value for bitfield LCD_WF33_BPBLCD33. */
#define BF_LCD_WF33_BPBLCD33(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF33_BPBLCD33) & BM_LCD_WF33_BPBLCD33)

/*! @brief Set the BPBLCD33 field to a new value. */
#define BW_LCD_WF33_BPBLCD33(x, v) (BME_BFI8(HW_LCD_WF33_ADDR(x), ((uint8_t)(v) << BP_LCD_WF33_BPBLCD33), BP_LCD_WF33_BPBLCD33, 1))
/*@}*/

/*!
 * @name Register LCD_WF33, field BPCLCD33[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF33_BPCLCD33 (2U)          /*!< Bit position for LCD_WF33_BPCLCD33. */
#define BM_LCD_WF33_BPCLCD33 (0x04U)       /*!< Bit mask for LCD_WF33_BPCLCD33. */
#define BS_LCD_WF33_BPCLCD33 (1U)          /*!< Bit field size in bits for LCD_WF33_BPCLCD33. */

/*! @brief Read current value of the LCD_WF33_BPCLCD33 field. */
#define BR_LCD_WF33_BPCLCD33(x) (BME_UBFX8(HW_LCD_WF33_ADDR(x), BP_LCD_WF33_BPCLCD33, BS_LCD_WF33_BPCLCD33))

/*! @brief Format value for bitfield LCD_WF33_BPCLCD33. */
#define BF_LCD_WF33_BPCLCD33(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF33_BPCLCD33) & BM_LCD_WF33_BPCLCD33)

/*! @brief Set the BPCLCD33 field to a new value. */
#define BW_LCD_WF33_BPCLCD33(x, v) (BME_BFI8(HW_LCD_WF33_ADDR(x), ((uint8_t)(v) << BP_LCD_WF33_BPCLCD33), BP_LCD_WF33_BPCLCD33, 1))
/*@}*/

/*!
 * @name Register LCD_WF33, field BPDLCD33[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF33_BPDLCD33 (3U)          /*!< Bit position for LCD_WF33_BPDLCD33. */
#define BM_LCD_WF33_BPDLCD33 (0x08U)       /*!< Bit mask for LCD_WF33_BPDLCD33. */
#define BS_LCD_WF33_BPDLCD33 (1U)          /*!< Bit field size in bits for LCD_WF33_BPDLCD33. */

/*! @brief Read current value of the LCD_WF33_BPDLCD33 field. */
#define BR_LCD_WF33_BPDLCD33(x) (BME_UBFX8(HW_LCD_WF33_ADDR(x), BP_LCD_WF33_BPDLCD33, BS_LCD_WF33_BPDLCD33))

/*! @brief Format value for bitfield LCD_WF33_BPDLCD33. */
#define BF_LCD_WF33_BPDLCD33(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF33_BPDLCD33) & BM_LCD_WF33_BPDLCD33)

/*! @brief Set the BPDLCD33 field to a new value. */
#define BW_LCD_WF33_BPDLCD33(x, v) (BME_BFI8(HW_LCD_WF33_ADDR(x), ((uint8_t)(v) << BP_LCD_WF33_BPDLCD33), BP_LCD_WF33_BPDLCD33, 1))
/*@}*/

/*!
 * @name Register LCD_WF33, field BPELCD33[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF33_BPELCD33 (4U)          /*!< Bit position for LCD_WF33_BPELCD33. */
#define BM_LCD_WF33_BPELCD33 (0x10U)       /*!< Bit mask for LCD_WF33_BPELCD33. */
#define BS_LCD_WF33_BPELCD33 (1U)          /*!< Bit field size in bits for LCD_WF33_BPELCD33. */

/*! @brief Read current value of the LCD_WF33_BPELCD33 field. */
#define BR_LCD_WF33_BPELCD33(x) (BME_UBFX8(HW_LCD_WF33_ADDR(x), BP_LCD_WF33_BPELCD33, BS_LCD_WF33_BPELCD33))

/*! @brief Format value for bitfield LCD_WF33_BPELCD33. */
#define BF_LCD_WF33_BPELCD33(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF33_BPELCD33) & BM_LCD_WF33_BPELCD33)

/*! @brief Set the BPELCD33 field to a new value. */
#define BW_LCD_WF33_BPELCD33(x, v) (BME_BFI8(HW_LCD_WF33_ADDR(x), ((uint8_t)(v) << BP_LCD_WF33_BPELCD33), BP_LCD_WF33_BPELCD33, 1))
/*@}*/

/*!
 * @name Register LCD_WF33, field BPFLCD33[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF33_BPFLCD33 (5U)          /*!< Bit position for LCD_WF33_BPFLCD33. */
#define BM_LCD_WF33_BPFLCD33 (0x20U)       /*!< Bit mask for LCD_WF33_BPFLCD33. */
#define BS_LCD_WF33_BPFLCD33 (1U)          /*!< Bit field size in bits for LCD_WF33_BPFLCD33. */

/*! @brief Read current value of the LCD_WF33_BPFLCD33 field. */
#define BR_LCD_WF33_BPFLCD33(x) (BME_UBFX8(HW_LCD_WF33_ADDR(x), BP_LCD_WF33_BPFLCD33, BS_LCD_WF33_BPFLCD33))

/*! @brief Format value for bitfield LCD_WF33_BPFLCD33. */
#define BF_LCD_WF33_BPFLCD33(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF33_BPFLCD33) & BM_LCD_WF33_BPFLCD33)

/*! @brief Set the BPFLCD33 field to a new value. */
#define BW_LCD_WF33_BPFLCD33(x, v) (BME_BFI8(HW_LCD_WF33_ADDR(x), ((uint8_t)(v) << BP_LCD_WF33_BPFLCD33), BP_LCD_WF33_BPFLCD33, 1))
/*@}*/

/*!
 * @name Register LCD_WF33, field BPGLCD33[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF33_BPGLCD33 (6U)          /*!< Bit position for LCD_WF33_BPGLCD33. */
#define BM_LCD_WF33_BPGLCD33 (0x40U)       /*!< Bit mask for LCD_WF33_BPGLCD33. */
#define BS_LCD_WF33_BPGLCD33 (1U)          /*!< Bit field size in bits for LCD_WF33_BPGLCD33. */

/*! @brief Read current value of the LCD_WF33_BPGLCD33 field. */
#define BR_LCD_WF33_BPGLCD33(x) (BME_UBFX8(HW_LCD_WF33_ADDR(x), BP_LCD_WF33_BPGLCD33, BS_LCD_WF33_BPGLCD33))

/*! @brief Format value for bitfield LCD_WF33_BPGLCD33. */
#define BF_LCD_WF33_BPGLCD33(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF33_BPGLCD33) & BM_LCD_WF33_BPGLCD33)

/*! @brief Set the BPGLCD33 field to a new value. */
#define BW_LCD_WF33_BPGLCD33(x, v) (BME_BFI8(HW_LCD_WF33_ADDR(x), ((uint8_t)(v) << BP_LCD_WF33_BPGLCD33), BP_LCD_WF33_BPGLCD33, 1))
/*@}*/

/*!
 * @name Register LCD_WF33, field BPHLCD33[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF33_BPHLCD33 (7U)          /*!< Bit position for LCD_WF33_BPHLCD33. */
#define BM_LCD_WF33_BPHLCD33 (0x80U)       /*!< Bit mask for LCD_WF33_BPHLCD33. */
#define BS_LCD_WF33_BPHLCD33 (1U)          /*!< Bit field size in bits for LCD_WF33_BPHLCD33. */

/*! @brief Read current value of the LCD_WF33_BPHLCD33 field. */
#define BR_LCD_WF33_BPHLCD33(x) (BME_UBFX8(HW_LCD_WF33_ADDR(x), BP_LCD_WF33_BPHLCD33, BS_LCD_WF33_BPHLCD33))

/*! @brief Format value for bitfield LCD_WF33_BPHLCD33. */
#define BF_LCD_WF33_BPHLCD33(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF33_BPHLCD33) & BM_LCD_WF33_BPHLCD33)

/*! @brief Set the BPHLCD33 field to a new value. */
#define BW_LCD_WF33_BPHLCD33(x, v) (BME_BFI8(HW_LCD_WF33_ADDR(x), ((uint8_t)(v) << BP_LCD_WF33_BPHLCD33), BP_LCD_WF33_BPHLCD33, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF34 - LCD Waveform Register 34.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF34 - LCD Waveform Register 34. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf34
{
    uint8_t U;
    struct _hw_lcd_wf34_bitfields
    {
        uint8_t BPALCD34 : 1;          /*!< [0]  */
        uint8_t BPBLCD34 : 1;          /*!< [1]  */
        uint8_t BPCLCD34 : 1;          /*!< [2]  */
        uint8_t BPDLCD34 : 1;          /*!< [3]  */
        uint8_t BPELCD34 : 1;          /*!< [4]  */
        uint8_t BPFLCD34 : 1;          /*!< [5]  */
        uint8_t BPGLCD34 : 1;          /*!< [6]  */
        uint8_t BPHLCD34 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf34_t;

/*!
 * @name Constants and macros for entire LCD_WF34 register
 */
/*@{*/
#define HW_LCD_WF34_ADDR(x)      ((x) + 0x42U)

#define HW_LCD_WF34(x)           (*(__IO hw_lcd_wf34_t *) HW_LCD_WF34_ADDR(x))
#define HW_LCD_WF34_RD(x)        (HW_LCD_WF34(x).U)
#define HW_LCD_WF34_WR(x, v)     (HW_LCD_WF34(x).U = (v))
#define HW_LCD_WF34_SET(x, v)    (BME_OR8(HW_LCD_WF34_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF34_CLR(x, v)    (BME_AND8(HW_LCD_WF34_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF34_TOG(x, v)    (BME_XOR8(HW_LCD_WF34_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF34 bitfields
 */

/*!
 * @name Register LCD_WF34, field BPALCD34[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF34_BPALCD34 (0U)          /*!< Bit position for LCD_WF34_BPALCD34. */
#define BM_LCD_WF34_BPALCD34 (0x01U)       /*!< Bit mask for LCD_WF34_BPALCD34. */
#define BS_LCD_WF34_BPALCD34 (1U)          /*!< Bit field size in bits for LCD_WF34_BPALCD34. */

/*! @brief Read current value of the LCD_WF34_BPALCD34 field. */
#define BR_LCD_WF34_BPALCD34(x) (BME_UBFX8(HW_LCD_WF34_ADDR(x), BP_LCD_WF34_BPALCD34, BS_LCD_WF34_BPALCD34))

/*! @brief Format value for bitfield LCD_WF34_BPALCD34. */
#define BF_LCD_WF34_BPALCD34(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF34_BPALCD34) & BM_LCD_WF34_BPALCD34)

/*! @brief Set the BPALCD34 field to a new value. */
#define BW_LCD_WF34_BPALCD34(x, v) (BME_BFI8(HW_LCD_WF34_ADDR(x), ((uint8_t)(v) << BP_LCD_WF34_BPALCD34), BP_LCD_WF34_BPALCD34, 1))
/*@}*/

/*!
 * @name Register LCD_WF34, field BPBLCD34[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF34_BPBLCD34 (1U)          /*!< Bit position for LCD_WF34_BPBLCD34. */
#define BM_LCD_WF34_BPBLCD34 (0x02U)       /*!< Bit mask for LCD_WF34_BPBLCD34. */
#define BS_LCD_WF34_BPBLCD34 (1U)          /*!< Bit field size in bits for LCD_WF34_BPBLCD34. */

/*! @brief Read current value of the LCD_WF34_BPBLCD34 field. */
#define BR_LCD_WF34_BPBLCD34(x) (BME_UBFX8(HW_LCD_WF34_ADDR(x), BP_LCD_WF34_BPBLCD34, BS_LCD_WF34_BPBLCD34))

/*! @brief Format value for bitfield LCD_WF34_BPBLCD34. */
#define BF_LCD_WF34_BPBLCD34(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF34_BPBLCD34) & BM_LCD_WF34_BPBLCD34)

/*! @brief Set the BPBLCD34 field to a new value. */
#define BW_LCD_WF34_BPBLCD34(x, v) (BME_BFI8(HW_LCD_WF34_ADDR(x), ((uint8_t)(v) << BP_LCD_WF34_BPBLCD34), BP_LCD_WF34_BPBLCD34, 1))
/*@}*/

/*!
 * @name Register LCD_WF34, field BPCLCD34[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF34_BPCLCD34 (2U)          /*!< Bit position for LCD_WF34_BPCLCD34. */
#define BM_LCD_WF34_BPCLCD34 (0x04U)       /*!< Bit mask for LCD_WF34_BPCLCD34. */
#define BS_LCD_WF34_BPCLCD34 (1U)          /*!< Bit field size in bits for LCD_WF34_BPCLCD34. */

/*! @brief Read current value of the LCD_WF34_BPCLCD34 field. */
#define BR_LCD_WF34_BPCLCD34(x) (BME_UBFX8(HW_LCD_WF34_ADDR(x), BP_LCD_WF34_BPCLCD34, BS_LCD_WF34_BPCLCD34))

/*! @brief Format value for bitfield LCD_WF34_BPCLCD34. */
#define BF_LCD_WF34_BPCLCD34(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF34_BPCLCD34) & BM_LCD_WF34_BPCLCD34)

/*! @brief Set the BPCLCD34 field to a new value. */
#define BW_LCD_WF34_BPCLCD34(x, v) (BME_BFI8(HW_LCD_WF34_ADDR(x), ((uint8_t)(v) << BP_LCD_WF34_BPCLCD34), BP_LCD_WF34_BPCLCD34, 1))
/*@}*/

/*!
 * @name Register LCD_WF34, field BPDLCD34[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF34_BPDLCD34 (3U)          /*!< Bit position for LCD_WF34_BPDLCD34. */
#define BM_LCD_WF34_BPDLCD34 (0x08U)       /*!< Bit mask for LCD_WF34_BPDLCD34. */
#define BS_LCD_WF34_BPDLCD34 (1U)          /*!< Bit field size in bits for LCD_WF34_BPDLCD34. */

/*! @brief Read current value of the LCD_WF34_BPDLCD34 field. */
#define BR_LCD_WF34_BPDLCD34(x) (BME_UBFX8(HW_LCD_WF34_ADDR(x), BP_LCD_WF34_BPDLCD34, BS_LCD_WF34_BPDLCD34))

/*! @brief Format value for bitfield LCD_WF34_BPDLCD34. */
#define BF_LCD_WF34_BPDLCD34(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF34_BPDLCD34) & BM_LCD_WF34_BPDLCD34)

/*! @brief Set the BPDLCD34 field to a new value. */
#define BW_LCD_WF34_BPDLCD34(x, v) (BME_BFI8(HW_LCD_WF34_ADDR(x), ((uint8_t)(v) << BP_LCD_WF34_BPDLCD34), BP_LCD_WF34_BPDLCD34, 1))
/*@}*/

/*!
 * @name Register LCD_WF34, field BPELCD34[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF34_BPELCD34 (4U)          /*!< Bit position for LCD_WF34_BPELCD34. */
#define BM_LCD_WF34_BPELCD34 (0x10U)       /*!< Bit mask for LCD_WF34_BPELCD34. */
#define BS_LCD_WF34_BPELCD34 (1U)          /*!< Bit field size in bits for LCD_WF34_BPELCD34. */

/*! @brief Read current value of the LCD_WF34_BPELCD34 field. */
#define BR_LCD_WF34_BPELCD34(x) (BME_UBFX8(HW_LCD_WF34_ADDR(x), BP_LCD_WF34_BPELCD34, BS_LCD_WF34_BPELCD34))

/*! @brief Format value for bitfield LCD_WF34_BPELCD34. */
#define BF_LCD_WF34_BPELCD34(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF34_BPELCD34) & BM_LCD_WF34_BPELCD34)

/*! @brief Set the BPELCD34 field to a new value. */
#define BW_LCD_WF34_BPELCD34(x, v) (BME_BFI8(HW_LCD_WF34_ADDR(x), ((uint8_t)(v) << BP_LCD_WF34_BPELCD34), BP_LCD_WF34_BPELCD34, 1))
/*@}*/

/*!
 * @name Register LCD_WF34, field BPFLCD34[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF34_BPFLCD34 (5U)          /*!< Bit position for LCD_WF34_BPFLCD34. */
#define BM_LCD_WF34_BPFLCD34 (0x20U)       /*!< Bit mask for LCD_WF34_BPFLCD34. */
#define BS_LCD_WF34_BPFLCD34 (1U)          /*!< Bit field size in bits for LCD_WF34_BPFLCD34. */

/*! @brief Read current value of the LCD_WF34_BPFLCD34 field. */
#define BR_LCD_WF34_BPFLCD34(x) (BME_UBFX8(HW_LCD_WF34_ADDR(x), BP_LCD_WF34_BPFLCD34, BS_LCD_WF34_BPFLCD34))

/*! @brief Format value for bitfield LCD_WF34_BPFLCD34. */
#define BF_LCD_WF34_BPFLCD34(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF34_BPFLCD34) & BM_LCD_WF34_BPFLCD34)

/*! @brief Set the BPFLCD34 field to a new value. */
#define BW_LCD_WF34_BPFLCD34(x, v) (BME_BFI8(HW_LCD_WF34_ADDR(x), ((uint8_t)(v) << BP_LCD_WF34_BPFLCD34), BP_LCD_WF34_BPFLCD34, 1))
/*@}*/

/*!
 * @name Register LCD_WF34, field BPGLCD34[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF34_BPGLCD34 (6U)          /*!< Bit position for LCD_WF34_BPGLCD34. */
#define BM_LCD_WF34_BPGLCD34 (0x40U)       /*!< Bit mask for LCD_WF34_BPGLCD34. */
#define BS_LCD_WF34_BPGLCD34 (1U)          /*!< Bit field size in bits for LCD_WF34_BPGLCD34. */

/*! @brief Read current value of the LCD_WF34_BPGLCD34 field. */
#define BR_LCD_WF34_BPGLCD34(x) (BME_UBFX8(HW_LCD_WF34_ADDR(x), BP_LCD_WF34_BPGLCD34, BS_LCD_WF34_BPGLCD34))

/*! @brief Format value for bitfield LCD_WF34_BPGLCD34. */
#define BF_LCD_WF34_BPGLCD34(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF34_BPGLCD34) & BM_LCD_WF34_BPGLCD34)

/*! @brief Set the BPGLCD34 field to a new value. */
#define BW_LCD_WF34_BPGLCD34(x, v) (BME_BFI8(HW_LCD_WF34_ADDR(x), ((uint8_t)(v) << BP_LCD_WF34_BPGLCD34), BP_LCD_WF34_BPGLCD34, 1))
/*@}*/

/*!
 * @name Register LCD_WF34, field BPHLCD34[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF34_BPHLCD34 (7U)          /*!< Bit position for LCD_WF34_BPHLCD34. */
#define BM_LCD_WF34_BPHLCD34 (0x80U)       /*!< Bit mask for LCD_WF34_BPHLCD34. */
#define BS_LCD_WF34_BPHLCD34 (1U)          /*!< Bit field size in bits for LCD_WF34_BPHLCD34. */

/*! @brief Read current value of the LCD_WF34_BPHLCD34 field. */
#define BR_LCD_WF34_BPHLCD34(x) (BME_UBFX8(HW_LCD_WF34_ADDR(x), BP_LCD_WF34_BPHLCD34, BS_LCD_WF34_BPHLCD34))

/*! @brief Format value for bitfield LCD_WF34_BPHLCD34. */
#define BF_LCD_WF34_BPHLCD34(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF34_BPHLCD34) & BM_LCD_WF34_BPHLCD34)

/*! @brief Set the BPHLCD34 field to a new value. */
#define BW_LCD_WF34_BPHLCD34(x, v) (BME_BFI8(HW_LCD_WF34_ADDR(x), ((uint8_t)(v) << BP_LCD_WF34_BPHLCD34), BP_LCD_WF34_BPHLCD34, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF35 - LCD Waveform Register 35.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF35 - LCD Waveform Register 35. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf35
{
    uint8_t U;
    struct _hw_lcd_wf35_bitfields
    {
        uint8_t BPALCD35 : 1;          /*!< [0]  */
        uint8_t BPBLCD35 : 1;          /*!< [1]  */
        uint8_t BPCLCD35 : 1;          /*!< [2]  */
        uint8_t BPDLCD35 : 1;          /*!< [3]  */
        uint8_t BPELCD35 : 1;          /*!< [4]  */
        uint8_t BPFLCD35 : 1;          /*!< [5]  */
        uint8_t BPGLCD35 : 1;          /*!< [6]  */
        uint8_t BPHLCD35 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf35_t;

/*!
 * @name Constants and macros for entire LCD_WF35 register
 */
/*@{*/
#define HW_LCD_WF35_ADDR(x)      ((x) + 0x43U)

#define HW_LCD_WF35(x)           (*(__IO hw_lcd_wf35_t *) HW_LCD_WF35_ADDR(x))
#define HW_LCD_WF35_RD(x)        (HW_LCD_WF35(x).U)
#define HW_LCD_WF35_WR(x, v)     (HW_LCD_WF35(x).U = (v))
#define HW_LCD_WF35_SET(x, v)    (BME_OR8(HW_LCD_WF35_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF35_CLR(x, v)    (BME_AND8(HW_LCD_WF35_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF35_TOG(x, v)    (BME_XOR8(HW_LCD_WF35_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF35 bitfields
 */

/*!
 * @name Register LCD_WF35, field BPALCD35[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF35_BPALCD35 (0U)          /*!< Bit position for LCD_WF35_BPALCD35. */
#define BM_LCD_WF35_BPALCD35 (0x01U)       /*!< Bit mask for LCD_WF35_BPALCD35. */
#define BS_LCD_WF35_BPALCD35 (1U)          /*!< Bit field size in bits for LCD_WF35_BPALCD35. */

/*! @brief Read current value of the LCD_WF35_BPALCD35 field. */
#define BR_LCD_WF35_BPALCD35(x) (BME_UBFX8(HW_LCD_WF35_ADDR(x), BP_LCD_WF35_BPALCD35, BS_LCD_WF35_BPALCD35))

/*! @brief Format value for bitfield LCD_WF35_BPALCD35. */
#define BF_LCD_WF35_BPALCD35(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF35_BPALCD35) & BM_LCD_WF35_BPALCD35)

/*! @brief Set the BPALCD35 field to a new value. */
#define BW_LCD_WF35_BPALCD35(x, v) (BME_BFI8(HW_LCD_WF35_ADDR(x), ((uint8_t)(v) << BP_LCD_WF35_BPALCD35), BP_LCD_WF35_BPALCD35, 1))
/*@}*/

/*!
 * @name Register LCD_WF35, field BPBLCD35[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF35_BPBLCD35 (1U)          /*!< Bit position for LCD_WF35_BPBLCD35. */
#define BM_LCD_WF35_BPBLCD35 (0x02U)       /*!< Bit mask for LCD_WF35_BPBLCD35. */
#define BS_LCD_WF35_BPBLCD35 (1U)          /*!< Bit field size in bits for LCD_WF35_BPBLCD35. */

/*! @brief Read current value of the LCD_WF35_BPBLCD35 field. */
#define BR_LCD_WF35_BPBLCD35(x) (BME_UBFX8(HW_LCD_WF35_ADDR(x), BP_LCD_WF35_BPBLCD35, BS_LCD_WF35_BPBLCD35))

/*! @brief Format value for bitfield LCD_WF35_BPBLCD35. */
#define BF_LCD_WF35_BPBLCD35(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF35_BPBLCD35) & BM_LCD_WF35_BPBLCD35)

/*! @brief Set the BPBLCD35 field to a new value. */
#define BW_LCD_WF35_BPBLCD35(x, v) (BME_BFI8(HW_LCD_WF35_ADDR(x), ((uint8_t)(v) << BP_LCD_WF35_BPBLCD35), BP_LCD_WF35_BPBLCD35, 1))
/*@}*/

/*!
 * @name Register LCD_WF35, field BPCLCD35[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF35_BPCLCD35 (2U)          /*!< Bit position for LCD_WF35_BPCLCD35. */
#define BM_LCD_WF35_BPCLCD35 (0x04U)       /*!< Bit mask for LCD_WF35_BPCLCD35. */
#define BS_LCD_WF35_BPCLCD35 (1U)          /*!< Bit field size in bits for LCD_WF35_BPCLCD35. */

/*! @brief Read current value of the LCD_WF35_BPCLCD35 field. */
#define BR_LCD_WF35_BPCLCD35(x) (BME_UBFX8(HW_LCD_WF35_ADDR(x), BP_LCD_WF35_BPCLCD35, BS_LCD_WF35_BPCLCD35))

/*! @brief Format value for bitfield LCD_WF35_BPCLCD35. */
#define BF_LCD_WF35_BPCLCD35(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF35_BPCLCD35) & BM_LCD_WF35_BPCLCD35)

/*! @brief Set the BPCLCD35 field to a new value. */
#define BW_LCD_WF35_BPCLCD35(x, v) (BME_BFI8(HW_LCD_WF35_ADDR(x), ((uint8_t)(v) << BP_LCD_WF35_BPCLCD35), BP_LCD_WF35_BPCLCD35, 1))
/*@}*/

/*!
 * @name Register LCD_WF35, field BPDLCD35[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF35_BPDLCD35 (3U)          /*!< Bit position for LCD_WF35_BPDLCD35. */
#define BM_LCD_WF35_BPDLCD35 (0x08U)       /*!< Bit mask for LCD_WF35_BPDLCD35. */
#define BS_LCD_WF35_BPDLCD35 (1U)          /*!< Bit field size in bits for LCD_WF35_BPDLCD35. */

/*! @brief Read current value of the LCD_WF35_BPDLCD35 field. */
#define BR_LCD_WF35_BPDLCD35(x) (BME_UBFX8(HW_LCD_WF35_ADDR(x), BP_LCD_WF35_BPDLCD35, BS_LCD_WF35_BPDLCD35))

/*! @brief Format value for bitfield LCD_WF35_BPDLCD35. */
#define BF_LCD_WF35_BPDLCD35(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF35_BPDLCD35) & BM_LCD_WF35_BPDLCD35)

/*! @brief Set the BPDLCD35 field to a new value. */
#define BW_LCD_WF35_BPDLCD35(x, v) (BME_BFI8(HW_LCD_WF35_ADDR(x), ((uint8_t)(v) << BP_LCD_WF35_BPDLCD35), BP_LCD_WF35_BPDLCD35, 1))
/*@}*/

/*!
 * @name Register LCD_WF35, field BPELCD35[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF35_BPELCD35 (4U)          /*!< Bit position for LCD_WF35_BPELCD35. */
#define BM_LCD_WF35_BPELCD35 (0x10U)       /*!< Bit mask for LCD_WF35_BPELCD35. */
#define BS_LCD_WF35_BPELCD35 (1U)          /*!< Bit field size in bits for LCD_WF35_BPELCD35. */

/*! @brief Read current value of the LCD_WF35_BPELCD35 field. */
#define BR_LCD_WF35_BPELCD35(x) (BME_UBFX8(HW_LCD_WF35_ADDR(x), BP_LCD_WF35_BPELCD35, BS_LCD_WF35_BPELCD35))

/*! @brief Format value for bitfield LCD_WF35_BPELCD35. */
#define BF_LCD_WF35_BPELCD35(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF35_BPELCD35) & BM_LCD_WF35_BPELCD35)

/*! @brief Set the BPELCD35 field to a new value. */
#define BW_LCD_WF35_BPELCD35(x, v) (BME_BFI8(HW_LCD_WF35_ADDR(x), ((uint8_t)(v) << BP_LCD_WF35_BPELCD35), BP_LCD_WF35_BPELCD35, 1))
/*@}*/

/*!
 * @name Register LCD_WF35, field BPFLCD35[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF35_BPFLCD35 (5U)          /*!< Bit position for LCD_WF35_BPFLCD35. */
#define BM_LCD_WF35_BPFLCD35 (0x20U)       /*!< Bit mask for LCD_WF35_BPFLCD35. */
#define BS_LCD_WF35_BPFLCD35 (1U)          /*!< Bit field size in bits for LCD_WF35_BPFLCD35. */

/*! @brief Read current value of the LCD_WF35_BPFLCD35 field. */
#define BR_LCD_WF35_BPFLCD35(x) (BME_UBFX8(HW_LCD_WF35_ADDR(x), BP_LCD_WF35_BPFLCD35, BS_LCD_WF35_BPFLCD35))

/*! @brief Format value for bitfield LCD_WF35_BPFLCD35. */
#define BF_LCD_WF35_BPFLCD35(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF35_BPFLCD35) & BM_LCD_WF35_BPFLCD35)

/*! @brief Set the BPFLCD35 field to a new value. */
#define BW_LCD_WF35_BPFLCD35(x, v) (BME_BFI8(HW_LCD_WF35_ADDR(x), ((uint8_t)(v) << BP_LCD_WF35_BPFLCD35), BP_LCD_WF35_BPFLCD35, 1))
/*@}*/

/*!
 * @name Register LCD_WF35, field BPGLCD35[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF35_BPGLCD35 (6U)          /*!< Bit position for LCD_WF35_BPGLCD35. */
#define BM_LCD_WF35_BPGLCD35 (0x40U)       /*!< Bit mask for LCD_WF35_BPGLCD35. */
#define BS_LCD_WF35_BPGLCD35 (1U)          /*!< Bit field size in bits for LCD_WF35_BPGLCD35. */

/*! @brief Read current value of the LCD_WF35_BPGLCD35 field. */
#define BR_LCD_WF35_BPGLCD35(x) (BME_UBFX8(HW_LCD_WF35_ADDR(x), BP_LCD_WF35_BPGLCD35, BS_LCD_WF35_BPGLCD35))

/*! @brief Format value for bitfield LCD_WF35_BPGLCD35. */
#define BF_LCD_WF35_BPGLCD35(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF35_BPGLCD35) & BM_LCD_WF35_BPGLCD35)

/*! @brief Set the BPGLCD35 field to a new value. */
#define BW_LCD_WF35_BPGLCD35(x, v) (BME_BFI8(HW_LCD_WF35_ADDR(x), ((uint8_t)(v) << BP_LCD_WF35_BPGLCD35), BP_LCD_WF35_BPGLCD35, 1))
/*@}*/

/*!
 * @name Register LCD_WF35, field BPHLCD35[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF35_BPHLCD35 (7U)          /*!< Bit position for LCD_WF35_BPHLCD35. */
#define BM_LCD_WF35_BPHLCD35 (0x80U)       /*!< Bit mask for LCD_WF35_BPHLCD35. */
#define BS_LCD_WF35_BPHLCD35 (1U)          /*!< Bit field size in bits for LCD_WF35_BPHLCD35. */

/*! @brief Read current value of the LCD_WF35_BPHLCD35 field. */
#define BR_LCD_WF35_BPHLCD35(x) (BME_UBFX8(HW_LCD_WF35_ADDR(x), BP_LCD_WF35_BPHLCD35, BS_LCD_WF35_BPHLCD35))

/*! @brief Format value for bitfield LCD_WF35_BPHLCD35. */
#define BF_LCD_WF35_BPHLCD35(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF35_BPHLCD35) & BM_LCD_WF35_BPHLCD35)

/*! @brief Set the BPHLCD35 field to a new value. */
#define BW_LCD_WF35_BPHLCD35(x, v) (BME_BFI8(HW_LCD_WF35_ADDR(x), ((uint8_t)(v) << BP_LCD_WF35_BPHLCD35), BP_LCD_WF35_BPHLCD35, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF36 - LCD Waveform Register 36.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF36 - LCD Waveform Register 36. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf36
{
    uint8_t U;
    struct _hw_lcd_wf36_bitfields
    {
        uint8_t BPALCD36 : 1;          /*!< [0]  */
        uint8_t BPBLCD36 : 1;          /*!< [1]  */
        uint8_t BPCLCD36 : 1;          /*!< [2]  */
        uint8_t BPDLCD36 : 1;          /*!< [3]  */
        uint8_t BPELCD36 : 1;          /*!< [4]  */
        uint8_t BPFLCD36 : 1;          /*!< [5]  */
        uint8_t BPGLCD36 : 1;          /*!< [6]  */
        uint8_t BPHLCD36 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf36_t;

/*!
 * @name Constants and macros for entire LCD_WF36 register
 */
/*@{*/
#define HW_LCD_WF36_ADDR(x)      ((x) + 0x44U)

#define HW_LCD_WF36(x)           (*(__IO hw_lcd_wf36_t *) HW_LCD_WF36_ADDR(x))
#define HW_LCD_WF36_RD(x)        (HW_LCD_WF36(x).U)
#define HW_LCD_WF36_WR(x, v)     (HW_LCD_WF36(x).U = (v))
#define HW_LCD_WF36_SET(x, v)    (BME_OR8(HW_LCD_WF36_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF36_CLR(x, v)    (BME_AND8(HW_LCD_WF36_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF36_TOG(x, v)    (BME_XOR8(HW_LCD_WF36_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF36 bitfields
 */

/*!
 * @name Register LCD_WF36, field BPALCD36[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF36_BPALCD36 (0U)          /*!< Bit position for LCD_WF36_BPALCD36. */
#define BM_LCD_WF36_BPALCD36 (0x01U)       /*!< Bit mask for LCD_WF36_BPALCD36. */
#define BS_LCD_WF36_BPALCD36 (1U)          /*!< Bit field size in bits for LCD_WF36_BPALCD36. */

/*! @brief Read current value of the LCD_WF36_BPALCD36 field. */
#define BR_LCD_WF36_BPALCD36(x) (BME_UBFX8(HW_LCD_WF36_ADDR(x), BP_LCD_WF36_BPALCD36, BS_LCD_WF36_BPALCD36))

/*! @brief Format value for bitfield LCD_WF36_BPALCD36. */
#define BF_LCD_WF36_BPALCD36(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF36_BPALCD36) & BM_LCD_WF36_BPALCD36)

/*! @brief Set the BPALCD36 field to a new value. */
#define BW_LCD_WF36_BPALCD36(x, v) (BME_BFI8(HW_LCD_WF36_ADDR(x), ((uint8_t)(v) << BP_LCD_WF36_BPALCD36), BP_LCD_WF36_BPALCD36, 1))
/*@}*/

/*!
 * @name Register LCD_WF36, field BPBLCD36[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF36_BPBLCD36 (1U)          /*!< Bit position for LCD_WF36_BPBLCD36. */
#define BM_LCD_WF36_BPBLCD36 (0x02U)       /*!< Bit mask for LCD_WF36_BPBLCD36. */
#define BS_LCD_WF36_BPBLCD36 (1U)          /*!< Bit field size in bits for LCD_WF36_BPBLCD36. */

/*! @brief Read current value of the LCD_WF36_BPBLCD36 field. */
#define BR_LCD_WF36_BPBLCD36(x) (BME_UBFX8(HW_LCD_WF36_ADDR(x), BP_LCD_WF36_BPBLCD36, BS_LCD_WF36_BPBLCD36))

/*! @brief Format value for bitfield LCD_WF36_BPBLCD36. */
#define BF_LCD_WF36_BPBLCD36(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF36_BPBLCD36) & BM_LCD_WF36_BPBLCD36)

/*! @brief Set the BPBLCD36 field to a new value. */
#define BW_LCD_WF36_BPBLCD36(x, v) (BME_BFI8(HW_LCD_WF36_ADDR(x), ((uint8_t)(v) << BP_LCD_WF36_BPBLCD36), BP_LCD_WF36_BPBLCD36, 1))
/*@}*/

/*!
 * @name Register LCD_WF36, field BPCLCD36[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF36_BPCLCD36 (2U)          /*!< Bit position for LCD_WF36_BPCLCD36. */
#define BM_LCD_WF36_BPCLCD36 (0x04U)       /*!< Bit mask for LCD_WF36_BPCLCD36. */
#define BS_LCD_WF36_BPCLCD36 (1U)          /*!< Bit field size in bits for LCD_WF36_BPCLCD36. */

/*! @brief Read current value of the LCD_WF36_BPCLCD36 field. */
#define BR_LCD_WF36_BPCLCD36(x) (BME_UBFX8(HW_LCD_WF36_ADDR(x), BP_LCD_WF36_BPCLCD36, BS_LCD_WF36_BPCLCD36))

/*! @brief Format value for bitfield LCD_WF36_BPCLCD36. */
#define BF_LCD_WF36_BPCLCD36(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF36_BPCLCD36) & BM_LCD_WF36_BPCLCD36)

/*! @brief Set the BPCLCD36 field to a new value. */
#define BW_LCD_WF36_BPCLCD36(x, v) (BME_BFI8(HW_LCD_WF36_ADDR(x), ((uint8_t)(v) << BP_LCD_WF36_BPCLCD36), BP_LCD_WF36_BPCLCD36, 1))
/*@}*/

/*!
 * @name Register LCD_WF36, field BPDLCD36[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF36_BPDLCD36 (3U)          /*!< Bit position for LCD_WF36_BPDLCD36. */
#define BM_LCD_WF36_BPDLCD36 (0x08U)       /*!< Bit mask for LCD_WF36_BPDLCD36. */
#define BS_LCD_WF36_BPDLCD36 (1U)          /*!< Bit field size in bits for LCD_WF36_BPDLCD36. */

/*! @brief Read current value of the LCD_WF36_BPDLCD36 field. */
#define BR_LCD_WF36_BPDLCD36(x) (BME_UBFX8(HW_LCD_WF36_ADDR(x), BP_LCD_WF36_BPDLCD36, BS_LCD_WF36_BPDLCD36))

/*! @brief Format value for bitfield LCD_WF36_BPDLCD36. */
#define BF_LCD_WF36_BPDLCD36(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF36_BPDLCD36) & BM_LCD_WF36_BPDLCD36)

/*! @brief Set the BPDLCD36 field to a new value. */
#define BW_LCD_WF36_BPDLCD36(x, v) (BME_BFI8(HW_LCD_WF36_ADDR(x), ((uint8_t)(v) << BP_LCD_WF36_BPDLCD36), BP_LCD_WF36_BPDLCD36, 1))
/*@}*/

/*!
 * @name Register LCD_WF36, field BPELCD36[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF36_BPELCD36 (4U)          /*!< Bit position for LCD_WF36_BPELCD36. */
#define BM_LCD_WF36_BPELCD36 (0x10U)       /*!< Bit mask for LCD_WF36_BPELCD36. */
#define BS_LCD_WF36_BPELCD36 (1U)          /*!< Bit field size in bits for LCD_WF36_BPELCD36. */

/*! @brief Read current value of the LCD_WF36_BPELCD36 field. */
#define BR_LCD_WF36_BPELCD36(x) (BME_UBFX8(HW_LCD_WF36_ADDR(x), BP_LCD_WF36_BPELCD36, BS_LCD_WF36_BPELCD36))

/*! @brief Format value for bitfield LCD_WF36_BPELCD36. */
#define BF_LCD_WF36_BPELCD36(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF36_BPELCD36) & BM_LCD_WF36_BPELCD36)

/*! @brief Set the BPELCD36 field to a new value. */
#define BW_LCD_WF36_BPELCD36(x, v) (BME_BFI8(HW_LCD_WF36_ADDR(x), ((uint8_t)(v) << BP_LCD_WF36_BPELCD36), BP_LCD_WF36_BPELCD36, 1))
/*@}*/

/*!
 * @name Register LCD_WF36, field BPFLCD36[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF36_BPFLCD36 (5U)          /*!< Bit position for LCD_WF36_BPFLCD36. */
#define BM_LCD_WF36_BPFLCD36 (0x20U)       /*!< Bit mask for LCD_WF36_BPFLCD36. */
#define BS_LCD_WF36_BPFLCD36 (1U)          /*!< Bit field size in bits for LCD_WF36_BPFLCD36. */

/*! @brief Read current value of the LCD_WF36_BPFLCD36 field. */
#define BR_LCD_WF36_BPFLCD36(x) (BME_UBFX8(HW_LCD_WF36_ADDR(x), BP_LCD_WF36_BPFLCD36, BS_LCD_WF36_BPFLCD36))

/*! @brief Format value for bitfield LCD_WF36_BPFLCD36. */
#define BF_LCD_WF36_BPFLCD36(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF36_BPFLCD36) & BM_LCD_WF36_BPFLCD36)

/*! @brief Set the BPFLCD36 field to a new value. */
#define BW_LCD_WF36_BPFLCD36(x, v) (BME_BFI8(HW_LCD_WF36_ADDR(x), ((uint8_t)(v) << BP_LCD_WF36_BPFLCD36), BP_LCD_WF36_BPFLCD36, 1))
/*@}*/

/*!
 * @name Register LCD_WF36, field BPGLCD36[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF36_BPGLCD36 (6U)          /*!< Bit position for LCD_WF36_BPGLCD36. */
#define BM_LCD_WF36_BPGLCD36 (0x40U)       /*!< Bit mask for LCD_WF36_BPGLCD36. */
#define BS_LCD_WF36_BPGLCD36 (1U)          /*!< Bit field size in bits for LCD_WF36_BPGLCD36. */

/*! @brief Read current value of the LCD_WF36_BPGLCD36 field. */
#define BR_LCD_WF36_BPGLCD36(x) (BME_UBFX8(HW_LCD_WF36_ADDR(x), BP_LCD_WF36_BPGLCD36, BS_LCD_WF36_BPGLCD36))

/*! @brief Format value for bitfield LCD_WF36_BPGLCD36. */
#define BF_LCD_WF36_BPGLCD36(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF36_BPGLCD36) & BM_LCD_WF36_BPGLCD36)

/*! @brief Set the BPGLCD36 field to a new value. */
#define BW_LCD_WF36_BPGLCD36(x, v) (BME_BFI8(HW_LCD_WF36_ADDR(x), ((uint8_t)(v) << BP_LCD_WF36_BPGLCD36), BP_LCD_WF36_BPGLCD36, 1))
/*@}*/

/*!
 * @name Register LCD_WF36, field BPHLCD36[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF36_BPHLCD36 (7U)          /*!< Bit position for LCD_WF36_BPHLCD36. */
#define BM_LCD_WF36_BPHLCD36 (0x80U)       /*!< Bit mask for LCD_WF36_BPHLCD36. */
#define BS_LCD_WF36_BPHLCD36 (1U)          /*!< Bit field size in bits for LCD_WF36_BPHLCD36. */

/*! @brief Read current value of the LCD_WF36_BPHLCD36 field. */
#define BR_LCD_WF36_BPHLCD36(x) (BME_UBFX8(HW_LCD_WF36_ADDR(x), BP_LCD_WF36_BPHLCD36, BS_LCD_WF36_BPHLCD36))

/*! @brief Format value for bitfield LCD_WF36_BPHLCD36. */
#define BF_LCD_WF36_BPHLCD36(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF36_BPHLCD36) & BM_LCD_WF36_BPHLCD36)

/*! @brief Set the BPHLCD36 field to a new value. */
#define BW_LCD_WF36_BPHLCD36(x, v) (BME_BFI8(HW_LCD_WF36_ADDR(x), ((uint8_t)(v) << BP_LCD_WF36_BPHLCD36), BP_LCD_WF36_BPHLCD36, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF37 - LCD Waveform Register 37.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF37 - LCD Waveform Register 37. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf37
{
    uint8_t U;
    struct _hw_lcd_wf37_bitfields
    {
        uint8_t BPALCD37 : 1;          /*!< [0]  */
        uint8_t BPBLCD37 : 1;          /*!< [1]  */
        uint8_t BPCLCD37 : 1;          /*!< [2]  */
        uint8_t BPDLCD37 : 1;          /*!< [3]  */
        uint8_t BPELCD37 : 1;          /*!< [4]  */
        uint8_t BPFLCD37 : 1;          /*!< [5]  */
        uint8_t BPGLCD37 : 1;          /*!< [6]  */
        uint8_t BPHLCD37 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf37_t;

/*!
 * @name Constants and macros for entire LCD_WF37 register
 */
/*@{*/
#define HW_LCD_WF37_ADDR(x)      ((x) + 0x45U)

#define HW_LCD_WF37(x)           (*(__IO hw_lcd_wf37_t *) HW_LCD_WF37_ADDR(x))
#define HW_LCD_WF37_RD(x)        (HW_LCD_WF37(x).U)
#define HW_LCD_WF37_WR(x, v)     (HW_LCD_WF37(x).U = (v))
#define HW_LCD_WF37_SET(x, v)    (BME_OR8(HW_LCD_WF37_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF37_CLR(x, v)    (BME_AND8(HW_LCD_WF37_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF37_TOG(x, v)    (BME_XOR8(HW_LCD_WF37_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF37 bitfields
 */

/*!
 * @name Register LCD_WF37, field BPALCD37[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF37_BPALCD37 (0U)          /*!< Bit position for LCD_WF37_BPALCD37. */
#define BM_LCD_WF37_BPALCD37 (0x01U)       /*!< Bit mask for LCD_WF37_BPALCD37. */
#define BS_LCD_WF37_BPALCD37 (1U)          /*!< Bit field size in bits for LCD_WF37_BPALCD37. */

/*! @brief Read current value of the LCD_WF37_BPALCD37 field. */
#define BR_LCD_WF37_BPALCD37(x) (BME_UBFX8(HW_LCD_WF37_ADDR(x), BP_LCD_WF37_BPALCD37, BS_LCD_WF37_BPALCD37))

/*! @brief Format value for bitfield LCD_WF37_BPALCD37. */
#define BF_LCD_WF37_BPALCD37(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF37_BPALCD37) & BM_LCD_WF37_BPALCD37)

/*! @brief Set the BPALCD37 field to a new value. */
#define BW_LCD_WF37_BPALCD37(x, v) (BME_BFI8(HW_LCD_WF37_ADDR(x), ((uint8_t)(v) << BP_LCD_WF37_BPALCD37), BP_LCD_WF37_BPALCD37, 1))
/*@}*/

/*!
 * @name Register LCD_WF37, field BPBLCD37[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF37_BPBLCD37 (1U)          /*!< Bit position for LCD_WF37_BPBLCD37. */
#define BM_LCD_WF37_BPBLCD37 (0x02U)       /*!< Bit mask for LCD_WF37_BPBLCD37. */
#define BS_LCD_WF37_BPBLCD37 (1U)          /*!< Bit field size in bits for LCD_WF37_BPBLCD37. */

/*! @brief Read current value of the LCD_WF37_BPBLCD37 field. */
#define BR_LCD_WF37_BPBLCD37(x) (BME_UBFX8(HW_LCD_WF37_ADDR(x), BP_LCD_WF37_BPBLCD37, BS_LCD_WF37_BPBLCD37))

/*! @brief Format value for bitfield LCD_WF37_BPBLCD37. */
#define BF_LCD_WF37_BPBLCD37(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF37_BPBLCD37) & BM_LCD_WF37_BPBLCD37)

/*! @brief Set the BPBLCD37 field to a new value. */
#define BW_LCD_WF37_BPBLCD37(x, v) (BME_BFI8(HW_LCD_WF37_ADDR(x), ((uint8_t)(v) << BP_LCD_WF37_BPBLCD37), BP_LCD_WF37_BPBLCD37, 1))
/*@}*/

/*!
 * @name Register LCD_WF37, field BPCLCD37[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF37_BPCLCD37 (2U)          /*!< Bit position for LCD_WF37_BPCLCD37. */
#define BM_LCD_WF37_BPCLCD37 (0x04U)       /*!< Bit mask for LCD_WF37_BPCLCD37. */
#define BS_LCD_WF37_BPCLCD37 (1U)          /*!< Bit field size in bits for LCD_WF37_BPCLCD37. */

/*! @brief Read current value of the LCD_WF37_BPCLCD37 field. */
#define BR_LCD_WF37_BPCLCD37(x) (BME_UBFX8(HW_LCD_WF37_ADDR(x), BP_LCD_WF37_BPCLCD37, BS_LCD_WF37_BPCLCD37))

/*! @brief Format value for bitfield LCD_WF37_BPCLCD37. */
#define BF_LCD_WF37_BPCLCD37(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF37_BPCLCD37) & BM_LCD_WF37_BPCLCD37)

/*! @brief Set the BPCLCD37 field to a new value. */
#define BW_LCD_WF37_BPCLCD37(x, v) (BME_BFI8(HW_LCD_WF37_ADDR(x), ((uint8_t)(v) << BP_LCD_WF37_BPCLCD37), BP_LCD_WF37_BPCLCD37, 1))
/*@}*/

/*!
 * @name Register LCD_WF37, field BPDLCD37[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF37_BPDLCD37 (3U)          /*!< Bit position for LCD_WF37_BPDLCD37. */
#define BM_LCD_WF37_BPDLCD37 (0x08U)       /*!< Bit mask for LCD_WF37_BPDLCD37. */
#define BS_LCD_WF37_BPDLCD37 (1U)          /*!< Bit field size in bits for LCD_WF37_BPDLCD37. */

/*! @brief Read current value of the LCD_WF37_BPDLCD37 field. */
#define BR_LCD_WF37_BPDLCD37(x) (BME_UBFX8(HW_LCD_WF37_ADDR(x), BP_LCD_WF37_BPDLCD37, BS_LCD_WF37_BPDLCD37))

/*! @brief Format value for bitfield LCD_WF37_BPDLCD37. */
#define BF_LCD_WF37_BPDLCD37(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF37_BPDLCD37) & BM_LCD_WF37_BPDLCD37)

/*! @brief Set the BPDLCD37 field to a new value. */
#define BW_LCD_WF37_BPDLCD37(x, v) (BME_BFI8(HW_LCD_WF37_ADDR(x), ((uint8_t)(v) << BP_LCD_WF37_BPDLCD37), BP_LCD_WF37_BPDLCD37, 1))
/*@}*/

/*!
 * @name Register LCD_WF37, field BPELCD37[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF37_BPELCD37 (4U)          /*!< Bit position for LCD_WF37_BPELCD37. */
#define BM_LCD_WF37_BPELCD37 (0x10U)       /*!< Bit mask for LCD_WF37_BPELCD37. */
#define BS_LCD_WF37_BPELCD37 (1U)          /*!< Bit field size in bits for LCD_WF37_BPELCD37. */

/*! @brief Read current value of the LCD_WF37_BPELCD37 field. */
#define BR_LCD_WF37_BPELCD37(x) (BME_UBFX8(HW_LCD_WF37_ADDR(x), BP_LCD_WF37_BPELCD37, BS_LCD_WF37_BPELCD37))

/*! @brief Format value for bitfield LCD_WF37_BPELCD37. */
#define BF_LCD_WF37_BPELCD37(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF37_BPELCD37) & BM_LCD_WF37_BPELCD37)

/*! @brief Set the BPELCD37 field to a new value. */
#define BW_LCD_WF37_BPELCD37(x, v) (BME_BFI8(HW_LCD_WF37_ADDR(x), ((uint8_t)(v) << BP_LCD_WF37_BPELCD37), BP_LCD_WF37_BPELCD37, 1))
/*@}*/

/*!
 * @name Register LCD_WF37, field BPFLCD37[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF37_BPFLCD37 (5U)          /*!< Bit position for LCD_WF37_BPFLCD37. */
#define BM_LCD_WF37_BPFLCD37 (0x20U)       /*!< Bit mask for LCD_WF37_BPFLCD37. */
#define BS_LCD_WF37_BPFLCD37 (1U)          /*!< Bit field size in bits for LCD_WF37_BPFLCD37. */

/*! @brief Read current value of the LCD_WF37_BPFLCD37 field. */
#define BR_LCD_WF37_BPFLCD37(x) (BME_UBFX8(HW_LCD_WF37_ADDR(x), BP_LCD_WF37_BPFLCD37, BS_LCD_WF37_BPFLCD37))

/*! @brief Format value for bitfield LCD_WF37_BPFLCD37. */
#define BF_LCD_WF37_BPFLCD37(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF37_BPFLCD37) & BM_LCD_WF37_BPFLCD37)

/*! @brief Set the BPFLCD37 field to a new value. */
#define BW_LCD_WF37_BPFLCD37(x, v) (BME_BFI8(HW_LCD_WF37_ADDR(x), ((uint8_t)(v) << BP_LCD_WF37_BPFLCD37), BP_LCD_WF37_BPFLCD37, 1))
/*@}*/

/*!
 * @name Register LCD_WF37, field BPGLCD37[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF37_BPGLCD37 (6U)          /*!< Bit position for LCD_WF37_BPGLCD37. */
#define BM_LCD_WF37_BPGLCD37 (0x40U)       /*!< Bit mask for LCD_WF37_BPGLCD37. */
#define BS_LCD_WF37_BPGLCD37 (1U)          /*!< Bit field size in bits for LCD_WF37_BPGLCD37. */

/*! @brief Read current value of the LCD_WF37_BPGLCD37 field. */
#define BR_LCD_WF37_BPGLCD37(x) (BME_UBFX8(HW_LCD_WF37_ADDR(x), BP_LCD_WF37_BPGLCD37, BS_LCD_WF37_BPGLCD37))

/*! @brief Format value for bitfield LCD_WF37_BPGLCD37. */
#define BF_LCD_WF37_BPGLCD37(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF37_BPGLCD37) & BM_LCD_WF37_BPGLCD37)

/*! @brief Set the BPGLCD37 field to a new value. */
#define BW_LCD_WF37_BPGLCD37(x, v) (BME_BFI8(HW_LCD_WF37_ADDR(x), ((uint8_t)(v) << BP_LCD_WF37_BPGLCD37), BP_LCD_WF37_BPGLCD37, 1))
/*@}*/

/*!
 * @name Register LCD_WF37, field BPHLCD37[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF37_BPHLCD37 (7U)          /*!< Bit position for LCD_WF37_BPHLCD37. */
#define BM_LCD_WF37_BPHLCD37 (0x80U)       /*!< Bit mask for LCD_WF37_BPHLCD37. */
#define BS_LCD_WF37_BPHLCD37 (1U)          /*!< Bit field size in bits for LCD_WF37_BPHLCD37. */

/*! @brief Read current value of the LCD_WF37_BPHLCD37 field. */
#define BR_LCD_WF37_BPHLCD37(x) (BME_UBFX8(HW_LCD_WF37_ADDR(x), BP_LCD_WF37_BPHLCD37, BS_LCD_WF37_BPHLCD37))

/*! @brief Format value for bitfield LCD_WF37_BPHLCD37. */
#define BF_LCD_WF37_BPHLCD37(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF37_BPHLCD37) & BM_LCD_WF37_BPHLCD37)

/*! @brief Set the BPHLCD37 field to a new value. */
#define BW_LCD_WF37_BPHLCD37(x, v) (BME_BFI8(HW_LCD_WF37_ADDR(x), ((uint8_t)(v) << BP_LCD_WF37_BPHLCD37), BP_LCD_WF37_BPHLCD37, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF38 - LCD Waveform Register 38.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF38 - LCD Waveform Register 38. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf38
{
    uint8_t U;
    struct _hw_lcd_wf38_bitfields
    {
        uint8_t BPALCD38 : 1;          /*!< [0]  */
        uint8_t BPBLCD38 : 1;          /*!< [1]  */
        uint8_t BPCLCD38 : 1;          /*!< [2]  */
        uint8_t BPDLCD38 : 1;          /*!< [3]  */
        uint8_t BPELCD38 : 1;          /*!< [4]  */
        uint8_t BPFLCD38 : 1;          /*!< [5]  */
        uint8_t BPGLCD38 : 1;          /*!< [6]  */
        uint8_t BPHLCD38 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf38_t;

/*!
 * @name Constants and macros for entire LCD_WF38 register
 */
/*@{*/
#define HW_LCD_WF38_ADDR(x)      ((x) + 0x46U)

#define HW_LCD_WF38(x)           (*(__IO hw_lcd_wf38_t *) HW_LCD_WF38_ADDR(x))
#define HW_LCD_WF38_RD(x)        (HW_LCD_WF38(x).U)
#define HW_LCD_WF38_WR(x, v)     (HW_LCD_WF38(x).U = (v))
#define HW_LCD_WF38_SET(x, v)    (BME_OR8(HW_LCD_WF38_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF38_CLR(x, v)    (BME_AND8(HW_LCD_WF38_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF38_TOG(x, v)    (BME_XOR8(HW_LCD_WF38_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF38 bitfields
 */

/*!
 * @name Register LCD_WF38, field BPALCD38[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF38_BPALCD38 (0U)          /*!< Bit position for LCD_WF38_BPALCD38. */
#define BM_LCD_WF38_BPALCD38 (0x01U)       /*!< Bit mask for LCD_WF38_BPALCD38. */
#define BS_LCD_WF38_BPALCD38 (1U)          /*!< Bit field size in bits for LCD_WF38_BPALCD38. */

/*! @brief Read current value of the LCD_WF38_BPALCD38 field. */
#define BR_LCD_WF38_BPALCD38(x) (BME_UBFX8(HW_LCD_WF38_ADDR(x), BP_LCD_WF38_BPALCD38, BS_LCD_WF38_BPALCD38))

/*! @brief Format value for bitfield LCD_WF38_BPALCD38. */
#define BF_LCD_WF38_BPALCD38(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF38_BPALCD38) & BM_LCD_WF38_BPALCD38)

/*! @brief Set the BPALCD38 field to a new value. */
#define BW_LCD_WF38_BPALCD38(x, v) (BME_BFI8(HW_LCD_WF38_ADDR(x), ((uint8_t)(v) << BP_LCD_WF38_BPALCD38), BP_LCD_WF38_BPALCD38, 1))
/*@}*/

/*!
 * @name Register LCD_WF38, field BPBLCD38[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF38_BPBLCD38 (1U)          /*!< Bit position for LCD_WF38_BPBLCD38. */
#define BM_LCD_WF38_BPBLCD38 (0x02U)       /*!< Bit mask for LCD_WF38_BPBLCD38. */
#define BS_LCD_WF38_BPBLCD38 (1U)          /*!< Bit field size in bits for LCD_WF38_BPBLCD38. */

/*! @brief Read current value of the LCD_WF38_BPBLCD38 field. */
#define BR_LCD_WF38_BPBLCD38(x) (BME_UBFX8(HW_LCD_WF38_ADDR(x), BP_LCD_WF38_BPBLCD38, BS_LCD_WF38_BPBLCD38))

/*! @brief Format value for bitfield LCD_WF38_BPBLCD38. */
#define BF_LCD_WF38_BPBLCD38(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF38_BPBLCD38) & BM_LCD_WF38_BPBLCD38)

/*! @brief Set the BPBLCD38 field to a new value. */
#define BW_LCD_WF38_BPBLCD38(x, v) (BME_BFI8(HW_LCD_WF38_ADDR(x), ((uint8_t)(v) << BP_LCD_WF38_BPBLCD38), BP_LCD_WF38_BPBLCD38, 1))
/*@}*/

/*!
 * @name Register LCD_WF38, field BPCLCD38[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF38_BPCLCD38 (2U)          /*!< Bit position for LCD_WF38_BPCLCD38. */
#define BM_LCD_WF38_BPCLCD38 (0x04U)       /*!< Bit mask for LCD_WF38_BPCLCD38. */
#define BS_LCD_WF38_BPCLCD38 (1U)          /*!< Bit field size in bits for LCD_WF38_BPCLCD38. */

/*! @brief Read current value of the LCD_WF38_BPCLCD38 field. */
#define BR_LCD_WF38_BPCLCD38(x) (BME_UBFX8(HW_LCD_WF38_ADDR(x), BP_LCD_WF38_BPCLCD38, BS_LCD_WF38_BPCLCD38))

/*! @brief Format value for bitfield LCD_WF38_BPCLCD38. */
#define BF_LCD_WF38_BPCLCD38(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF38_BPCLCD38) & BM_LCD_WF38_BPCLCD38)

/*! @brief Set the BPCLCD38 field to a new value. */
#define BW_LCD_WF38_BPCLCD38(x, v) (BME_BFI8(HW_LCD_WF38_ADDR(x), ((uint8_t)(v) << BP_LCD_WF38_BPCLCD38), BP_LCD_WF38_BPCLCD38, 1))
/*@}*/

/*!
 * @name Register LCD_WF38, field BPDLCD38[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF38_BPDLCD38 (3U)          /*!< Bit position for LCD_WF38_BPDLCD38. */
#define BM_LCD_WF38_BPDLCD38 (0x08U)       /*!< Bit mask for LCD_WF38_BPDLCD38. */
#define BS_LCD_WF38_BPDLCD38 (1U)          /*!< Bit field size in bits for LCD_WF38_BPDLCD38. */

/*! @brief Read current value of the LCD_WF38_BPDLCD38 field. */
#define BR_LCD_WF38_BPDLCD38(x) (BME_UBFX8(HW_LCD_WF38_ADDR(x), BP_LCD_WF38_BPDLCD38, BS_LCD_WF38_BPDLCD38))

/*! @brief Format value for bitfield LCD_WF38_BPDLCD38. */
#define BF_LCD_WF38_BPDLCD38(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF38_BPDLCD38) & BM_LCD_WF38_BPDLCD38)

/*! @brief Set the BPDLCD38 field to a new value. */
#define BW_LCD_WF38_BPDLCD38(x, v) (BME_BFI8(HW_LCD_WF38_ADDR(x), ((uint8_t)(v) << BP_LCD_WF38_BPDLCD38), BP_LCD_WF38_BPDLCD38, 1))
/*@}*/

/*!
 * @name Register LCD_WF38, field BPELCD38[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF38_BPELCD38 (4U)          /*!< Bit position for LCD_WF38_BPELCD38. */
#define BM_LCD_WF38_BPELCD38 (0x10U)       /*!< Bit mask for LCD_WF38_BPELCD38. */
#define BS_LCD_WF38_BPELCD38 (1U)          /*!< Bit field size in bits for LCD_WF38_BPELCD38. */

/*! @brief Read current value of the LCD_WF38_BPELCD38 field. */
#define BR_LCD_WF38_BPELCD38(x) (BME_UBFX8(HW_LCD_WF38_ADDR(x), BP_LCD_WF38_BPELCD38, BS_LCD_WF38_BPELCD38))

/*! @brief Format value for bitfield LCD_WF38_BPELCD38. */
#define BF_LCD_WF38_BPELCD38(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF38_BPELCD38) & BM_LCD_WF38_BPELCD38)

/*! @brief Set the BPELCD38 field to a new value. */
#define BW_LCD_WF38_BPELCD38(x, v) (BME_BFI8(HW_LCD_WF38_ADDR(x), ((uint8_t)(v) << BP_LCD_WF38_BPELCD38), BP_LCD_WF38_BPELCD38, 1))
/*@}*/

/*!
 * @name Register LCD_WF38, field BPFLCD38[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF38_BPFLCD38 (5U)          /*!< Bit position for LCD_WF38_BPFLCD38. */
#define BM_LCD_WF38_BPFLCD38 (0x20U)       /*!< Bit mask for LCD_WF38_BPFLCD38. */
#define BS_LCD_WF38_BPFLCD38 (1U)          /*!< Bit field size in bits for LCD_WF38_BPFLCD38. */

/*! @brief Read current value of the LCD_WF38_BPFLCD38 field. */
#define BR_LCD_WF38_BPFLCD38(x) (BME_UBFX8(HW_LCD_WF38_ADDR(x), BP_LCD_WF38_BPFLCD38, BS_LCD_WF38_BPFLCD38))

/*! @brief Format value for bitfield LCD_WF38_BPFLCD38. */
#define BF_LCD_WF38_BPFLCD38(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF38_BPFLCD38) & BM_LCD_WF38_BPFLCD38)

/*! @brief Set the BPFLCD38 field to a new value. */
#define BW_LCD_WF38_BPFLCD38(x, v) (BME_BFI8(HW_LCD_WF38_ADDR(x), ((uint8_t)(v) << BP_LCD_WF38_BPFLCD38), BP_LCD_WF38_BPFLCD38, 1))
/*@}*/

/*!
 * @name Register LCD_WF38, field BPGLCD38[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF38_BPGLCD38 (6U)          /*!< Bit position for LCD_WF38_BPGLCD38. */
#define BM_LCD_WF38_BPGLCD38 (0x40U)       /*!< Bit mask for LCD_WF38_BPGLCD38. */
#define BS_LCD_WF38_BPGLCD38 (1U)          /*!< Bit field size in bits for LCD_WF38_BPGLCD38. */

/*! @brief Read current value of the LCD_WF38_BPGLCD38 field. */
#define BR_LCD_WF38_BPGLCD38(x) (BME_UBFX8(HW_LCD_WF38_ADDR(x), BP_LCD_WF38_BPGLCD38, BS_LCD_WF38_BPGLCD38))

/*! @brief Format value for bitfield LCD_WF38_BPGLCD38. */
#define BF_LCD_WF38_BPGLCD38(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF38_BPGLCD38) & BM_LCD_WF38_BPGLCD38)

/*! @brief Set the BPGLCD38 field to a new value. */
#define BW_LCD_WF38_BPGLCD38(x, v) (BME_BFI8(HW_LCD_WF38_ADDR(x), ((uint8_t)(v) << BP_LCD_WF38_BPGLCD38), BP_LCD_WF38_BPGLCD38, 1))
/*@}*/

/*!
 * @name Register LCD_WF38, field BPHLCD38[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF38_BPHLCD38 (7U)          /*!< Bit position for LCD_WF38_BPHLCD38. */
#define BM_LCD_WF38_BPHLCD38 (0x80U)       /*!< Bit mask for LCD_WF38_BPHLCD38. */
#define BS_LCD_WF38_BPHLCD38 (1U)          /*!< Bit field size in bits for LCD_WF38_BPHLCD38. */

/*! @brief Read current value of the LCD_WF38_BPHLCD38 field. */
#define BR_LCD_WF38_BPHLCD38(x) (BME_UBFX8(HW_LCD_WF38_ADDR(x), BP_LCD_WF38_BPHLCD38, BS_LCD_WF38_BPHLCD38))

/*! @brief Format value for bitfield LCD_WF38_BPHLCD38. */
#define BF_LCD_WF38_BPHLCD38(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF38_BPHLCD38) & BM_LCD_WF38_BPHLCD38)

/*! @brief Set the BPHLCD38 field to a new value. */
#define BW_LCD_WF38_BPHLCD38(x, v) (BME_BFI8(HW_LCD_WF38_ADDR(x), ((uint8_t)(v) << BP_LCD_WF38_BPHLCD38), BP_LCD_WF38_BPHLCD38, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF39 - LCD Waveform Register 39.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF39 - LCD Waveform Register 39. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf39
{
    uint8_t U;
    struct _hw_lcd_wf39_bitfields
    {
        uint8_t BPALCD39 : 1;          /*!< [0]  */
        uint8_t BPBLCD39 : 1;          /*!< [1]  */
        uint8_t BPCLCD39 : 1;          /*!< [2]  */
        uint8_t BPDLCD39 : 1;          /*!< [3]  */
        uint8_t BPELCD39 : 1;          /*!< [4]  */
        uint8_t BPFLCD39 : 1;          /*!< [5]  */
        uint8_t BPGLCD39 : 1;          /*!< [6]  */
        uint8_t BPHLCD39 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf39_t;

/*!
 * @name Constants and macros for entire LCD_WF39 register
 */
/*@{*/
#define HW_LCD_WF39_ADDR(x)      ((x) + 0x47U)

#define HW_LCD_WF39(x)           (*(__IO hw_lcd_wf39_t *) HW_LCD_WF39_ADDR(x))
#define HW_LCD_WF39_RD(x)        (HW_LCD_WF39(x).U)
#define HW_LCD_WF39_WR(x, v)     (HW_LCD_WF39(x).U = (v))
#define HW_LCD_WF39_SET(x, v)    (BME_OR8(HW_LCD_WF39_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF39_CLR(x, v)    (BME_AND8(HW_LCD_WF39_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF39_TOG(x, v)    (BME_XOR8(HW_LCD_WF39_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF39 bitfields
 */

/*!
 * @name Register LCD_WF39, field BPALCD39[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF39_BPALCD39 (0U)          /*!< Bit position for LCD_WF39_BPALCD39. */
#define BM_LCD_WF39_BPALCD39 (0x01U)       /*!< Bit mask for LCD_WF39_BPALCD39. */
#define BS_LCD_WF39_BPALCD39 (1U)          /*!< Bit field size in bits for LCD_WF39_BPALCD39. */

/*! @brief Read current value of the LCD_WF39_BPALCD39 field. */
#define BR_LCD_WF39_BPALCD39(x) (BME_UBFX8(HW_LCD_WF39_ADDR(x), BP_LCD_WF39_BPALCD39, BS_LCD_WF39_BPALCD39))

/*! @brief Format value for bitfield LCD_WF39_BPALCD39. */
#define BF_LCD_WF39_BPALCD39(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF39_BPALCD39) & BM_LCD_WF39_BPALCD39)

/*! @brief Set the BPALCD39 field to a new value. */
#define BW_LCD_WF39_BPALCD39(x, v) (BME_BFI8(HW_LCD_WF39_ADDR(x), ((uint8_t)(v) << BP_LCD_WF39_BPALCD39), BP_LCD_WF39_BPALCD39, 1))
/*@}*/

/*!
 * @name Register LCD_WF39, field BPBLCD39[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF39_BPBLCD39 (1U)          /*!< Bit position for LCD_WF39_BPBLCD39. */
#define BM_LCD_WF39_BPBLCD39 (0x02U)       /*!< Bit mask for LCD_WF39_BPBLCD39. */
#define BS_LCD_WF39_BPBLCD39 (1U)          /*!< Bit field size in bits for LCD_WF39_BPBLCD39. */

/*! @brief Read current value of the LCD_WF39_BPBLCD39 field. */
#define BR_LCD_WF39_BPBLCD39(x) (BME_UBFX8(HW_LCD_WF39_ADDR(x), BP_LCD_WF39_BPBLCD39, BS_LCD_WF39_BPBLCD39))

/*! @brief Format value for bitfield LCD_WF39_BPBLCD39. */
#define BF_LCD_WF39_BPBLCD39(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF39_BPBLCD39) & BM_LCD_WF39_BPBLCD39)

/*! @brief Set the BPBLCD39 field to a new value. */
#define BW_LCD_WF39_BPBLCD39(x, v) (BME_BFI8(HW_LCD_WF39_ADDR(x), ((uint8_t)(v) << BP_LCD_WF39_BPBLCD39), BP_LCD_WF39_BPBLCD39, 1))
/*@}*/

/*!
 * @name Register LCD_WF39, field BPCLCD39[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF39_BPCLCD39 (2U)          /*!< Bit position for LCD_WF39_BPCLCD39. */
#define BM_LCD_WF39_BPCLCD39 (0x04U)       /*!< Bit mask for LCD_WF39_BPCLCD39. */
#define BS_LCD_WF39_BPCLCD39 (1U)          /*!< Bit field size in bits for LCD_WF39_BPCLCD39. */

/*! @brief Read current value of the LCD_WF39_BPCLCD39 field. */
#define BR_LCD_WF39_BPCLCD39(x) (BME_UBFX8(HW_LCD_WF39_ADDR(x), BP_LCD_WF39_BPCLCD39, BS_LCD_WF39_BPCLCD39))

/*! @brief Format value for bitfield LCD_WF39_BPCLCD39. */
#define BF_LCD_WF39_BPCLCD39(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF39_BPCLCD39) & BM_LCD_WF39_BPCLCD39)

/*! @brief Set the BPCLCD39 field to a new value. */
#define BW_LCD_WF39_BPCLCD39(x, v) (BME_BFI8(HW_LCD_WF39_ADDR(x), ((uint8_t)(v) << BP_LCD_WF39_BPCLCD39), BP_LCD_WF39_BPCLCD39, 1))
/*@}*/

/*!
 * @name Register LCD_WF39, field BPDLCD39[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF39_BPDLCD39 (3U)          /*!< Bit position for LCD_WF39_BPDLCD39. */
#define BM_LCD_WF39_BPDLCD39 (0x08U)       /*!< Bit mask for LCD_WF39_BPDLCD39. */
#define BS_LCD_WF39_BPDLCD39 (1U)          /*!< Bit field size in bits for LCD_WF39_BPDLCD39. */

/*! @brief Read current value of the LCD_WF39_BPDLCD39 field. */
#define BR_LCD_WF39_BPDLCD39(x) (BME_UBFX8(HW_LCD_WF39_ADDR(x), BP_LCD_WF39_BPDLCD39, BS_LCD_WF39_BPDLCD39))

/*! @brief Format value for bitfield LCD_WF39_BPDLCD39. */
#define BF_LCD_WF39_BPDLCD39(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF39_BPDLCD39) & BM_LCD_WF39_BPDLCD39)

/*! @brief Set the BPDLCD39 field to a new value. */
#define BW_LCD_WF39_BPDLCD39(x, v) (BME_BFI8(HW_LCD_WF39_ADDR(x), ((uint8_t)(v) << BP_LCD_WF39_BPDLCD39), BP_LCD_WF39_BPDLCD39, 1))
/*@}*/

/*!
 * @name Register LCD_WF39, field BPELCD39[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF39_BPELCD39 (4U)          /*!< Bit position for LCD_WF39_BPELCD39. */
#define BM_LCD_WF39_BPELCD39 (0x10U)       /*!< Bit mask for LCD_WF39_BPELCD39. */
#define BS_LCD_WF39_BPELCD39 (1U)          /*!< Bit field size in bits for LCD_WF39_BPELCD39. */

/*! @brief Read current value of the LCD_WF39_BPELCD39 field. */
#define BR_LCD_WF39_BPELCD39(x) (BME_UBFX8(HW_LCD_WF39_ADDR(x), BP_LCD_WF39_BPELCD39, BS_LCD_WF39_BPELCD39))

/*! @brief Format value for bitfield LCD_WF39_BPELCD39. */
#define BF_LCD_WF39_BPELCD39(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF39_BPELCD39) & BM_LCD_WF39_BPELCD39)

/*! @brief Set the BPELCD39 field to a new value. */
#define BW_LCD_WF39_BPELCD39(x, v) (BME_BFI8(HW_LCD_WF39_ADDR(x), ((uint8_t)(v) << BP_LCD_WF39_BPELCD39), BP_LCD_WF39_BPELCD39, 1))
/*@}*/

/*!
 * @name Register LCD_WF39, field BPFLCD39[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF39_BPFLCD39 (5U)          /*!< Bit position for LCD_WF39_BPFLCD39. */
#define BM_LCD_WF39_BPFLCD39 (0x20U)       /*!< Bit mask for LCD_WF39_BPFLCD39. */
#define BS_LCD_WF39_BPFLCD39 (1U)          /*!< Bit field size in bits for LCD_WF39_BPFLCD39. */

/*! @brief Read current value of the LCD_WF39_BPFLCD39 field. */
#define BR_LCD_WF39_BPFLCD39(x) (BME_UBFX8(HW_LCD_WF39_ADDR(x), BP_LCD_WF39_BPFLCD39, BS_LCD_WF39_BPFLCD39))

/*! @brief Format value for bitfield LCD_WF39_BPFLCD39. */
#define BF_LCD_WF39_BPFLCD39(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF39_BPFLCD39) & BM_LCD_WF39_BPFLCD39)

/*! @brief Set the BPFLCD39 field to a new value. */
#define BW_LCD_WF39_BPFLCD39(x, v) (BME_BFI8(HW_LCD_WF39_ADDR(x), ((uint8_t)(v) << BP_LCD_WF39_BPFLCD39), BP_LCD_WF39_BPFLCD39, 1))
/*@}*/

/*!
 * @name Register LCD_WF39, field BPGLCD39[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF39_BPGLCD39 (6U)          /*!< Bit position for LCD_WF39_BPGLCD39. */
#define BM_LCD_WF39_BPGLCD39 (0x40U)       /*!< Bit mask for LCD_WF39_BPGLCD39. */
#define BS_LCD_WF39_BPGLCD39 (1U)          /*!< Bit field size in bits for LCD_WF39_BPGLCD39. */

/*! @brief Read current value of the LCD_WF39_BPGLCD39 field. */
#define BR_LCD_WF39_BPGLCD39(x) (BME_UBFX8(HW_LCD_WF39_ADDR(x), BP_LCD_WF39_BPGLCD39, BS_LCD_WF39_BPGLCD39))

/*! @brief Format value for bitfield LCD_WF39_BPGLCD39. */
#define BF_LCD_WF39_BPGLCD39(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF39_BPGLCD39) & BM_LCD_WF39_BPGLCD39)

/*! @brief Set the BPGLCD39 field to a new value. */
#define BW_LCD_WF39_BPGLCD39(x, v) (BME_BFI8(HW_LCD_WF39_ADDR(x), ((uint8_t)(v) << BP_LCD_WF39_BPGLCD39), BP_LCD_WF39_BPGLCD39, 1))
/*@}*/

/*!
 * @name Register LCD_WF39, field BPHLCD39[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF39_BPHLCD39 (7U)          /*!< Bit position for LCD_WF39_BPHLCD39. */
#define BM_LCD_WF39_BPHLCD39 (0x80U)       /*!< Bit mask for LCD_WF39_BPHLCD39. */
#define BS_LCD_WF39_BPHLCD39 (1U)          /*!< Bit field size in bits for LCD_WF39_BPHLCD39. */

/*! @brief Read current value of the LCD_WF39_BPHLCD39 field. */
#define BR_LCD_WF39_BPHLCD39(x) (BME_UBFX8(HW_LCD_WF39_ADDR(x), BP_LCD_WF39_BPHLCD39, BS_LCD_WF39_BPHLCD39))

/*! @brief Format value for bitfield LCD_WF39_BPHLCD39. */
#define BF_LCD_WF39_BPHLCD39(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF39_BPHLCD39) & BM_LCD_WF39_BPHLCD39)

/*! @brief Set the BPHLCD39 field to a new value. */
#define BW_LCD_WF39_BPHLCD39(x, v) (BME_BFI8(HW_LCD_WF39_ADDR(x), ((uint8_t)(v) << BP_LCD_WF39_BPHLCD39), BP_LCD_WF39_BPHLCD39, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF40 - LCD Waveform Register 40.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF40 - LCD Waveform Register 40. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf40
{
    uint8_t U;
    struct _hw_lcd_wf40_bitfields
    {
        uint8_t BPALCD40 : 1;          /*!< [0]  */
        uint8_t BPBLCD40 : 1;          /*!< [1]  */
        uint8_t BPCLCD40 : 1;          /*!< [2]  */
        uint8_t BPDLCD40 : 1;          /*!< [3]  */
        uint8_t BPELCD40 : 1;          /*!< [4]  */
        uint8_t BPFLCD40 : 1;          /*!< [5]  */
        uint8_t BPGLCD40 : 1;          /*!< [6]  */
        uint8_t BPHLCD40 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf40_t;

/*!
 * @name Constants and macros for entire LCD_WF40 register
 */
/*@{*/
#define HW_LCD_WF40_ADDR(x)      ((x) + 0x48U)

#define HW_LCD_WF40(x)           (*(__IO hw_lcd_wf40_t *) HW_LCD_WF40_ADDR(x))
#define HW_LCD_WF40_RD(x)        (HW_LCD_WF40(x).U)
#define HW_LCD_WF40_WR(x, v)     (HW_LCD_WF40(x).U = (v))
#define HW_LCD_WF40_SET(x, v)    (BME_OR8(HW_LCD_WF40_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF40_CLR(x, v)    (BME_AND8(HW_LCD_WF40_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF40_TOG(x, v)    (BME_XOR8(HW_LCD_WF40_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF40 bitfields
 */

/*!
 * @name Register LCD_WF40, field BPALCD40[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF40_BPALCD40 (0U)          /*!< Bit position for LCD_WF40_BPALCD40. */
#define BM_LCD_WF40_BPALCD40 (0x01U)       /*!< Bit mask for LCD_WF40_BPALCD40. */
#define BS_LCD_WF40_BPALCD40 (1U)          /*!< Bit field size in bits for LCD_WF40_BPALCD40. */

/*! @brief Read current value of the LCD_WF40_BPALCD40 field. */
#define BR_LCD_WF40_BPALCD40(x) (BME_UBFX8(HW_LCD_WF40_ADDR(x), BP_LCD_WF40_BPALCD40, BS_LCD_WF40_BPALCD40))

/*! @brief Format value for bitfield LCD_WF40_BPALCD40. */
#define BF_LCD_WF40_BPALCD40(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF40_BPALCD40) & BM_LCD_WF40_BPALCD40)

/*! @brief Set the BPALCD40 field to a new value. */
#define BW_LCD_WF40_BPALCD40(x, v) (BME_BFI8(HW_LCD_WF40_ADDR(x), ((uint8_t)(v) << BP_LCD_WF40_BPALCD40), BP_LCD_WF40_BPALCD40, 1))
/*@}*/

/*!
 * @name Register LCD_WF40, field BPBLCD40[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF40_BPBLCD40 (1U)          /*!< Bit position for LCD_WF40_BPBLCD40. */
#define BM_LCD_WF40_BPBLCD40 (0x02U)       /*!< Bit mask for LCD_WF40_BPBLCD40. */
#define BS_LCD_WF40_BPBLCD40 (1U)          /*!< Bit field size in bits for LCD_WF40_BPBLCD40. */

/*! @brief Read current value of the LCD_WF40_BPBLCD40 field. */
#define BR_LCD_WF40_BPBLCD40(x) (BME_UBFX8(HW_LCD_WF40_ADDR(x), BP_LCD_WF40_BPBLCD40, BS_LCD_WF40_BPBLCD40))

/*! @brief Format value for bitfield LCD_WF40_BPBLCD40. */
#define BF_LCD_WF40_BPBLCD40(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF40_BPBLCD40) & BM_LCD_WF40_BPBLCD40)

/*! @brief Set the BPBLCD40 field to a new value. */
#define BW_LCD_WF40_BPBLCD40(x, v) (BME_BFI8(HW_LCD_WF40_ADDR(x), ((uint8_t)(v) << BP_LCD_WF40_BPBLCD40), BP_LCD_WF40_BPBLCD40, 1))
/*@}*/

/*!
 * @name Register LCD_WF40, field BPCLCD40[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF40_BPCLCD40 (2U)          /*!< Bit position for LCD_WF40_BPCLCD40. */
#define BM_LCD_WF40_BPCLCD40 (0x04U)       /*!< Bit mask for LCD_WF40_BPCLCD40. */
#define BS_LCD_WF40_BPCLCD40 (1U)          /*!< Bit field size in bits for LCD_WF40_BPCLCD40. */

/*! @brief Read current value of the LCD_WF40_BPCLCD40 field. */
#define BR_LCD_WF40_BPCLCD40(x) (BME_UBFX8(HW_LCD_WF40_ADDR(x), BP_LCD_WF40_BPCLCD40, BS_LCD_WF40_BPCLCD40))

/*! @brief Format value for bitfield LCD_WF40_BPCLCD40. */
#define BF_LCD_WF40_BPCLCD40(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF40_BPCLCD40) & BM_LCD_WF40_BPCLCD40)

/*! @brief Set the BPCLCD40 field to a new value. */
#define BW_LCD_WF40_BPCLCD40(x, v) (BME_BFI8(HW_LCD_WF40_ADDR(x), ((uint8_t)(v) << BP_LCD_WF40_BPCLCD40), BP_LCD_WF40_BPCLCD40, 1))
/*@}*/

/*!
 * @name Register LCD_WF40, field BPDLCD40[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF40_BPDLCD40 (3U)          /*!< Bit position for LCD_WF40_BPDLCD40. */
#define BM_LCD_WF40_BPDLCD40 (0x08U)       /*!< Bit mask for LCD_WF40_BPDLCD40. */
#define BS_LCD_WF40_BPDLCD40 (1U)          /*!< Bit field size in bits for LCD_WF40_BPDLCD40. */

/*! @brief Read current value of the LCD_WF40_BPDLCD40 field. */
#define BR_LCD_WF40_BPDLCD40(x) (BME_UBFX8(HW_LCD_WF40_ADDR(x), BP_LCD_WF40_BPDLCD40, BS_LCD_WF40_BPDLCD40))

/*! @brief Format value for bitfield LCD_WF40_BPDLCD40. */
#define BF_LCD_WF40_BPDLCD40(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF40_BPDLCD40) & BM_LCD_WF40_BPDLCD40)

/*! @brief Set the BPDLCD40 field to a new value. */
#define BW_LCD_WF40_BPDLCD40(x, v) (BME_BFI8(HW_LCD_WF40_ADDR(x), ((uint8_t)(v) << BP_LCD_WF40_BPDLCD40), BP_LCD_WF40_BPDLCD40, 1))
/*@}*/

/*!
 * @name Register LCD_WF40, field BPELCD40[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF40_BPELCD40 (4U)          /*!< Bit position for LCD_WF40_BPELCD40. */
#define BM_LCD_WF40_BPELCD40 (0x10U)       /*!< Bit mask for LCD_WF40_BPELCD40. */
#define BS_LCD_WF40_BPELCD40 (1U)          /*!< Bit field size in bits for LCD_WF40_BPELCD40. */

/*! @brief Read current value of the LCD_WF40_BPELCD40 field. */
#define BR_LCD_WF40_BPELCD40(x) (BME_UBFX8(HW_LCD_WF40_ADDR(x), BP_LCD_WF40_BPELCD40, BS_LCD_WF40_BPELCD40))

/*! @brief Format value for bitfield LCD_WF40_BPELCD40. */
#define BF_LCD_WF40_BPELCD40(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF40_BPELCD40) & BM_LCD_WF40_BPELCD40)

/*! @brief Set the BPELCD40 field to a new value. */
#define BW_LCD_WF40_BPELCD40(x, v) (BME_BFI8(HW_LCD_WF40_ADDR(x), ((uint8_t)(v) << BP_LCD_WF40_BPELCD40), BP_LCD_WF40_BPELCD40, 1))
/*@}*/

/*!
 * @name Register LCD_WF40, field BPFLCD40[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF40_BPFLCD40 (5U)          /*!< Bit position for LCD_WF40_BPFLCD40. */
#define BM_LCD_WF40_BPFLCD40 (0x20U)       /*!< Bit mask for LCD_WF40_BPFLCD40. */
#define BS_LCD_WF40_BPFLCD40 (1U)          /*!< Bit field size in bits for LCD_WF40_BPFLCD40. */

/*! @brief Read current value of the LCD_WF40_BPFLCD40 field. */
#define BR_LCD_WF40_BPFLCD40(x) (BME_UBFX8(HW_LCD_WF40_ADDR(x), BP_LCD_WF40_BPFLCD40, BS_LCD_WF40_BPFLCD40))

/*! @brief Format value for bitfield LCD_WF40_BPFLCD40. */
#define BF_LCD_WF40_BPFLCD40(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF40_BPFLCD40) & BM_LCD_WF40_BPFLCD40)

/*! @brief Set the BPFLCD40 field to a new value. */
#define BW_LCD_WF40_BPFLCD40(x, v) (BME_BFI8(HW_LCD_WF40_ADDR(x), ((uint8_t)(v) << BP_LCD_WF40_BPFLCD40), BP_LCD_WF40_BPFLCD40, 1))
/*@}*/

/*!
 * @name Register LCD_WF40, field BPGLCD40[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF40_BPGLCD40 (6U)          /*!< Bit position for LCD_WF40_BPGLCD40. */
#define BM_LCD_WF40_BPGLCD40 (0x40U)       /*!< Bit mask for LCD_WF40_BPGLCD40. */
#define BS_LCD_WF40_BPGLCD40 (1U)          /*!< Bit field size in bits for LCD_WF40_BPGLCD40. */

/*! @brief Read current value of the LCD_WF40_BPGLCD40 field. */
#define BR_LCD_WF40_BPGLCD40(x) (BME_UBFX8(HW_LCD_WF40_ADDR(x), BP_LCD_WF40_BPGLCD40, BS_LCD_WF40_BPGLCD40))

/*! @brief Format value for bitfield LCD_WF40_BPGLCD40. */
#define BF_LCD_WF40_BPGLCD40(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF40_BPGLCD40) & BM_LCD_WF40_BPGLCD40)

/*! @brief Set the BPGLCD40 field to a new value. */
#define BW_LCD_WF40_BPGLCD40(x, v) (BME_BFI8(HW_LCD_WF40_ADDR(x), ((uint8_t)(v) << BP_LCD_WF40_BPGLCD40), BP_LCD_WF40_BPGLCD40, 1))
/*@}*/

/*!
 * @name Register LCD_WF40, field BPHLCD40[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF40_BPHLCD40 (7U)          /*!< Bit position for LCD_WF40_BPHLCD40. */
#define BM_LCD_WF40_BPHLCD40 (0x80U)       /*!< Bit mask for LCD_WF40_BPHLCD40. */
#define BS_LCD_WF40_BPHLCD40 (1U)          /*!< Bit field size in bits for LCD_WF40_BPHLCD40. */

/*! @brief Read current value of the LCD_WF40_BPHLCD40 field. */
#define BR_LCD_WF40_BPHLCD40(x) (BME_UBFX8(HW_LCD_WF40_ADDR(x), BP_LCD_WF40_BPHLCD40, BS_LCD_WF40_BPHLCD40))

/*! @brief Format value for bitfield LCD_WF40_BPHLCD40. */
#define BF_LCD_WF40_BPHLCD40(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF40_BPHLCD40) & BM_LCD_WF40_BPHLCD40)

/*! @brief Set the BPHLCD40 field to a new value. */
#define BW_LCD_WF40_BPHLCD40(x, v) (BME_BFI8(HW_LCD_WF40_ADDR(x), ((uint8_t)(v) << BP_LCD_WF40_BPHLCD40), BP_LCD_WF40_BPHLCD40, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF41 - LCD Waveform Register 41.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF41 - LCD Waveform Register 41. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf41
{
    uint8_t U;
    struct _hw_lcd_wf41_bitfields
    {
        uint8_t BPALCD41 : 1;          /*!< [0]  */
        uint8_t BPBLCD41 : 1;          /*!< [1]  */
        uint8_t BPCLCD41 : 1;          /*!< [2]  */
        uint8_t BPDLCD41 : 1;          /*!< [3]  */
        uint8_t BPELCD41 : 1;          /*!< [4]  */
        uint8_t BPFLCD41 : 1;          /*!< [5]  */
        uint8_t BPGLCD41 : 1;          /*!< [6]  */
        uint8_t BPHLCD41 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf41_t;

/*!
 * @name Constants and macros for entire LCD_WF41 register
 */
/*@{*/
#define HW_LCD_WF41_ADDR(x)      ((x) + 0x49U)

#define HW_LCD_WF41(x)           (*(__IO hw_lcd_wf41_t *) HW_LCD_WF41_ADDR(x))
#define HW_LCD_WF41_RD(x)        (HW_LCD_WF41(x).U)
#define HW_LCD_WF41_WR(x, v)     (HW_LCD_WF41(x).U = (v))
#define HW_LCD_WF41_SET(x, v)    (BME_OR8(HW_LCD_WF41_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF41_CLR(x, v)    (BME_AND8(HW_LCD_WF41_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF41_TOG(x, v)    (BME_XOR8(HW_LCD_WF41_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF41 bitfields
 */

/*!
 * @name Register LCD_WF41, field BPALCD41[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF41_BPALCD41 (0U)          /*!< Bit position for LCD_WF41_BPALCD41. */
#define BM_LCD_WF41_BPALCD41 (0x01U)       /*!< Bit mask for LCD_WF41_BPALCD41. */
#define BS_LCD_WF41_BPALCD41 (1U)          /*!< Bit field size in bits for LCD_WF41_BPALCD41. */

/*! @brief Read current value of the LCD_WF41_BPALCD41 field. */
#define BR_LCD_WF41_BPALCD41(x) (BME_UBFX8(HW_LCD_WF41_ADDR(x), BP_LCD_WF41_BPALCD41, BS_LCD_WF41_BPALCD41))

/*! @brief Format value for bitfield LCD_WF41_BPALCD41. */
#define BF_LCD_WF41_BPALCD41(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF41_BPALCD41) & BM_LCD_WF41_BPALCD41)

/*! @brief Set the BPALCD41 field to a new value. */
#define BW_LCD_WF41_BPALCD41(x, v) (BME_BFI8(HW_LCD_WF41_ADDR(x), ((uint8_t)(v) << BP_LCD_WF41_BPALCD41), BP_LCD_WF41_BPALCD41, 1))
/*@}*/

/*!
 * @name Register LCD_WF41, field BPBLCD41[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF41_BPBLCD41 (1U)          /*!< Bit position for LCD_WF41_BPBLCD41. */
#define BM_LCD_WF41_BPBLCD41 (0x02U)       /*!< Bit mask for LCD_WF41_BPBLCD41. */
#define BS_LCD_WF41_BPBLCD41 (1U)          /*!< Bit field size in bits for LCD_WF41_BPBLCD41. */

/*! @brief Read current value of the LCD_WF41_BPBLCD41 field. */
#define BR_LCD_WF41_BPBLCD41(x) (BME_UBFX8(HW_LCD_WF41_ADDR(x), BP_LCD_WF41_BPBLCD41, BS_LCD_WF41_BPBLCD41))

/*! @brief Format value for bitfield LCD_WF41_BPBLCD41. */
#define BF_LCD_WF41_BPBLCD41(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF41_BPBLCD41) & BM_LCD_WF41_BPBLCD41)

/*! @brief Set the BPBLCD41 field to a new value. */
#define BW_LCD_WF41_BPBLCD41(x, v) (BME_BFI8(HW_LCD_WF41_ADDR(x), ((uint8_t)(v) << BP_LCD_WF41_BPBLCD41), BP_LCD_WF41_BPBLCD41, 1))
/*@}*/

/*!
 * @name Register LCD_WF41, field BPCLCD41[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF41_BPCLCD41 (2U)          /*!< Bit position for LCD_WF41_BPCLCD41. */
#define BM_LCD_WF41_BPCLCD41 (0x04U)       /*!< Bit mask for LCD_WF41_BPCLCD41. */
#define BS_LCD_WF41_BPCLCD41 (1U)          /*!< Bit field size in bits for LCD_WF41_BPCLCD41. */

/*! @brief Read current value of the LCD_WF41_BPCLCD41 field. */
#define BR_LCD_WF41_BPCLCD41(x) (BME_UBFX8(HW_LCD_WF41_ADDR(x), BP_LCD_WF41_BPCLCD41, BS_LCD_WF41_BPCLCD41))

/*! @brief Format value for bitfield LCD_WF41_BPCLCD41. */
#define BF_LCD_WF41_BPCLCD41(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF41_BPCLCD41) & BM_LCD_WF41_BPCLCD41)

/*! @brief Set the BPCLCD41 field to a new value. */
#define BW_LCD_WF41_BPCLCD41(x, v) (BME_BFI8(HW_LCD_WF41_ADDR(x), ((uint8_t)(v) << BP_LCD_WF41_BPCLCD41), BP_LCD_WF41_BPCLCD41, 1))
/*@}*/

/*!
 * @name Register LCD_WF41, field BPDLCD41[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF41_BPDLCD41 (3U)          /*!< Bit position for LCD_WF41_BPDLCD41. */
#define BM_LCD_WF41_BPDLCD41 (0x08U)       /*!< Bit mask for LCD_WF41_BPDLCD41. */
#define BS_LCD_WF41_BPDLCD41 (1U)          /*!< Bit field size in bits for LCD_WF41_BPDLCD41. */

/*! @brief Read current value of the LCD_WF41_BPDLCD41 field. */
#define BR_LCD_WF41_BPDLCD41(x) (BME_UBFX8(HW_LCD_WF41_ADDR(x), BP_LCD_WF41_BPDLCD41, BS_LCD_WF41_BPDLCD41))

/*! @brief Format value for bitfield LCD_WF41_BPDLCD41. */
#define BF_LCD_WF41_BPDLCD41(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF41_BPDLCD41) & BM_LCD_WF41_BPDLCD41)

/*! @brief Set the BPDLCD41 field to a new value. */
#define BW_LCD_WF41_BPDLCD41(x, v) (BME_BFI8(HW_LCD_WF41_ADDR(x), ((uint8_t)(v) << BP_LCD_WF41_BPDLCD41), BP_LCD_WF41_BPDLCD41, 1))
/*@}*/

/*!
 * @name Register LCD_WF41, field BPELCD41[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF41_BPELCD41 (4U)          /*!< Bit position for LCD_WF41_BPELCD41. */
#define BM_LCD_WF41_BPELCD41 (0x10U)       /*!< Bit mask for LCD_WF41_BPELCD41. */
#define BS_LCD_WF41_BPELCD41 (1U)          /*!< Bit field size in bits for LCD_WF41_BPELCD41. */

/*! @brief Read current value of the LCD_WF41_BPELCD41 field. */
#define BR_LCD_WF41_BPELCD41(x) (BME_UBFX8(HW_LCD_WF41_ADDR(x), BP_LCD_WF41_BPELCD41, BS_LCD_WF41_BPELCD41))

/*! @brief Format value for bitfield LCD_WF41_BPELCD41. */
#define BF_LCD_WF41_BPELCD41(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF41_BPELCD41) & BM_LCD_WF41_BPELCD41)

/*! @brief Set the BPELCD41 field to a new value. */
#define BW_LCD_WF41_BPELCD41(x, v) (BME_BFI8(HW_LCD_WF41_ADDR(x), ((uint8_t)(v) << BP_LCD_WF41_BPELCD41), BP_LCD_WF41_BPELCD41, 1))
/*@}*/

/*!
 * @name Register LCD_WF41, field BPFLCD41[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF41_BPFLCD41 (5U)          /*!< Bit position for LCD_WF41_BPFLCD41. */
#define BM_LCD_WF41_BPFLCD41 (0x20U)       /*!< Bit mask for LCD_WF41_BPFLCD41. */
#define BS_LCD_WF41_BPFLCD41 (1U)          /*!< Bit field size in bits for LCD_WF41_BPFLCD41. */

/*! @brief Read current value of the LCD_WF41_BPFLCD41 field. */
#define BR_LCD_WF41_BPFLCD41(x) (BME_UBFX8(HW_LCD_WF41_ADDR(x), BP_LCD_WF41_BPFLCD41, BS_LCD_WF41_BPFLCD41))

/*! @brief Format value for bitfield LCD_WF41_BPFLCD41. */
#define BF_LCD_WF41_BPFLCD41(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF41_BPFLCD41) & BM_LCD_WF41_BPFLCD41)

/*! @brief Set the BPFLCD41 field to a new value. */
#define BW_LCD_WF41_BPFLCD41(x, v) (BME_BFI8(HW_LCD_WF41_ADDR(x), ((uint8_t)(v) << BP_LCD_WF41_BPFLCD41), BP_LCD_WF41_BPFLCD41, 1))
/*@}*/

/*!
 * @name Register LCD_WF41, field BPGLCD41[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF41_BPGLCD41 (6U)          /*!< Bit position for LCD_WF41_BPGLCD41. */
#define BM_LCD_WF41_BPGLCD41 (0x40U)       /*!< Bit mask for LCD_WF41_BPGLCD41. */
#define BS_LCD_WF41_BPGLCD41 (1U)          /*!< Bit field size in bits for LCD_WF41_BPGLCD41. */

/*! @brief Read current value of the LCD_WF41_BPGLCD41 field. */
#define BR_LCD_WF41_BPGLCD41(x) (BME_UBFX8(HW_LCD_WF41_ADDR(x), BP_LCD_WF41_BPGLCD41, BS_LCD_WF41_BPGLCD41))

/*! @brief Format value for bitfield LCD_WF41_BPGLCD41. */
#define BF_LCD_WF41_BPGLCD41(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF41_BPGLCD41) & BM_LCD_WF41_BPGLCD41)

/*! @brief Set the BPGLCD41 field to a new value. */
#define BW_LCD_WF41_BPGLCD41(x, v) (BME_BFI8(HW_LCD_WF41_ADDR(x), ((uint8_t)(v) << BP_LCD_WF41_BPGLCD41), BP_LCD_WF41_BPGLCD41, 1))
/*@}*/

/*!
 * @name Register LCD_WF41, field BPHLCD41[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF41_BPHLCD41 (7U)          /*!< Bit position for LCD_WF41_BPHLCD41. */
#define BM_LCD_WF41_BPHLCD41 (0x80U)       /*!< Bit mask for LCD_WF41_BPHLCD41. */
#define BS_LCD_WF41_BPHLCD41 (1U)          /*!< Bit field size in bits for LCD_WF41_BPHLCD41. */

/*! @brief Read current value of the LCD_WF41_BPHLCD41 field. */
#define BR_LCD_WF41_BPHLCD41(x) (BME_UBFX8(HW_LCD_WF41_ADDR(x), BP_LCD_WF41_BPHLCD41, BS_LCD_WF41_BPHLCD41))

/*! @brief Format value for bitfield LCD_WF41_BPHLCD41. */
#define BF_LCD_WF41_BPHLCD41(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF41_BPHLCD41) & BM_LCD_WF41_BPHLCD41)

/*! @brief Set the BPHLCD41 field to a new value. */
#define BW_LCD_WF41_BPHLCD41(x, v) (BME_BFI8(HW_LCD_WF41_ADDR(x), ((uint8_t)(v) << BP_LCD_WF41_BPHLCD41), BP_LCD_WF41_BPHLCD41, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF42 - LCD Waveform Register 42.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF42 - LCD Waveform Register 42. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf42
{
    uint8_t U;
    struct _hw_lcd_wf42_bitfields
    {
        uint8_t BPALCD42 : 1;          /*!< [0]  */
        uint8_t BPBLCD42 : 1;          /*!< [1]  */
        uint8_t BPCLCD42 : 1;          /*!< [2]  */
        uint8_t BPDLCD42 : 1;          /*!< [3]  */
        uint8_t BPELCD42 : 1;          /*!< [4]  */
        uint8_t BPFLCD42 : 1;          /*!< [5]  */
        uint8_t BPGLCD42 : 1;          /*!< [6]  */
        uint8_t BPHLCD42 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf42_t;

/*!
 * @name Constants and macros for entire LCD_WF42 register
 */
/*@{*/
#define HW_LCD_WF42_ADDR(x)      ((x) + 0x4AU)

#define HW_LCD_WF42(x)           (*(__IO hw_lcd_wf42_t *) HW_LCD_WF42_ADDR(x))
#define HW_LCD_WF42_RD(x)        (HW_LCD_WF42(x).U)
#define HW_LCD_WF42_WR(x, v)     (HW_LCD_WF42(x).U = (v))
#define HW_LCD_WF42_SET(x, v)    (BME_OR8(HW_LCD_WF42_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF42_CLR(x, v)    (BME_AND8(HW_LCD_WF42_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF42_TOG(x, v)    (BME_XOR8(HW_LCD_WF42_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF42 bitfields
 */

/*!
 * @name Register LCD_WF42, field BPALCD42[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF42_BPALCD42 (0U)          /*!< Bit position for LCD_WF42_BPALCD42. */
#define BM_LCD_WF42_BPALCD42 (0x01U)       /*!< Bit mask for LCD_WF42_BPALCD42. */
#define BS_LCD_WF42_BPALCD42 (1U)          /*!< Bit field size in bits for LCD_WF42_BPALCD42. */

/*! @brief Read current value of the LCD_WF42_BPALCD42 field. */
#define BR_LCD_WF42_BPALCD42(x) (BME_UBFX8(HW_LCD_WF42_ADDR(x), BP_LCD_WF42_BPALCD42, BS_LCD_WF42_BPALCD42))

/*! @brief Format value for bitfield LCD_WF42_BPALCD42. */
#define BF_LCD_WF42_BPALCD42(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF42_BPALCD42) & BM_LCD_WF42_BPALCD42)

/*! @brief Set the BPALCD42 field to a new value. */
#define BW_LCD_WF42_BPALCD42(x, v) (BME_BFI8(HW_LCD_WF42_ADDR(x), ((uint8_t)(v) << BP_LCD_WF42_BPALCD42), BP_LCD_WF42_BPALCD42, 1))
/*@}*/

/*!
 * @name Register LCD_WF42, field BPBLCD42[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF42_BPBLCD42 (1U)          /*!< Bit position for LCD_WF42_BPBLCD42. */
#define BM_LCD_WF42_BPBLCD42 (0x02U)       /*!< Bit mask for LCD_WF42_BPBLCD42. */
#define BS_LCD_WF42_BPBLCD42 (1U)          /*!< Bit field size in bits for LCD_WF42_BPBLCD42. */

/*! @brief Read current value of the LCD_WF42_BPBLCD42 field. */
#define BR_LCD_WF42_BPBLCD42(x) (BME_UBFX8(HW_LCD_WF42_ADDR(x), BP_LCD_WF42_BPBLCD42, BS_LCD_WF42_BPBLCD42))

/*! @brief Format value for bitfield LCD_WF42_BPBLCD42. */
#define BF_LCD_WF42_BPBLCD42(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF42_BPBLCD42) & BM_LCD_WF42_BPBLCD42)

/*! @brief Set the BPBLCD42 field to a new value. */
#define BW_LCD_WF42_BPBLCD42(x, v) (BME_BFI8(HW_LCD_WF42_ADDR(x), ((uint8_t)(v) << BP_LCD_WF42_BPBLCD42), BP_LCD_WF42_BPBLCD42, 1))
/*@}*/

/*!
 * @name Register LCD_WF42, field BPCLCD42[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF42_BPCLCD42 (2U)          /*!< Bit position for LCD_WF42_BPCLCD42. */
#define BM_LCD_WF42_BPCLCD42 (0x04U)       /*!< Bit mask for LCD_WF42_BPCLCD42. */
#define BS_LCD_WF42_BPCLCD42 (1U)          /*!< Bit field size in bits for LCD_WF42_BPCLCD42. */

/*! @brief Read current value of the LCD_WF42_BPCLCD42 field. */
#define BR_LCD_WF42_BPCLCD42(x) (BME_UBFX8(HW_LCD_WF42_ADDR(x), BP_LCD_WF42_BPCLCD42, BS_LCD_WF42_BPCLCD42))

/*! @brief Format value for bitfield LCD_WF42_BPCLCD42. */
#define BF_LCD_WF42_BPCLCD42(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF42_BPCLCD42) & BM_LCD_WF42_BPCLCD42)

/*! @brief Set the BPCLCD42 field to a new value. */
#define BW_LCD_WF42_BPCLCD42(x, v) (BME_BFI8(HW_LCD_WF42_ADDR(x), ((uint8_t)(v) << BP_LCD_WF42_BPCLCD42), BP_LCD_WF42_BPCLCD42, 1))
/*@}*/

/*!
 * @name Register LCD_WF42, field BPDLCD42[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF42_BPDLCD42 (3U)          /*!< Bit position for LCD_WF42_BPDLCD42. */
#define BM_LCD_WF42_BPDLCD42 (0x08U)       /*!< Bit mask for LCD_WF42_BPDLCD42. */
#define BS_LCD_WF42_BPDLCD42 (1U)          /*!< Bit field size in bits for LCD_WF42_BPDLCD42. */

/*! @brief Read current value of the LCD_WF42_BPDLCD42 field. */
#define BR_LCD_WF42_BPDLCD42(x) (BME_UBFX8(HW_LCD_WF42_ADDR(x), BP_LCD_WF42_BPDLCD42, BS_LCD_WF42_BPDLCD42))

/*! @brief Format value for bitfield LCD_WF42_BPDLCD42. */
#define BF_LCD_WF42_BPDLCD42(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF42_BPDLCD42) & BM_LCD_WF42_BPDLCD42)

/*! @brief Set the BPDLCD42 field to a new value. */
#define BW_LCD_WF42_BPDLCD42(x, v) (BME_BFI8(HW_LCD_WF42_ADDR(x), ((uint8_t)(v) << BP_LCD_WF42_BPDLCD42), BP_LCD_WF42_BPDLCD42, 1))
/*@}*/

/*!
 * @name Register LCD_WF42, field BPELCD42[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF42_BPELCD42 (4U)          /*!< Bit position for LCD_WF42_BPELCD42. */
#define BM_LCD_WF42_BPELCD42 (0x10U)       /*!< Bit mask for LCD_WF42_BPELCD42. */
#define BS_LCD_WF42_BPELCD42 (1U)          /*!< Bit field size in bits for LCD_WF42_BPELCD42. */

/*! @brief Read current value of the LCD_WF42_BPELCD42 field. */
#define BR_LCD_WF42_BPELCD42(x) (BME_UBFX8(HW_LCD_WF42_ADDR(x), BP_LCD_WF42_BPELCD42, BS_LCD_WF42_BPELCD42))

/*! @brief Format value for bitfield LCD_WF42_BPELCD42. */
#define BF_LCD_WF42_BPELCD42(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF42_BPELCD42) & BM_LCD_WF42_BPELCD42)

/*! @brief Set the BPELCD42 field to a new value. */
#define BW_LCD_WF42_BPELCD42(x, v) (BME_BFI8(HW_LCD_WF42_ADDR(x), ((uint8_t)(v) << BP_LCD_WF42_BPELCD42), BP_LCD_WF42_BPELCD42, 1))
/*@}*/

/*!
 * @name Register LCD_WF42, field BPFLCD42[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF42_BPFLCD42 (5U)          /*!< Bit position for LCD_WF42_BPFLCD42. */
#define BM_LCD_WF42_BPFLCD42 (0x20U)       /*!< Bit mask for LCD_WF42_BPFLCD42. */
#define BS_LCD_WF42_BPFLCD42 (1U)          /*!< Bit field size in bits for LCD_WF42_BPFLCD42. */

/*! @brief Read current value of the LCD_WF42_BPFLCD42 field. */
#define BR_LCD_WF42_BPFLCD42(x) (BME_UBFX8(HW_LCD_WF42_ADDR(x), BP_LCD_WF42_BPFLCD42, BS_LCD_WF42_BPFLCD42))

/*! @brief Format value for bitfield LCD_WF42_BPFLCD42. */
#define BF_LCD_WF42_BPFLCD42(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF42_BPFLCD42) & BM_LCD_WF42_BPFLCD42)

/*! @brief Set the BPFLCD42 field to a new value. */
#define BW_LCD_WF42_BPFLCD42(x, v) (BME_BFI8(HW_LCD_WF42_ADDR(x), ((uint8_t)(v) << BP_LCD_WF42_BPFLCD42), BP_LCD_WF42_BPFLCD42, 1))
/*@}*/

/*!
 * @name Register LCD_WF42, field BPGLCD42[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF42_BPGLCD42 (6U)          /*!< Bit position for LCD_WF42_BPGLCD42. */
#define BM_LCD_WF42_BPGLCD42 (0x40U)       /*!< Bit mask for LCD_WF42_BPGLCD42. */
#define BS_LCD_WF42_BPGLCD42 (1U)          /*!< Bit field size in bits for LCD_WF42_BPGLCD42. */

/*! @brief Read current value of the LCD_WF42_BPGLCD42 field. */
#define BR_LCD_WF42_BPGLCD42(x) (BME_UBFX8(HW_LCD_WF42_ADDR(x), BP_LCD_WF42_BPGLCD42, BS_LCD_WF42_BPGLCD42))

/*! @brief Format value for bitfield LCD_WF42_BPGLCD42. */
#define BF_LCD_WF42_BPGLCD42(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF42_BPGLCD42) & BM_LCD_WF42_BPGLCD42)

/*! @brief Set the BPGLCD42 field to a new value. */
#define BW_LCD_WF42_BPGLCD42(x, v) (BME_BFI8(HW_LCD_WF42_ADDR(x), ((uint8_t)(v) << BP_LCD_WF42_BPGLCD42), BP_LCD_WF42_BPGLCD42, 1))
/*@}*/

/*!
 * @name Register LCD_WF42, field BPHLCD42[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF42_BPHLCD42 (7U)          /*!< Bit position for LCD_WF42_BPHLCD42. */
#define BM_LCD_WF42_BPHLCD42 (0x80U)       /*!< Bit mask for LCD_WF42_BPHLCD42. */
#define BS_LCD_WF42_BPHLCD42 (1U)          /*!< Bit field size in bits for LCD_WF42_BPHLCD42. */

/*! @brief Read current value of the LCD_WF42_BPHLCD42 field. */
#define BR_LCD_WF42_BPHLCD42(x) (BME_UBFX8(HW_LCD_WF42_ADDR(x), BP_LCD_WF42_BPHLCD42, BS_LCD_WF42_BPHLCD42))

/*! @brief Format value for bitfield LCD_WF42_BPHLCD42. */
#define BF_LCD_WF42_BPHLCD42(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF42_BPHLCD42) & BM_LCD_WF42_BPHLCD42)

/*! @brief Set the BPHLCD42 field to a new value. */
#define BW_LCD_WF42_BPHLCD42(x, v) (BME_BFI8(HW_LCD_WF42_ADDR(x), ((uint8_t)(v) << BP_LCD_WF42_BPHLCD42), BP_LCD_WF42_BPHLCD42, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF43 - LCD Waveform Register 43.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF43 - LCD Waveform Register 43. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf43
{
    uint8_t U;
    struct _hw_lcd_wf43_bitfields
    {
        uint8_t BPALCD43 : 1;          /*!< [0]  */
        uint8_t BPBLCD43 : 1;          /*!< [1]  */
        uint8_t BPCLCD43 : 1;          /*!< [2]  */
        uint8_t BPDLCD43 : 1;          /*!< [3]  */
        uint8_t BPELCD43 : 1;          /*!< [4]  */
        uint8_t BPFLCD43 : 1;          /*!< [5]  */
        uint8_t BPGLCD43 : 1;          /*!< [6]  */
        uint8_t BPHLCD43 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf43_t;

/*!
 * @name Constants and macros for entire LCD_WF43 register
 */
/*@{*/
#define HW_LCD_WF43_ADDR(x)      ((x) + 0x4BU)

#define HW_LCD_WF43(x)           (*(__IO hw_lcd_wf43_t *) HW_LCD_WF43_ADDR(x))
#define HW_LCD_WF43_RD(x)        (HW_LCD_WF43(x).U)
#define HW_LCD_WF43_WR(x, v)     (HW_LCD_WF43(x).U = (v))
#define HW_LCD_WF43_SET(x, v)    (BME_OR8(HW_LCD_WF43_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF43_CLR(x, v)    (BME_AND8(HW_LCD_WF43_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF43_TOG(x, v)    (BME_XOR8(HW_LCD_WF43_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF43 bitfields
 */

/*!
 * @name Register LCD_WF43, field BPALCD43[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF43_BPALCD43 (0U)          /*!< Bit position for LCD_WF43_BPALCD43. */
#define BM_LCD_WF43_BPALCD43 (0x01U)       /*!< Bit mask for LCD_WF43_BPALCD43. */
#define BS_LCD_WF43_BPALCD43 (1U)          /*!< Bit field size in bits for LCD_WF43_BPALCD43. */

/*! @brief Read current value of the LCD_WF43_BPALCD43 field. */
#define BR_LCD_WF43_BPALCD43(x) (BME_UBFX8(HW_LCD_WF43_ADDR(x), BP_LCD_WF43_BPALCD43, BS_LCD_WF43_BPALCD43))

/*! @brief Format value for bitfield LCD_WF43_BPALCD43. */
#define BF_LCD_WF43_BPALCD43(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF43_BPALCD43) & BM_LCD_WF43_BPALCD43)

/*! @brief Set the BPALCD43 field to a new value. */
#define BW_LCD_WF43_BPALCD43(x, v) (BME_BFI8(HW_LCD_WF43_ADDR(x), ((uint8_t)(v) << BP_LCD_WF43_BPALCD43), BP_LCD_WF43_BPALCD43, 1))
/*@}*/

/*!
 * @name Register LCD_WF43, field BPBLCD43[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF43_BPBLCD43 (1U)          /*!< Bit position for LCD_WF43_BPBLCD43. */
#define BM_LCD_WF43_BPBLCD43 (0x02U)       /*!< Bit mask for LCD_WF43_BPBLCD43. */
#define BS_LCD_WF43_BPBLCD43 (1U)          /*!< Bit field size in bits for LCD_WF43_BPBLCD43. */

/*! @brief Read current value of the LCD_WF43_BPBLCD43 field. */
#define BR_LCD_WF43_BPBLCD43(x) (BME_UBFX8(HW_LCD_WF43_ADDR(x), BP_LCD_WF43_BPBLCD43, BS_LCD_WF43_BPBLCD43))

/*! @brief Format value for bitfield LCD_WF43_BPBLCD43. */
#define BF_LCD_WF43_BPBLCD43(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF43_BPBLCD43) & BM_LCD_WF43_BPBLCD43)

/*! @brief Set the BPBLCD43 field to a new value. */
#define BW_LCD_WF43_BPBLCD43(x, v) (BME_BFI8(HW_LCD_WF43_ADDR(x), ((uint8_t)(v) << BP_LCD_WF43_BPBLCD43), BP_LCD_WF43_BPBLCD43, 1))
/*@}*/

/*!
 * @name Register LCD_WF43, field BPCLCD43[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF43_BPCLCD43 (2U)          /*!< Bit position for LCD_WF43_BPCLCD43. */
#define BM_LCD_WF43_BPCLCD43 (0x04U)       /*!< Bit mask for LCD_WF43_BPCLCD43. */
#define BS_LCD_WF43_BPCLCD43 (1U)          /*!< Bit field size in bits for LCD_WF43_BPCLCD43. */

/*! @brief Read current value of the LCD_WF43_BPCLCD43 field. */
#define BR_LCD_WF43_BPCLCD43(x) (BME_UBFX8(HW_LCD_WF43_ADDR(x), BP_LCD_WF43_BPCLCD43, BS_LCD_WF43_BPCLCD43))

/*! @brief Format value for bitfield LCD_WF43_BPCLCD43. */
#define BF_LCD_WF43_BPCLCD43(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF43_BPCLCD43) & BM_LCD_WF43_BPCLCD43)

/*! @brief Set the BPCLCD43 field to a new value. */
#define BW_LCD_WF43_BPCLCD43(x, v) (BME_BFI8(HW_LCD_WF43_ADDR(x), ((uint8_t)(v) << BP_LCD_WF43_BPCLCD43), BP_LCD_WF43_BPCLCD43, 1))
/*@}*/

/*!
 * @name Register LCD_WF43, field BPDLCD43[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF43_BPDLCD43 (3U)          /*!< Bit position for LCD_WF43_BPDLCD43. */
#define BM_LCD_WF43_BPDLCD43 (0x08U)       /*!< Bit mask for LCD_WF43_BPDLCD43. */
#define BS_LCD_WF43_BPDLCD43 (1U)          /*!< Bit field size in bits for LCD_WF43_BPDLCD43. */

/*! @brief Read current value of the LCD_WF43_BPDLCD43 field. */
#define BR_LCD_WF43_BPDLCD43(x) (BME_UBFX8(HW_LCD_WF43_ADDR(x), BP_LCD_WF43_BPDLCD43, BS_LCD_WF43_BPDLCD43))

/*! @brief Format value for bitfield LCD_WF43_BPDLCD43. */
#define BF_LCD_WF43_BPDLCD43(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF43_BPDLCD43) & BM_LCD_WF43_BPDLCD43)

/*! @brief Set the BPDLCD43 field to a new value. */
#define BW_LCD_WF43_BPDLCD43(x, v) (BME_BFI8(HW_LCD_WF43_ADDR(x), ((uint8_t)(v) << BP_LCD_WF43_BPDLCD43), BP_LCD_WF43_BPDLCD43, 1))
/*@}*/

/*!
 * @name Register LCD_WF43, field BPELCD43[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF43_BPELCD43 (4U)          /*!< Bit position for LCD_WF43_BPELCD43. */
#define BM_LCD_WF43_BPELCD43 (0x10U)       /*!< Bit mask for LCD_WF43_BPELCD43. */
#define BS_LCD_WF43_BPELCD43 (1U)          /*!< Bit field size in bits for LCD_WF43_BPELCD43. */

/*! @brief Read current value of the LCD_WF43_BPELCD43 field. */
#define BR_LCD_WF43_BPELCD43(x) (BME_UBFX8(HW_LCD_WF43_ADDR(x), BP_LCD_WF43_BPELCD43, BS_LCD_WF43_BPELCD43))

/*! @brief Format value for bitfield LCD_WF43_BPELCD43. */
#define BF_LCD_WF43_BPELCD43(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF43_BPELCD43) & BM_LCD_WF43_BPELCD43)

/*! @brief Set the BPELCD43 field to a new value. */
#define BW_LCD_WF43_BPELCD43(x, v) (BME_BFI8(HW_LCD_WF43_ADDR(x), ((uint8_t)(v) << BP_LCD_WF43_BPELCD43), BP_LCD_WF43_BPELCD43, 1))
/*@}*/

/*!
 * @name Register LCD_WF43, field BPFLCD43[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF43_BPFLCD43 (5U)          /*!< Bit position for LCD_WF43_BPFLCD43. */
#define BM_LCD_WF43_BPFLCD43 (0x20U)       /*!< Bit mask for LCD_WF43_BPFLCD43. */
#define BS_LCD_WF43_BPFLCD43 (1U)          /*!< Bit field size in bits for LCD_WF43_BPFLCD43. */

/*! @brief Read current value of the LCD_WF43_BPFLCD43 field. */
#define BR_LCD_WF43_BPFLCD43(x) (BME_UBFX8(HW_LCD_WF43_ADDR(x), BP_LCD_WF43_BPFLCD43, BS_LCD_WF43_BPFLCD43))

/*! @brief Format value for bitfield LCD_WF43_BPFLCD43. */
#define BF_LCD_WF43_BPFLCD43(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF43_BPFLCD43) & BM_LCD_WF43_BPFLCD43)

/*! @brief Set the BPFLCD43 field to a new value. */
#define BW_LCD_WF43_BPFLCD43(x, v) (BME_BFI8(HW_LCD_WF43_ADDR(x), ((uint8_t)(v) << BP_LCD_WF43_BPFLCD43), BP_LCD_WF43_BPFLCD43, 1))
/*@}*/

/*!
 * @name Register LCD_WF43, field BPGLCD43[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF43_BPGLCD43 (6U)          /*!< Bit position for LCD_WF43_BPGLCD43. */
#define BM_LCD_WF43_BPGLCD43 (0x40U)       /*!< Bit mask for LCD_WF43_BPGLCD43. */
#define BS_LCD_WF43_BPGLCD43 (1U)          /*!< Bit field size in bits for LCD_WF43_BPGLCD43. */

/*! @brief Read current value of the LCD_WF43_BPGLCD43 field. */
#define BR_LCD_WF43_BPGLCD43(x) (BME_UBFX8(HW_LCD_WF43_ADDR(x), BP_LCD_WF43_BPGLCD43, BS_LCD_WF43_BPGLCD43))

/*! @brief Format value for bitfield LCD_WF43_BPGLCD43. */
#define BF_LCD_WF43_BPGLCD43(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF43_BPGLCD43) & BM_LCD_WF43_BPGLCD43)

/*! @brief Set the BPGLCD43 field to a new value. */
#define BW_LCD_WF43_BPGLCD43(x, v) (BME_BFI8(HW_LCD_WF43_ADDR(x), ((uint8_t)(v) << BP_LCD_WF43_BPGLCD43), BP_LCD_WF43_BPGLCD43, 1))
/*@}*/

/*!
 * @name Register LCD_WF43, field BPHLCD43[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF43_BPHLCD43 (7U)          /*!< Bit position for LCD_WF43_BPHLCD43. */
#define BM_LCD_WF43_BPHLCD43 (0x80U)       /*!< Bit mask for LCD_WF43_BPHLCD43. */
#define BS_LCD_WF43_BPHLCD43 (1U)          /*!< Bit field size in bits for LCD_WF43_BPHLCD43. */

/*! @brief Read current value of the LCD_WF43_BPHLCD43 field. */
#define BR_LCD_WF43_BPHLCD43(x) (BME_UBFX8(HW_LCD_WF43_ADDR(x), BP_LCD_WF43_BPHLCD43, BS_LCD_WF43_BPHLCD43))

/*! @brief Format value for bitfield LCD_WF43_BPHLCD43. */
#define BF_LCD_WF43_BPHLCD43(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF43_BPHLCD43) & BM_LCD_WF43_BPHLCD43)

/*! @brief Set the BPHLCD43 field to a new value. */
#define BW_LCD_WF43_BPHLCD43(x, v) (BME_BFI8(HW_LCD_WF43_ADDR(x), ((uint8_t)(v) << BP_LCD_WF43_BPHLCD43), BP_LCD_WF43_BPHLCD43, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF44 - LCD Waveform Register 44.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF44 - LCD Waveform Register 44. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf44
{
    uint8_t U;
    struct _hw_lcd_wf44_bitfields
    {
        uint8_t BPALCD44 : 1;          /*!< [0]  */
        uint8_t BPBLCD44 : 1;          /*!< [1]  */
        uint8_t BPCLCD44 : 1;          /*!< [2]  */
        uint8_t BPDLCD44 : 1;          /*!< [3]  */
        uint8_t BPELCD44 : 1;          /*!< [4]  */
        uint8_t BPFLCD44 : 1;          /*!< [5]  */
        uint8_t BPGLCD44 : 1;          /*!< [6]  */
        uint8_t BPHLCD44 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf44_t;

/*!
 * @name Constants and macros for entire LCD_WF44 register
 */
/*@{*/
#define HW_LCD_WF44_ADDR(x)      ((x) + 0x4CU)

#define HW_LCD_WF44(x)           (*(__IO hw_lcd_wf44_t *) HW_LCD_WF44_ADDR(x))
#define HW_LCD_WF44_RD(x)        (HW_LCD_WF44(x).U)
#define HW_LCD_WF44_WR(x, v)     (HW_LCD_WF44(x).U = (v))
#define HW_LCD_WF44_SET(x, v)    (BME_OR8(HW_LCD_WF44_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF44_CLR(x, v)    (BME_AND8(HW_LCD_WF44_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF44_TOG(x, v)    (BME_XOR8(HW_LCD_WF44_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF44 bitfields
 */

/*!
 * @name Register LCD_WF44, field BPALCD44[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF44_BPALCD44 (0U)          /*!< Bit position for LCD_WF44_BPALCD44. */
#define BM_LCD_WF44_BPALCD44 (0x01U)       /*!< Bit mask for LCD_WF44_BPALCD44. */
#define BS_LCD_WF44_BPALCD44 (1U)          /*!< Bit field size in bits for LCD_WF44_BPALCD44. */

/*! @brief Read current value of the LCD_WF44_BPALCD44 field. */
#define BR_LCD_WF44_BPALCD44(x) (BME_UBFX8(HW_LCD_WF44_ADDR(x), BP_LCD_WF44_BPALCD44, BS_LCD_WF44_BPALCD44))

/*! @brief Format value for bitfield LCD_WF44_BPALCD44. */
#define BF_LCD_WF44_BPALCD44(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF44_BPALCD44) & BM_LCD_WF44_BPALCD44)

/*! @brief Set the BPALCD44 field to a new value. */
#define BW_LCD_WF44_BPALCD44(x, v) (BME_BFI8(HW_LCD_WF44_ADDR(x), ((uint8_t)(v) << BP_LCD_WF44_BPALCD44), BP_LCD_WF44_BPALCD44, 1))
/*@}*/

/*!
 * @name Register LCD_WF44, field BPBLCD44[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF44_BPBLCD44 (1U)          /*!< Bit position for LCD_WF44_BPBLCD44. */
#define BM_LCD_WF44_BPBLCD44 (0x02U)       /*!< Bit mask for LCD_WF44_BPBLCD44. */
#define BS_LCD_WF44_BPBLCD44 (1U)          /*!< Bit field size in bits for LCD_WF44_BPBLCD44. */

/*! @brief Read current value of the LCD_WF44_BPBLCD44 field. */
#define BR_LCD_WF44_BPBLCD44(x) (BME_UBFX8(HW_LCD_WF44_ADDR(x), BP_LCD_WF44_BPBLCD44, BS_LCD_WF44_BPBLCD44))

/*! @brief Format value for bitfield LCD_WF44_BPBLCD44. */
#define BF_LCD_WF44_BPBLCD44(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF44_BPBLCD44) & BM_LCD_WF44_BPBLCD44)

/*! @brief Set the BPBLCD44 field to a new value. */
#define BW_LCD_WF44_BPBLCD44(x, v) (BME_BFI8(HW_LCD_WF44_ADDR(x), ((uint8_t)(v) << BP_LCD_WF44_BPBLCD44), BP_LCD_WF44_BPBLCD44, 1))
/*@}*/

/*!
 * @name Register LCD_WF44, field BPCLCD44[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF44_BPCLCD44 (2U)          /*!< Bit position for LCD_WF44_BPCLCD44. */
#define BM_LCD_WF44_BPCLCD44 (0x04U)       /*!< Bit mask for LCD_WF44_BPCLCD44. */
#define BS_LCD_WF44_BPCLCD44 (1U)          /*!< Bit field size in bits for LCD_WF44_BPCLCD44. */

/*! @brief Read current value of the LCD_WF44_BPCLCD44 field. */
#define BR_LCD_WF44_BPCLCD44(x) (BME_UBFX8(HW_LCD_WF44_ADDR(x), BP_LCD_WF44_BPCLCD44, BS_LCD_WF44_BPCLCD44))

/*! @brief Format value for bitfield LCD_WF44_BPCLCD44. */
#define BF_LCD_WF44_BPCLCD44(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF44_BPCLCD44) & BM_LCD_WF44_BPCLCD44)

/*! @brief Set the BPCLCD44 field to a new value. */
#define BW_LCD_WF44_BPCLCD44(x, v) (BME_BFI8(HW_LCD_WF44_ADDR(x), ((uint8_t)(v) << BP_LCD_WF44_BPCLCD44), BP_LCD_WF44_BPCLCD44, 1))
/*@}*/

/*!
 * @name Register LCD_WF44, field BPDLCD44[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF44_BPDLCD44 (3U)          /*!< Bit position for LCD_WF44_BPDLCD44. */
#define BM_LCD_WF44_BPDLCD44 (0x08U)       /*!< Bit mask for LCD_WF44_BPDLCD44. */
#define BS_LCD_WF44_BPDLCD44 (1U)          /*!< Bit field size in bits for LCD_WF44_BPDLCD44. */

/*! @brief Read current value of the LCD_WF44_BPDLCD44 field. */
#define BR_LCD_WF44_BPDLCD44(x) (BME_UBFX8(HW_LCD_WF44_ADDR(x), BP_LCD_WF44_BPDLCD44, BS_LCD_WF44_BPDLCD44))

/*! @brief Format value for bitfield LCD_WF44_BPDLCD44. */
#define BF_LCD_WF44_BPDLCD44(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF44_BPDLCD44) & BM_LCD_WF44_BPDLCD44)

/*! @brief Set the BPDLCD44 field to a new value. */
#define BW_LCD_WF44_BPDLCD44(x, v) (BME_BFI8(HW_LCD_WF44_ADDR(x), ((uint8_t)(v) << BP_LCD_WF44_BPDLCD44), BP_LCD_WF44_BPDLCD44, 1))
/*@}*/

/*!
 * @name Register LCD_WF44, field BPELCD44[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF44_BPELCD44 (4U)          /*!< Bit position for LCD_WF44_BPELCD44. */
#define BM_LCD_WF44_BPELCD44 (0x10U)       /*!< Bit mask for LCD_WF44_BPELCD44. */
#define BS_LCD_WF44_BPELCD44 (1U)          /*!< Bit field size in bits for LCD_WF44_BPELCD44. */

/*! @brief Read current value of the LCD_WF44_BPELCD44 field. */
#define BR_LCD_WF44_BPELCD44(x) (BME_UBFX8(HW_LCD_WF44_ADDR(x), BP_LCD_WF44_BPELCD44, BS_LCD_WF44_BPELCD44))

/*! @brief Format value for bitfield LCD_WF44_BPELCD44. */
#define BF_LCD_WF44_BPELCD44(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF44_BPELCD44) & BM_LCD_WF44_BPELCD44)

/*! @brief Set the BPELCD44 field to a new value. */
#define BW_LCD_WF44_BPELCD44(x, v) (BME_BFI8(HW_LCD_WF44_ADDR(x), ((uint8_t)(v) << BP_LCD_WF44_BPELCD44), BP_LCD_WF44_BPELCD44, 1))
/*@}*/

/*!
 * @name Register LCD_WF44, field BPFLCD44[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF44_BPFLCD44 (5U)          /*!< Bit position for LCD_WF44_BPFLCD44. */
#define BM_LCD_WF44_BPFLCD44 (0x20U)       /*!< Bit mask for LCD_WF44_BPFLCD44. */
#define BS_LCD_WF44_BPFLCD44 (1U)          /*!< Bit field size in bits for LCD_WF44_BPFLCD44. */

/*! @brief Read current value of the LCD_WF44_BPFLCD44 field. */
#define BR_LCD_WF44_BPFLCD44(x) (BME_UBFX8(HW_LCD_WF44_ADDR(x), BP_LCD_WF44_BPFLCD44, BS_LCD_WF44_BPFLCD44))

/*! @brief Format value for bitfield LCD_WF44_BPFLCD44. */
#define BF_LCD_WF44_BPFLCD44(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF44_BPFLCD44) & BM_LCD_WF44_BPFLCD44)

/*! @brief Set the BPFLCD44 field to a new value. */
#define BW_LCD_WF44_BPFLCD44(x, v) (BME_BFI8(HW_LCD_WF44_ADDR(x), ((uint8_t)(v) << BP_LCD_WF44_BPFLCD44), BP_LCD_WF44_BPFLCD44, 1))
/*@}*/

/*!
 * @name Register LCD_WF44, field BPGLCD44[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF44_BPGLCD44 (6U)          /*!< Bit position for LCD_WF44_BPGLCD44. */
#define BM_LCD_WF44_BPGLCD44 (0x40U)       /*!< Bit mask for LCD_WF44_BPGLCD44. */
#define BS_LCD_WF44_BPGLCD44 (1U)          /*!< Bit field size in bits for LCD_WF44_BPGLCD44. */

/*! @brief Read current value of the LCD_WF44_BPGLCD44 field. */
#define BR_LCD_WF44_BPGLCD44(x) (BME_UBFX8(HW_LCD_WF44_ADDR(x), BP_LCD_WF44_BPGLCD44, BS_LCD_WF44_BPGLCD44))

/*! @brief Format value for bitfield LCD_WF44_BPGLCD44. */
#define BF_LCD_WF44_BPGLCD44(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF44_BPGLCD44) & BM_LCD_WF44_BPGLCD44)

/*! @brief Set the BPGLCD44 field to a new value. */
#define BW_LCD_WF44_BPGLCD44(x, v) (BME_BFI8(HW_LCD_WF44_ADDR(x), ((uint8_t)(v) << BP_LCD_WF44_BPGLCD44), BP_LCD_WF44_BPGLCD44, 1))
/*@}*/

/*!
 * @name Register LCD_WF44, field BPHLCD44[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF44_BPHLCD44 (7U)          /*!< Bit position for LCD_WF44_BPHLCD44. */
#define BM_LCD_WF44_BPHLCD44 (0x80U)       /*!< Bit mask for LCD_WF44_BPHLCD44. */
#define BS_LCD_WF44_BPHLCD44 (1U)          /*!< Bit field size in bits for LCD_WF44_BPHLCD44. */

/*! @brief Read current value of the LCD_WF44_BPHLCD44 field. */
#define BR_LCD_WF44_BPHLCD44(x) (BME_UBFX8(HW_LCD_WF44_ADDR(x), BP_LCD_WF44_BPHLCD44, BS_LCD_WF44_BPHLCD44))

/*! @brief Format value for bitfield LCD_WF44_BPHLCD44. */
#define BF_LCD_WF44_BPHLCD44(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF44_BPHLCD44) & BM_LCD_WF44_BPHLCD44)

/*! @brief Set the BPHLCD44 field to a new value. */
#define BW_LCD_WF44_BPHLCD44(x, v) (BME_BFI8(HW_LCD_WF44_ADDR(x), ((uint8_t)(v) << BP_LCD_WF44_BPHLCD44), BP_LCD_WF44_BPHLCD44, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF45 - LCD Waveform Register 45.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF45 - LCD Waveform Register 45. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf45
{
    uint8_t U;
    struct _hw_lcd_wf45_bitfields
    {
        uint8_t BPALCD45 : 1;          /*!< [0]  */
        uint8_t BPBLCD45 : 1;          /*!< [1]  */
        uint8_t BPCLCD45 : 1;          /*!< [2]  */
        uint8_t BPDLCD45 : 1;          /*!< [3]  */
        uint8_t BPELCD45 : 1;          /*!< [4]  */
        uint8_t BPFLCD45 : 1;          /*!< [5]  */
        uint8_t BPGLCD45 : 1;          /*!< [6]  */
        uint8_t BPHLCD45 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf45_t;

/*!
 * @name Constants and macros for entire LCD_WF45 register
 */
/*@{*/
#define HW_LCD_WF45_ADDR(x)      ((x) + 0x4DU)

#define HW_LCD_WF45(x)           (*(__IO hw_lcd_wf45_t *) HW_LCD_WF45_ADDR(x))
#define HW_LCD_WF45_RD(x)        (HW_LCD_WF45(x).U)
#define HW_LCD_WF45_WR(x, v)     (HW_LCD_WF45(x).U = (v))
#define HW_LCD_WF45_SET(x, v)    (BME_OR8(HW_LCD_WF45_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF45_CLR(x, v)    (BME_AND8(HW_LCD_WF45_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF45_TOG(x, v)    (BME_XOR8(HW_LCD_WF45_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF45 bitfields
 */

/*!
 * @name Register LCD_WF45, field BPALCD45[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF45_BPALCD45 (0U)          /*!< Bit position for LCD_WF45_BPALCD45. */
#define BM_LCD_WF45_BPALCD45 (0x01U)       /*!< Bit mask for LCD_WF45_BPALCD45. */
#define BS_LCD_WF45_BPALCD45 (1U)          /*!< Bit field size in bits for LCD_WF45_BPALCD45. */

/*! @brief Read current value of the LCD_WF45_BPALCD45 field. */
#define BR_LCD_WF45_BPALCD45(x) (BME_UBFX8(HW_LCD_WF45_ADDR(x), BP_LCD_WF45_BPALCD45, BS_LCD_WF45_BPALCD45))

/*! @brief Format value for bitfield LCD_WF45_BPALCD45. */
#define BF_LCD_WF45_BPALCD45(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF45_BPALCD45) & BM_LCD_WF45_BPALCD45)

/*! @brief Set the BPALCD45 field to a new value. */
#define BW_LCD_WF45_BPALCD45(x, v) (BME_BFI8(HW_LCD_WF45_ADDR(x), ((uint8_t)(v) << BP_LCD_WF45_BPALCD45), BP_LCD_WF45_BPALCD45, 1))
/*@}*/

/*!
 * @name Register LCD_WF45, field BPBLCD45[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF45_BPBLCD45 (1U)          /*!< Bit position for LCD_WF45_BPBLCD45. */
#define BM_LCD_WF45_BPBLCD45 (0x02U)       /*!< Bit mask for LCD_WF45_BPBLCD45. */
#define BS_LCD_WF45_BPBLCD45 (1U)          /*!< Bit field size in bits for LCD_WF45_BPBLCD45. */

/*! @brief Read current value of the LCD_WF45_BPBLCD45 field. */
#define BR_LCD_WF45_BPBLCD45(x) (BME_UBFX8(HW_LCD_WF45_ADDR(x), BP_LCD_WF45_BPBLCD45, BS_LCD_WF45_BPBLCD45))

/*! @brief Format value for bitfield LCD_WF45_BPBLCD45. */
#define BF_LCD_WF45_BPBLCD45(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF45_BPBLCD45) & BM_LCD_WF45_BPBLCD45)

/*! @brief Set the BPBLCD45 field to a new value. */
#define BW_LCD_WF45_BPBLCD45(x, v) (BME_BFI8(HW_LCD_WF45_ADDR(x), ((uint8_t)(v) << BP_LCD_WF45_BPBLCD45), BP_LCD_WF45_BPBLCD45, 1))
/*@}*/

/*!
 * @name Register LCD_WF45, field BPCLCD45[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF45_BPCLCD45 (2U)          /*!< Bit position for LCD_WF45_BPCLCD45. */
#define BM_LCD_WF45_BPCLCD45 (0x04U)       /*!< Bit mask for LCD_WF45_BPCLCD45. */
#define BS_LCD_WF45_BPCLCD45 (1U)          /*!< Bit field size in bits for LCD_WF45_BPCLCD45. */

/*! @brief Read current value of the LCD_WF45_BPCLCD45 field. */
#define BR_LCD_WF45_BPCLCD45(x) (BME_UBFX8(HW_LCD_WF45_ADDR(x), BP_LCD_WF45_BPCLCD45, BS_LCD_WF45_BPCLCD45))

/*! @brief Format value for bitfield LCD_WF45_BPCLCD45. */
#define BF_LCD_WF45_BPCLCD45(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF45_BPCLCD45) & BM_LCD_WF45_BPCLCD45)

/*! @brief Set the BPCLCD45 field to a new value. */
#define BW_LCD_WF45_BPCLCD45(x, v) (BME_BFI8(HW_LCD_WF45_ADDR(x), ((uint8_t)(v) << BP_LCD_WF45_BPCLCD45), BP_LCD_WF45_BPCLCD45, 1))
/*@}*/

/*!
 * @name Register LCD_WF45, field BPDLCD45[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF45_BPDLCD45 (3U)          /*!< Bit position for LCD_WF45_BPDLCD45. */
#define BM_LCD_WF45_BPDLCD45 (0x08U)       /*!< Bit mask for LCD_WF45_BPDLCD45. */
#define BS_LCD_WF45_BPDLCD45 (1U)          /*!< Bit field size in bits for LCD_WF45_BPDLCD45. */

/*! @brief Read current value of the LCD_WF45_BPDLCD45 field. */
#define BR_LCD_WF45_BPDLCD45(x) (BME_UBFX8(HW_LCD_WF45_ADDR(x), BP_LCD_WF45_BPDLCD45, BS_LCD_WF45_BPDLCD45))

/*! @brief Format value for bitfield LCD_WF45_BPDLCD45. */
#define BF_LCD_WF45_BPDLCD45(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF45_BPDLCD45) & BM_LCD_WF45_BPDLCD45)

/*! @brief Set the BPDLCD45 field to a new value. */
#define BW_LCD_WF45_BPDLCD45(x, v) (BME_BFI8(HW_LCD_WF45_ADDR(x), ((uint8_t)(v) << BP_LCD_WF45_BPDLCD45), BP_LCD_WF45_BPDLCD45, 1))
/*@}*/

/*!
 * @name Register LCD_WF45, field BPELCD45[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF45_BPELCD45 (4U)          /*!< Bit position for LCD_WF45_BPELCD45. */
#define BM_LCD_WF45_BPELCD45 (0x10U)       /*!< Bit mask for LCD_WF45_BPELCD45. */
#define BS_LCD_WF45_BPELCD45 (1U)          /*!< Bit field size in bits for LCD_WF45_BPELCD45. */

/*! @brief Read current value of the LCD_WF45_BPELCD45 field. */
#define BR_LCD_WF45_BPELCD45(x) (BME_UBFX8(HW_LCD_WF45_ADDR(x), BP_LCD_WF45_BPELCD45, BS_LCD_WF45_BPELCD45))

/*! @brief Format value for bitfield LCD_WF45_BPELCD45. */
#define BF_LCD_WF45_BPELCD45(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF45_BPELCD45) & BM_LCD_WF45_BPELCD45)

/*! @brief Set the BPELCD45 field to a new value. */
#define BW_LCD_WF45_BPELCD45(x, v) (BME_BFI8(HW_LCD_WF45_ADDR(x), ((uint8_t)(v) << BP_LCD_WF45_BPELCD45), BP_LCD_WF45_BPELCD45, 1))
/*@}*/

/*!
 * @name Register LCD_WF45, field BPFLCD45[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF45_BPFLCD45 (5U)          /*!< Bit position for LCD_WF45_BPFLCD45. */
#define BM_LCD_WF45_BPFLCD45 (0x20U)       /*!< Bit mask for LCD_WF45_BPFLCD45. */
#define BS_LCD_WF45_BPFLCD45 (1U)          /*!< Bit field size in bits for LCD_WF45_BPFLCD45. */

/*! @brief Read current value of the LCD_WF45_BPFLCD45 field. */
#define BR_LCD_WF45_BPFLCD45(x) (BME_UBFX8(HW_LCD_WF45_ADDR(x), BP_LCD_WF45_BPFLCD45, BS_LCD_WF45_BPFLCD45))

/*! @brief Format value for bitfield LCD_WF45_BPFLCD45. */
#define BF_LCD_WF45_BPFLCD45(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF45_BPFLCD45) & BM_LCD_WF45_BPFLCD45)

/*! @brief Set the BPFLCD45 field to a new value. */
#define BW_LCD_WF45_BPFLCD45(x, v) (BME_BFI8(HW_LCD_WF45_ADDR(x), ((uint8_t)(v) << BP_LCD_WF45_BPFLCD45), BP_LCD_WF45_BPFLCD45, 1))
/*@}*/

/*!
 * @name Register LCD_WF45, field BPGLCD45[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF45_BPGLCD45 (6U)          /*!< Bit position for LCD_WF45_BPGLCD45. */
#define BM_LCD_WF45_BPGLCD45 (0x40U)       /*!< Bit mask for LCD_WF45_BPGLCD45. */
#define BS_LCD_WF45_BPGLCD45 (1U)          /*!< Bit field size in bits for LCD_WF45_BPGLCD45. */

/*! @brief Read current value of the LCD_WF45_BPGLCD45 field. */
#define BR_LCD_WF45_BPGLCD45(x) (BME_UBFX8(HW_LCD_WF45_ADDR(x), BP_LCD_WF45_BPGLCD45, BS_LCD_WF45_BPGLCD45))

/*! @brief Format value for bitfield LCD_WF45_BPGLCD45. */
#define BF_LCD_WF45_BPGLCD45(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF45_BPGLCD45) & BM_LCD_WF45_BPGLCD45)

/*! @brief Set the BPGLCD45 field to a new value. */
#define BW_LCD_WF45_BPGLCD45(x, v) (BME_BFI8(HW_LCD_WF45_ADDR(x), ((uint8_t)(v) << BP_LCD_WF45_BPGLCD45), BP_LCD_WF45_BPGLCD45, 1))
/*@}*/

/*!
 * @name Register LCD_WF45, field BPHLCD45[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF45_BPHLCD45 (7U)          /*!< Bit position for LCD_WF45_BPHLCD45. */
#define BM_LCD_WF45_BPHLCD45 (0x80U)       /*!< Bit mask for LCD_WF45_BPHLCD45. */
#define BS_LCD_WF45_BPHLCD45 (1U)          /*!< Bit field size in bits for LCD_WF45_BPHLCD45. */

/*! @brief Read current value of the LCD_WF45_BPHLCD45 field. */
#define BR_LCD_WF45_BPHLCD45(x) (BME_UBFX8(HW_LCD_WF45_ADDR(x), BP_LCD_WF45_BPHLCD45, BS_LCD_WF45_BPHLCD45))

/*! @brief Format value for bitfield LCD_WF45_BPHLCD45. */
#define BF_LCD_WF45_BPHLCD45(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF45_BPHLCD45) & BM_LCD_WF45_BPHLCD45)

/*! @brief Set the BPHLCD45 field to a new value. */
#define BW_LCD_WF45_BPHLCD45(x, v) (BME_BFI8(HW_LCD_WF45_ADDR(x), ((uint8_t)(v) << BP_LCD_WF45_BPHLCD45), BP_LCD_WF45_BPHLCD45, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF46 - LCD Waveform Register 46.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF46 - LCD Waveform Register 46. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf46
{
    uint8_t U;
    struct _hw_lcd_wf46_bitfields
    {
        uint8_t BPALCD46 : 1;          /*!< [0]  */
        uint8_t BPBLCD46 : 1;          /*!< [1]  */
        uint8_t BPCLCD46 : 1;          /*!< [2]  */
        uint8_t BPDLCD46 : 1;          /*!< [3]  */
        uint8_t BPELCD46 : 1;          /*!< [4]  */
        uint8_t BPFLCD46 : 1;          /*!< [5]  */
        uint8_t BPGLCD46 : 1;          /*!< [6]  */
        uint8_t BPHLCD46 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf46_t;

/*!
 * @name Constants and macros for entire LCD_WF46 register
 */
/*@{*/
#define HW_LCD_WF46_ADDR(x)      ((x) + 0x4EU)

#define HW_LCD_WF46(x)           (*(__IO hw_lcd_wf46_t *) HW_LCD_WF46_ADDR(x))
#define HW_LCD_WF46_RD(x)        (HW_LCD_WF46(x).U)
#define HW_LCD_WF46_WR(x, v)     (HW_LCD_WF46(x).U = (v))
#define HW_LCD_WF46_SET(x, v)    (BME_OR8(HW_LCD_WF46_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF46_CLR(x, v)    (BME_AND8(HW_LCD_WF46_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF46_TOG(x, v)    (BME_XOR8(HW_LCD_WF46_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF46 bitfields
 */

/*!
 * @name Register LCD_WF46, field BPALCD46[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF46_BPALCD46 (0U)          /*!< Bit position for LCD_WF46_BPALCD46. */
#define BM_LCD_WF46_BPALCD46 (0x01U)       /*!< Bit mask for LCD_WF46_BPALCD46. */
#define BS_LCD_WF46_BPALCD46 (1U)          /*!< Bit field size in bits for LCD_WF46_BPALCD46. */

/*! @brief Read current value of the LCD_WF46_BPALCD46 field. */
#define BR_LCD_WF46_BPALCD46(x) (BME_UBFX8(HW_LCD_WF46_ADDR(x), BP_LCD_WF46_BPALCD46, BS_LCD_WF46_BPALCD46))

/*! @brief Format value for bitfield LCD_WF46_BPALCD46. */
#define BF_LCD_WF46_BPALCD46(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF46_BPALCD46) & BM_LCD_WF46_BPALCD46)

/*! @brief Set the BPALCD46 field to a new value. */
#define BW_LCD_WF46_BPALCD46(x, v) (BME_BFI8(HW_LCD_WF46_ADDR(x), ((uint8_t)(v) << BP_LCD_WF46_BPALCD46), BP_LCD_WF46_BPALCD46, 1))
/*@}*/

/*!
 * @name Register LCD_WF46, field BPBLCD46[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF46_BPBLCD46 (1U)          /*!< Bit position for LCD_WF46_BPBLCD46. */
#define BM_LCD_WF46_BPBLCD46 (0x02U)       /*!< Bit mask for LCD_WF46_BPBLCD46. */
#define BS_LCD_WF46_BPBLCD46 (1U)          /*!< Bit field size in bits for LCD_WF46_BPBLCD46. */

/*! @brief Read current value of the LCD_WF46_BPBLCD46 field. */
#define BR_LCD_WF46_BPBLCD46(x) (BME_UBFX8(HW_LCD_WF46_ADDR(x), BP_LCD_WF46_BPBLCD46, BS_LCD_WF46_BPBLCD46))

/*! @brief Format value for bitfield LCD_WF46_BPBLCD46. */
#define BF_LCD_WF46_BPBLCD46(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF46_BPBLCD46) & BM_LCD_WF46_BPBLCD46)

/*! @brief Set the BPBLCD46 field to a new value. */
#define BW_LCD_WF46_BPBLCD46(x, v) (BME_BFI8(HW_LCD_WF46_ADDR(x), ((uint8_t)(v) << BP_LCD_WF46_BPBLCD46), BP_LCD_WF46_BPBLCD46, 1))
/*@}*/

/*!
 * @name Register LCD_WF46, field BPCLCD46[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF46_BPCLCD46 (2U)          /*!< Bit position for LCD_WF46_BPCLCD46. */
#define BM_LCD_WF46_BPCLCD46 (0x04U)       /*!< Bit mask for LCD_WF46_BPCLCD46. */
#define BS_LCD_WF46_BPCLCD46 (1U)          /*!< Bit field size in bits for LCD_WF46_BPCLCD46. */

/*! @brief Read current value of the LCD_WF46_BPCLCD46 field. */
#define BR_LCD_WF46_BPCLCD46(x) (BME_UBFX8(HW_LCD_WF46_ADDR(x), BP_LCD_WF46_BPCLCD46, BS_LCD_WF46_BPCLCD46))

/*! @brief Format value for bitfield LCD_WF46_BPCLCD46. */
#define BF_LCD_WF46_BPCLCD46(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF46_BPCLCD46) & BM_LCD_WF46_BPCLCD46)

/*! @brief Set the BPCLCD46 field to a new value. */
#define BW_LCD_WF46_BPCLCD46(x, v) (BME_BFI8(HW_LCD_WF46_ADDR(x), ((uint8_t)(v) << BP_LCD_WF46_BPCLCD46), BP_LCD_WF46_BPCLCD46, 1))
/*@}*/

/*!
 * @name Register LCD_WF46, field BPDLCD46[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF46_BPDLCD46 (3U)          /*!< Bit position for LCD_WF46_BPDLCD46. */
#define BM_LCD_WF46_BPDLCD46 (0x08U)       /*!< Bit mask for LCD_WF46_BPDLCD46. */
#define BS_LCD_WF46_BPDLCD46 (1U)          /*!< Bit field size in bits for LCD_WF46_BPDLCD46. */

/*! @brief Read current value of the LCD_WF46_BPDLCD46 field. */
#define BR_LCD_WF46_BPDLCD46(x) (BME_UBFX8(HW_LCD_WF46_ADDR(x), BP_LCD_WF46_BPDLCD46, BS_LCD_WF46_BPDLCD46))

/*! @brief Format value for bitfield LCD_WF46_BPDLCD46. */
#define BF_LCD_WF46_BPDLCD46(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF46_BPDLCD46) & BM_LCD_WF46_BPDLCD46)

/*! @brief Set the BPDLCD46 field to a new value. */
#define BW_LCD_WF46_BPDLCD46(x, v) (BME_BFI8(HW_LCD_WF46_ADDR(x), ((uint8_t)(v) << BP_LCD_WF46_BPDLCD46), BP_LCD_WF46_BPDLCD46, 1))
/*@}*/

/*!
 * @name Register LCD_WF46, field BPELCD46[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF46_BPELCD46 (4U)          /*!< Bit position for LCD_WF46_BPELCD46. */
#define BM_LCD_WF46_BPELCD46 (0x10U)       /*!< Bit mask for LCD_WF46_BPELCD46. */
#define BS_LCD_WF46_BPELCD46 (1U)          /*!< Bit field size in bits for LCD_WF46_BPELCD46. */

/*! @brief Read current value of the LCD_WF46_BPELCD46 field. */
#define BR_LCD_WF46_BPELCD46(x) (BME_UBFX8(HW_LCD_WF46_ADDR(x), BP_LCD_WF46_BPELCD46, BS_LCD_WF46_BPELCD46))

/*! @brief Format value for bitfield LCD_WF46_BPELCD46. */
#define BF_LCD_WF46_BPELCD46(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF46_BPELCD46) & BM_LCD_WF46_BPELCD46)

/*! @brief Set the BPELCD46 field to a new value. */
#define BW_LCD_WF46_BPELCD46(x, v) (BME_BFI8(HW_LCD_WF46_ADDR(x), ((uint8_t)(v) << BP_LCD_WF46_BPELCD46), BP_LCD_WF46_BPELCD46, 1))
/*@}*/

/*!
 * @name Register LCD_WF46, field BPFLCD46[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF46_BPFLCD46 (5U)          /*!< Bit position for LCD_WF46_BPFLCD46. */
#define BM_LCD_WF46_BPFLCD46 (0x20U)       /*!< Bit mask for LCD_WF46_BPFLCD46. */
#define BS_LCD_WF46_BPFLCD46 (1U)          /*!< Bit field size in bits for LCD_WF46_BPFLCD46. */

/*! @brief Read current value of the LCD_WF46_BPFLCD46 field. */
#define BR_LCD_WF46_BPFLCD46(x) (BME_UBFX8(HW_LCD_WF46_ADDR(x), BP_LCD_WF46_BPFLCD46, BS_LCD_WF46_BPFLCD46))

/*! @brief Format value for bitfield LCD_WF46_BPFLCD46. */
#define BF_LCD_WF46_BPFLCD46(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF46_BPFLCD46) & BM_LCD_WF46_BPFLCD46)

/*! @brief Set the BPFLCD46 field to a new value. */
#define BW_LCD_WF46_BPFLCD46(x, v) (BME_BFI8(HW_LCD_WF46_ADDR(x), ((uint8_t)(v) << BP_LCD_WF46_BPFLCD46), BP_LCD_WF46_BPFLCD46, 1))
/*@}*/

/*!
 * @name Register LCD_WF46, field BPGLCD46[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF46_BPGLCD46 (6U)          /*!< Bit position for LCD_WF46_BPGLCD46. */
#define BM_LCD_WF46_BPGLCD46 (0x40U)       /*!< Bit mask for LCD_WF46_BPGLCD46. */
#define BS_LCD_WF46_BPGLCD46 (1U)          /*!< Bit field size in bits for LCD_WF46_BPGLCD46. */

/*! @brief Read current value of the LCD_WF46_BPGLCD46 field. */
#define BR_LCD_WF46_BPGLCD46(x) (BME_UBFX8(HW_LCD_WF46_ADDR(x), BP_LCD_WF46_BPGLCD46, BS_LCD_WF46_BPGLCD46))

/*! @brief Format value for bitfield LCD_WF46_BPGLCD46. */
#define BF_LCD_WF46_BPGLCD46(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF46_BPGLCD46) & BM_LCD_WF46_BPGLCD46)

/*! @brief Set the BPGLCD46 field to a new value. */
#define BW_LCD_WF46_BPGLCD46(x, v) (BME_BFI8(HW_LCD_WF46_ADDR(x), ((uint8_t)(v) << BP_LCD_WF46_BPGLCD46), BP_LCD_WF46_BPGLCD46, 1))
/*@}*/

/*!
 * @name Register LCD_WF46, field BPHLCD46[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF46_BPHLCD46 (7U)          /*!< Bit position for LCD_WF46_BPHLCD46. */
#define BM_LCD_WF46_BPHLCD46 (0x80U)       /*!< Bit mask for LCD_WF46_BPHLCD46. */
#define BS_LCD_WF46_BPHLCD46 (1U)          /*!< Bit field size in bits for LCD_WF46_BPHLCD46. */

/*! @brief Read current value of the LCD_WF46_BPHLCD46 field. */
#define BR_LCD_WF46_BPHLCD46(x) (BME_UBFX8(HW_LCD_WF46_ADDR(x), BP_LCD_WF46_BPHLCD46, BS_LCD_WF46_BPHLCD46))

/*! @brief Format value for bitfield LCD_WF46_BPHLCD46. */
#define BF_LCD_WF46_BPHLCD46(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF46_BPHLCD46) & BM_LCD_WF46_BPHLCD46)

/*! @brief Set the BPHLCD46 field to a new value. */
#define BW_LCD_WF46_BPHLCD46(x, v) (BME_BFI8(HW_LCD_WF46_ADDR(x), ((uint8_t)(v) << BP_LCD_WF46_BPHLCD46), BP_LCD_WF46_BPHLCD46, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF47 - LCD Waveform Register 47.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF47 - LCD Waveform Register 47. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf47
{
    uint8_t U;
    struct _hw_lcd_wf47_bitfields
    {
        uint8_t BPALCD47 : 1;          /*!< [0]  */
        uint8_t BPBLCD47 : 1;          /*!< [1]  */
        uint8_t BPCLCD47 : 1;          /*!< [2]  */
        uint8_t BPDLCD47 : 1;          /*!< [3]  */
        uint8_t BPELCD47 : 1;          /*!< [4]  */
        uint8_t BPFLCD47 : 1;          /*!< [5]  */
        uint8_t BPGLCD47 : 1;          /*!< [6]  */
        uint8_t BPHLCD47 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf47_t;

/*!
 * @name Constants and macros for entire LCD_WF47 register
 */
/*@{*/
#define HW_LCD_WF47_ADDR(x)      ((x) + 0x4FU)

#define HW_LCD_WF47(x)           (*(__IO hw_lcd_wf47_t *) HW_LCD_WF47_ADDR(x))
#define HW_LCD_WF47_RD(x)        (HW_LCD_WF47(x).U)
#define HW_LCD_WF47_WR(x, v)     (HW_LCD_WF47(x).U = (v))
#define HW_LCD_WF47_SET(x, v)    (BME_OR8(HW_LCD_WF47_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF47_CLR(x, v)    (BME_AND8(HW_LCD_WF47_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF47_TOG(x, v)    (BME_XOR8(HW_LCD_WF47_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF47 bitfields
 */

/*!
 * @name Register LCD_WF47, field BPALCD47[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF47_BPALCD47 (0U)          /*!< Bit position for LCD_WF47_BPALCD47. */
#define BM_LCD_WF47_BPALCD47 (0x01U)       /*!< Bit mask for LCD_WF47_BPALCD47. */
#define BS_LCD_WF47_BPALCD47 (1U)          /*!< Bit field size in bits for LCD_WF47_BPALCD47. */

/*! @brief Read current value of the LCD_WF47_BPALCD47 field. */
#define BR_LCD_WF47_BPALCD47(x) (BME_UBFX8(HW_LCD_WF47_ADDR(x), BP_LCD_WF47_BPALCD47, BS_LCD_WF47_BPALCD47))

/*! @brief Format value for bitfield LCD_WF47_BPALCD47. */
#define BF_LCD_WF47_BPALCD47(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF47_BPALCD47) & BM_LCD_WF47_BPALCD47)

/*! @brief Set the BPALCD47 field to a new value. */
#define BW_LCD_WF47_BPALCD47(x, v) (BME_BFI8(HW_LCD_WF47_ADDR(x), ((uint8_t)(v) << BP_LCD_WF47_BPALCD47), BP_LCD_WF47_BPALCD47, 1))
/*@}*/

/*!
 * @name Register LCD_WF47, field BPBLCD47[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF47_BPBLCD47 (1U)          /*!< Bit position for LCD_WF47_BPBLCD47. */
#define BM_LCD_WF47_BPBLCD47 (0x02U)       /*!< Bit mask for LCD_WF47_BPBLCD47. */
#define BS_LCD_WF47_BPBLCD47 (1U)          /*!< Bit field size in bits for LCD_WF47_BPBLCD47. */

/*! @brief Read current value of the LCD_WF47_BPBLCD47 field. */
#define BR_LCD_WF47_BPBLCD47(x) (BME_UBFX8(HW_LCD_WF47_ADDR(x), BP_LCD_WF47_BPBLCD47, BS_LCD_WF47_BPBLCD47))

/*! @brief Format value for bitfield LCD_WF47_BPBLCD47. */
#define BF_LCD_WF47_BPBLCD47(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF47_BPBLCD47) & BM_LCD_WF47_BPBLCD47)

/*! @brief Set the BPBLCD47 field to a new value. */
#define BW_LCD_WF47_BPBLCD47(x, v) (BME_BFI8(HW_LCD_WF47_ADDR(x), ((uint8_t)(v) << BP_LCD_WF47_BPBLCD47), BP_LCD_WF47_BPBLCD47, 1))
/*@}*/

/*!
 * @name Register LCD_WF47, field BPCLCD47[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF47_BPCLCD47 (2U)          /*!< Bit position for LCD_WF47_BPCLCD47. */
#define BM_LCD_WF47_BPCLCD47 (0x04U)       /*!< Bit mask for LCD_WF47_BPCLCD47. */
#define BS_LCD_WF47_BPCLCD47 (1U)          /*!< Bit field size in bits for LCD_WF47_BPCLCD47. */

/*! @brief Read current value of the LCD_WF47_BPCLCD47 field. */
#define BR_LCD_WF47_BPCLCD47(x) (BME_UBFX8(HW_LCD_WF47_ADDR(x), BP_LCD_WF47_BPCLCD47, BS_LCD_WF47_BPCLCD47))

/*! @brief Format value for bitfield LCD_WF47_BPCLCD47. */
#define BF_LCD_WF47_BPCLCD47(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF47_BPCLCD47) & BM_LCD_WF47_BPCLCD47)

/*! @brief Set the BPCLCD47 field to a new value. */
#define BW_LCD_WF47_BPCLCD47(x, v) (BME_BFI8(HW_LCD_WF47_ADDR(x), ((uint8_t)(v) << BP_LCD_WF47_BPCLCD47), BP_LCD_WF47_BPCLCD47, 1))
/*@}*/

/*!
 * @name Register LCD_WF47, field BPDLCD47[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF47_BPDLCD47 (3U)          /*!< Bit position for LCD_WF47_BPDLCD47. */
#define BM_LCD_WF47_BPDLCD47 (0x08U)       /*!< Bit mask for LCD_WF47_BPDLCD47. */
#define BS_LCD_WF47_BPDLCD47 (1U)          /*!< Bit field size in bits for LCD_WF47_BPDLCD47. */

/*! @brief Read current value of the LCD_WF47_BPDLCD47 field. */
#define BR_LCD_WF47_BPDLCD47(x) (BME_UBFX8(HW_LCD_WF47_ADDR(x), BP_LCD_WF47_BPDLCD47, BS_LCD_WF47_BPDLCD47))

/*! @brief Format value for bitfield LCD_WF47_BPDLCD47. */
#define BF_LCD_WF47_BPDLCD47(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF47_BPDLCD47) & BM_LCD_WF47_BPDLCD47)

/*! @brief Set the BPDLCD47 field to a new value. */
#define BW_LCD_WF47_BPDLCD47(x, v) (BME_BFI8(HW_LCD_WF47_ADDR(x), ((uint8_t)(v) << BP_LCD_WF47_BPDLCD47), BP_LCD_WF47_BPDLCD47, 1))
/*@}*/

/*!
 * @name Register LCD_WF47, field BPELCD47[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF47_BPELCD47 (4U)          /*!< Bit position for LCD_WF47_BPELCD47. */
#define BM_LCD_WF47_BPELCD47 (0x10U)       /*!< Bit mask for LCD_WF47_BPELCD47. */
#define BS_LCD_WF47_BPELCD47 (1U)          /*!< Bit field size in bits for LCD_WF47_BPELCD47. */

/*! @brief Read current value of the LCD_WF47_BPELCD47 field. */
#define BR_LCD_WF47_BPELCD47(x) (BME_UBFX8(HW_LCD_WF47_ADDR(x), BP_LCD_WF47_BPELCD47, BS_LCD_WF47_BPELCD47))

/*! @brief Format value for bitfield LCD_WF47_BPELCD47. */
#define BF_LCD_WF47_BPELCD47(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF47_BPELCD47) & BM_LCD_WF47_BPELCD47)

/*! @brief Set the BPELCD47 field to a new value. */
#define BW_LCD_WF47_BPELCD47(x, v) (BME_BFI8(HW_LCD_WF47_ADDR(x), ((uint8_t)(v) << BP_LCD_WF47_BPELCD47), BP_LCD_WF47_BPELCD47, 1))
/*@}*/

/*!
 * @name Register LCD_WF47, field BPFLCD47[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF47_BPFLCD47 (5U)          /*!< Bit position for LCD_WF47_BPFLCD47. */
#define BM_LCD_WF47_BPFLCD47 (0x20U)       /*!< Bit mask for LCD_WF47_BPFLCD47. */
#define BS_LCD_WF47_BPFLCD47 (1U)          /*!< Bit field size in bits for LCD_WF47_BPFLCD47. */

/*! @brief Read current value of the LCD_WF47_BPFLCD47 field. */
#define BR_LCD_WF47_BPFLCD47(x) (BME_UBFX8(HW_LCD_WF47_ADDR(x), BP_LCD_WF47_BPFLCD47, BS_LCD_WF47_BPFLCD47))

/*! @brief Format value for bitfield LCD_WF47_BPFLCD47. */
#define BF_LCD_WF47_BPFLCD47(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF47_BPFLCD47) & BM_LCD_WF47_BPFLCD47)

/*! @brief Set the BPFLCD47 field to a new value. */
#define BW_LCD_WF47_BPFLCD47(x, v) (BME_BFI8(HW_LCD_WF47_ADDR(x), ((uint8_t)(v) << BP_LCD_WF47_BPFLCD47), BP_LCD_WF47_BPFLCD47, 1))
/*@}*/

/*!
 * @name Register LCD_WF47, field BPGLCD47[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF47_BPGLCD47 (6U)          /*!< Bit position for LCD_WF47_BPGLCD47. */
#define BM_LCD_WF47_BPGLCD47 (0x40U)       /*!< Bit mask for LCD_WF47_BPGLCD47. */
#define BS_LCD_WF47_BPGLCD47 (1U)          /*!< Bit field size in bits for LCD_WF47_BPGLCD47. */

/*! @brief Read current value of the LCD_WF47_BPGLCD47 field. */
#define BR_LCD_WF47_BPGLCD47(x) (BME_UBFX8(HW_LCD_WF47_ADDR(x), BP_LCD_WF47_BPGLCD47, BS_LCD_WF47_BPGLCD47))

/*! @brief Format value for bitfield LCD_WF47_BPGLCD47. */
#define BF_LCD_WF47_BPGLCD47(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF47_BPGLCD47) & BM_LCD_WF47_BPGLCD47)

/*! @brief Set the BPGLCD47 field to a new value. */
#define BW_LCD_WF47_BPGLCD47(x, v) (BME_BFI8(HW_LCD_WF47_ADDR(x), ((uint8_t)(v) << BP_LCD_WF47_BPGLCD47), BP_LCD_WF47_BPGLCD47, 1))
/*@}*/

/*!
 * @name Register LCD_WF47, field BPHLCD47[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF47_BPHLCD47 (7U)          /*!< Bit position for LCD_WF47_BPHLCD47. */
#define BM_LCD_WF47_BPHLCD47 (0x80U)       /*!< Bit mask for LCD_WF47_BPHLCD47. */
#define BS_LCD_WF47_BPHLCD47 (1U)          /*!< Bit field size in bits for LCD_WF47_BPHLCD47. */

/*! @brief Read current value of the LCD_WF47_BPHLCD47 field. */
#define BR_LCD_WF47_BPHLCD47(x) (BME_UBFX8(HW_LCD_WF47_ADDR(x), BP_LCD_WF47_BPHLCD47, BS_LCD_WF47_BPHLCD47))

/*! @brief Format value for bitfield LCD_WF47_BPHLCD47. */
#define BF_LCD_WF47_BPHLCD47(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF47_BPHLCD47) & BM_LCD_WF47_BPHLCD47)

/*! @brief Set the BPHLCD47 field to a new value. */
#define BW_LCD_WF47_BPHLCD47(x, v) (BME_BFI8(HW_LCD_WF47_ADDR(x), ((uint8_t)(v) << BP_LCD_WF47_BPHLCD47), BP_LCD_WF47_BPHLCD47, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF48 - LCD Waveform Register 48.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF48 - LCD Waveform Register 48. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf48
{
    uint8_t U;
    struct _hw_lcd_wf48_bitfields
    {
        uint8_t BPALCD48 : 1;          /*!< [0]  */
        uint8_t BPBLCD48 : 1;          /*!< [1]  */
        uint8_t BPCLCD48 : 1;          /*!< [2]  */
        uint8_t BPDLCD48 : 1;          /*!< [3]  */
        uint8_t BPELCD48 : 1;          /*!< [4]  */
        uint8_t BPFLCD48 : 1;          /*!< [5]  */
        uint8_t BPGLCD48 : 1;          /*!< [6]  */
        uint8_t BPHLCD48 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf48_t;

/*!
 * @name Constants and macros for entire LCD_WF48 register
 */
/*@{*/
#define HW_LCD_WF48_ADDR(x)      ((x) + 0x50U)

#define HW_LCD_WF48(x)           (*(__IO hw_lcd_wf48_t *) HW_LCD_WF48_ADDR(x))
#define HW_LCD_WF48_RD(x)        (HW_LCD_WF48(x).U)
#define HW_LCD_WF48_WR(x, v)     (HW_LCD_WF48(x).U = (v))
#define HW_LCD_WF48_SET(x, v)    (BME_OR8(HW_LCD_WF48_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF48_CLR(x, v)    (BME_AND8(HW_LCD_WF48_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF48_TOG(x, v)    (BME_XOR8(HW_LCD_WF48_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF48 bitfields
 */

/*!
 * @name Register LCD_WF48, field BPALCD48[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF48_BPALCD48 (0U)          /*!< Bit position for LCD_WF48_BPALCD48. */
#define BM_LCD_WF48_BPALCD48 (0x01U)       /*!< Bit mask for LCD_WF48_BPALCD48. */
#define BS_LCD_WF48_BPALCD48 (1U)          /*!< Bit field size in bits for LCD_WF48_BPALCD48. */

/*! @brief Read current value of the LCD_WF48_BPALCD48 field. */
#define BR_LCD_WF48_BPALCD48(x) (BME_UBFX8(HW_LCD_WF48_ADDR(x), BP_LCD_WF48_BPALCD48, BS_LCD_WF48_BPALCD48))

/*! @brief Format value for bitfield LCD_WF48_BPALCD48. */
#define BF_LCD_WF48_BPALCD48(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF48_BPALCD48) & BM_LCD_WF48_BPALCD48)

/*! @brief Set the BPALCD48 field to a new value. */
#define BW_LCD_WF48_BPALCD48(x, v) (BME_BFI8(HW_LCD_WF48_ADDR(x), ((uint8_t)(v) << BP_LCD_WF48_BPALCD48), BP_LCD_WF48_BPALCD48, 1))
/*@}*/

/*!
 * @name Register LCD_WF48, field BPBLCD48[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF48_BPBLCD48 (1U)          /*!< Bit position for LCD_WF48_BPBLCD48. */
#define BM_LCD_WF48_BPBLCD48 (0x02U)       /*!< Bit mask for LCD_WF48_BPBLCD48. */
#define BS_LCD_WF48_BPBLCD48 (1U)          /*!< Bit field size in bits for LCD_WF48_BPBLCD48. */

/*! @brief Read current value of the LCD_WF48_BPBLCD48 field. */
#define BR_LCD_WF48_BPBLCD48(x) (BME_UBFX8(HW_LCD_WF48_ADDR(x), BP_LCD_WF48_BPBLCD48, BS_LCD_WF48_BPBLCD48))

/*! @brief Format value for bitfield LCD_WF48_BPBLCD48. */
#define BF_LCD_WF48_BPBLCD48(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF48_BPBLCD48) & BM_LCD_WF48_BPBLCD48)

/*! @brief Set the BPBLCD48 field to a new value. */
#define BW_LCD_WF48_BPBLCD48(x, v) (BME_BFI8(HW_LCD_WF48_ADDR(x), ((uint8_t)(v) << BP_LCD_WF48_BPBLCD48), BP_LCD_WF48_BPBLCD48, 1))
/*@}*/

/*!
 * @name Register LCD_WF48, field BPCLCD48[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF48_BPCLCD48 (2U)          /*!< Bit position for LCD_WF48_BPCLCD48. */
#define BM_LCD_WF48_BPCLCD48 (0x04U)       /*!< Bit mask for LCD_WF48_BPCLCD48. */
#define BS_LCD_WF48_BPCLCD48 (1U)          /*!< Bit field size in bits for LCD_WF48_BPCLCD48. */

/*! @brief Read current value of the LCD_WF48_BPCLCD48 field. */
#define BR_LCD_WF48_BPCLCD48(x) (BME_UBFX8(HW_LCD_WF48_ADDR(x), BP_LCD_WF48_BPCLCD48, BS_LCD_WF48_BPCLCD48))

/*! @brief Format value for bitfield LCD_WF48_BPCLCD48. */
#define BF_LCD_WF48_BPCLCD48(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF48_BPCLCD48) & BM_LCD_WF48_BPCLCD48)

/*! @brief Set the BPCLCD48 field to a new value. */
#define BW_LCD_WF48_BPCLCD48(x, v) (BME_BFI8(HW_LCD_WF48_ADDR(x), ((uint8_t)(v) << BP_LCD_WF48_BPCLCD48), BP_LCD_WF48_BPCLCD48, 1))
/*@}*/

/*!
 * @name Register LCD_WF48, field BPDLCD48[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF48_BPDLCD48 (3U)          /*!< Bit position for LCD_WF48_BPDLCD48. */
#define BM_LCD_WF48_BPDLCD48 (0x08U)       /*!< Bit mask for LCD_WF48_BPDLCD48. */
#define BS_LCD_WF48_BPDLCD48 (1U)          /*!< Bit field size in bits for LCD_WF48_BPDLCD48. */

/*! @brief Read current value of the LCD_WF48_BPDLCD48 field. */
#define BR_LCD_WF48_BPDLCD48(x) (BME_UBFX8(HW_LCD_WF48_ADDR(x), BP_LCD_WF48_BPDLCD48, BS_LCD_WF48_BPDLCD48))

/*! @brief Format value for bitfield LCD_WF48_BPDLCD48. */
#define BF_LCD_WF48_BPDLCD48(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF48_BPDLCD48) & BM_LCD_WF48_BPDLCD48)

/*! @brief Set the BPDLCD48 field to a new value. */
#define BW_LCD_WF48_BPDLCD48(x, v) (BME_BFI8(HW_LCD_WF48_ADDR(x), ((uint8_t)(v) << BP_LCD_WF48_BPDLCD48), BP_LCD_WF48_BPDLCD48, 1))
/*@}*/

/*!
 * @name Register LCD_WF48, field BPELCD48[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF48_BPELCD48 (4U)          /*!< Bit position for LCD_WF48_BPELCD48. */
#define BM_LCD_WF48_BPELCD48 (0x10U)       /*!< Bit mask for LCD_WF48_BPELCD48. */
#define BS_LCD_WF48_BPELCD48 (1U)          /*!< Bit field size in bits for LCD_WF48_BPELCD48. */

/*! @brief Read current value of the LCD_WF48_BPELCD48 field. */
#define BR_LCD_WF48_BPELCD48(x) (BME_UBFX8(HW_LCD_WF48_ADDR(x), BP_LCD_WF48_BPELCD48, BS_LCD_WF48_BPELCD48))

/*! @brief Format value for bitfield LCD_WF48_BPELCD48. */
#define BF_LCD_WF48_BPELCD48(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF48_BPELCD48) & BM_LCD_WF48_BPELCD48)

/*! @brief Set the BPELCD48 field to a new value. */
#define BW_LCD_WF48_BPELCD48(x, v) (BME_BFI8(HW_LCD_WF48_ADDR(x), ((uint8_t)(v) << BP_LCD_WF48_BPELCD48), BP_LCD_WF48_BPELCD48, 1))
/*@}*/

/*!
 * @name Register LCD_WF48, field BPFLCD48[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF48_BPFLCD48 (5U)          /*!< Bit position for LCD_WF48_BPFLCD48. */
#define BM_LCD_WF48_BPFLCD48 (0x20U)       /*!< Bit mask for LCD_WF48_BPFLCD48. */
#define BS_LCD_WF48_BPFLCD48 (1U)          /*!< Bit field size in bits for LCD_WF48_BPFLCD48. */

/*! @brief Read current value of the LCD_WF48_BPFLCD48 field. */
#define BR_LCD_WF48_BPFLCD48(x) (BME_UBFX8(HW_LCD_WF48_ADDR(x), BP_LCD_WF48_BPFLCD48, BS_LCD_WF48_BPFLCD48))

/*! @brief Format value for bitfield LCD_WF48_BPFLCD48. */
#define BF_LCD_WF48_BPFLCD48(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF48_BPFLCD48) & BM_LCD_WF48_BPFLCD48)

/*! @brief Set the BPFLCD48 field to a new value. */
#define BW_LCD_WF48_BPFLCD48(x, v) (BME_BFI8(HW_LCD_WF48_ADDR(x), ((uint8_t)(v) << BP_LCD_WF48_BPFLCD48), BP_LCD_WF48_BPFLCD48, 1))
/*@}*/

/*!
 * @name Register LCD_WF48, field BPGLCD48[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF48_BPGLCD48 (6U)          /*!< Bit position for LCD_WF48_BPGLCD48. */
#define BM_LCD_WF48_BPGLCD48 (0x40U)       /*!< Bit mask for LCD_WF48_BPGLCD48. */
#define BS_LCD_WF48_BPGLCD48 (1U)          /*!< Bit field size in bits for LCD_WF48_BPGLCD48. */

/*! @brief Read current value of the LCD_WF48_BPGLCD48 field. */
#define BR_LCD_WF48_BPGLCD48(x) (BME_UBFX8(HW_LCD_WF48_ADDR(x), BP_LCD_WF48_BPGLCD48, BS_LCD_WF48_BPGLCD48))

/*! @brief Format value for bitfield LCD_WF48_BPGLCD48. */
#define BF_LCD_WF48_BPGLCD48(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF48_BPGLCD48) & BM_LCD_WF48_BPGLCD48)

/*! @brief Set the BPGLCD48 field to a new value. */
#define BW_LCD_WF48_BPGLCD48(x, v) (BME_BFI8(HW_LCD_WF48_ADDR(x), ((uint8_t)(v) << BP_LCD_WF48_BPGLCD48), BP_LCD_WF48_BPGLCD48, 1))
/*@}*/

/*!
 * @name Register LCD_WF48, field BPHLCD48[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF48_BPHLCD48 (7U)          /*!< Bit position for LCD_WF48_BPHLCD48. */
#define BM_LCD_WF48_BPHLCD48 (0x80U)       /*!< Bit mask for LCD_WF48_BPHLCD48. */
#define BS_LCD_WF48_BPHLCD48 (1U)          /*!< Bit field size in bits for LCD_WF48_BPHLCD48. */

/*! @brief Read current value of the LCD_WF48_BPHLCD48 field. */
#define BR_LCD_WF48_BPHLCD48(x) (BME_UBFX8(HW_LCD_WF48_ADDR(x), BP_LCD_WF48_BPHLCD48, BS_LCD_WF48_BPHLCD48))

/*! @brief Format value for bitfield LCD_WF48_BPHLCD48. */
#define BF_LCD_WF48_BPHLCD48(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF48_BPHLCD48) & BM_LCD_WF48_BPHLCD48)

/*! @brief Set the BPHLCD48 field to a new value. */
#define BW_LCD_WF48_BPHLCD48(x, v) (BME_BFI8(HW_LCD_WF48_ADDR(x), ((uint8_t)(v) << BP_LCD_WF48_BPHLCD48), BP_LCD_WF48_BPHLCD48, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF49 - LCD Waveform Register 49.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF49 - LCD Waveform Register 49. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf49
{
    uint8_t U;
    struct _hw_lcd_wf49_bitfields
    {
        uint8_t BPALCD49 : 1;          /*!< [0]  */
        uint8_t BPBLCD49 : 1;          /*!< [1]  */
        uint8_t BPCLCD49 : 1;          /*!< [2]  */
        uint8_t BPDLCD49 : 1;          /*!< [3]  */
        uint8_t BPELCD49 : 1;          /*!< [4]  */
        uint8_t BPFLCD49 : 1;          /*!< [5]  */
        uint8_t BPGLCD49 : 1;          /*!< [6]  */
        uint8_t BPHLCD49 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf49_t;

/*!
 * @name Constants and macros for entire LCD_WF49 register
 */
/*@{*/
#define HW_LCD_WF49_ADDR(x)      ((x) + 0x51U)

#define HW_LCD_WF49(x)           (*(__IO hw_lcd_wf49_t *) HW_LCD_WF49_ADDR(x))
#define HW_LCD_WF49_RD(x)        (HW_LCD_WF49(x).U)
#define HW_LCD_WF49_WR(x, v)     (HW_LCD_WF49(x).U = (v))
#define HW_LCD_WF49_SET(x, v)    (BME_OR8(HW_LCD_WF49_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF49_CLR(x, v)    (BME_AND8(HW_LCD_WF49_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF49_TOG(x, v)    (BME_XOR8(HW_LCD_WF49_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF49 bitfields
 */

/*!
 * @name Register LCD_WF49, field BPALCD49[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF49_BPALCD49 (0U)          /*!< Bit position for LCD_WF49_BPALCD49. */
#define BM_LCD_WF49_BPALCD49 (0x01U)       /*!< Bit mask for LCD_WF49_BPALCD49. */
#define BS_LCD_WF49_BPALCD49 (1U)          /*!< Bit field size in bits for LCD_WF49_BPALCD49. */

/*! @brief Read current value of the LCD_WF49_BPALCD49 field. */
#define BR_LCD_WF49_BPALCD49(x) (BME_UBFX8(HW_LCD_WF49_ADDR(x), BP_LCD_WF49_BPALCD49, BS_LCD_WF49_BPALCD49))

/*! @brief Format value for bitfield LCD_WF49_BPALCD49. */
#define BF_LCD_WF49_BPALCD49(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF49_BPALCD49) & BM_LCD_WF49_BPALCD49)

/*! @brief Set the BPALCD49 field to a new value. */
#define BW_LCD_WF49_BPALCD49(x, v) (BME_BFI8(HW_LCD_WF49_ADDR(x), ((uint8_t)(v) << BP_LCD_WF49_BPALCD49), BP_LCD_WF49_BPALCD49, 1))
/*@}*/

/*!
 * @name Register LCD_WF49, field BPBLCD49[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF49_BPBLCD49 (1U)          /*!< Bit position for LCD_WF49_BPBLCD49. */
#define BM_LCD_WF49_BPBLCD49 (0x02U)       /*!< Bit mask for LCD_WF49_BPBLCD49. */
#define BS_LCD_WF49_BPBLCD49 (1U)          /*!< Bit field size in bits for LCD_WF49_BPBLCD49. */

/*! @brief Read current value of the LCD_WF49_BPBLCD49 field. */
#define BR_LCD_WF49_BPBLCD49(x) (BME_UBFX8(HW_LCD_WF49_ADDR(x), BP_LCD_WF49_BPBLCD49, BS_LCD_WF49_BPBLCD49))

/*! @brief Format value for bitfield LCD_WF49_BPBLCD49. */
#define BF_LCD_WF49_BPBLCD49(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF49_BPBLCD49) & BM_LCD_WF49_BPBLCD49)

/*! @brief Set the BPBLCD49 field to a new value. */
#define BW_LCD_WF49_BPBLCD49(x, v) (BME_BFI8(HW_LCD_WF49_ADDR(x), ((uint8_t)(v) << BP_LCD_WF49_BPBLCD49), BP_LCD_WF49_BPBLCD49, 1))
/*@}*/

/*!
 * @name Register LCD_WF49, field BPCLCD49[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF49_BPCLCD49 (2U)          /*!< Bit position for LCD_WF49_BPCLCD49. */
#define BM_LCD_WF49_BPCLCD49 (0x04U)       /*!< Bit mask for LCD_WF49_BPCLCD49. */
#define BS_LCD_WF49_BPCLCD49 (1U)          /*!< Bit field size in bits for LCD_WF49_BPCLCD49. */

/*! @brief Read current value of the LCD_WF49_BPCLCD49 field. */
#define BR_LCD_WF49_BPCLCD49(x) (BME_UBFX8(HW_LCD_WF49_ADDR(x), BP_LCD_WF49_BPCLCD49, BS_LCD_WF49_BPCLCD49))

/*! @brief Format value for bitfield LCD_WF49_BPCLCD49. */
#define BF_LCD_WF49_BPCLCD49(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF49_BPCLCD49) & BM_LCD_WF49_BPCLCD49)

/*! @brief Set the BPCLCD49 field to a new value. */
#define BW_LCD_WF49_BPCLCD49(x, v) (BME_BFI8(HW_LCD_WF49_ADDR(x), ((uint8_t)(v) << BP_LCD_WF49_BPCLCD49), BP_LCD_WF49_BPCLCD49, 1))
/*@}*/

/*!
 * @name Register LCD_WF49, field BPDLCD49[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF49_BPDLCD49 (3U)          /*!< Bit position for LCD_WF49_BPDLCD49. */
#define BM_LCD_WF49_BPDLCD49 (0x08U)       /*!< Bit mask for LCD_WF49_BPDLCD49. */
#define BS_LCD_WF49_BPDLCD49 (1U)          /*!< Bit field size in bits for LCD_WF49_BPDLCD49. */

/*! @brief Read current value of the LCD_WF49_BPDLCD49 field. */
#define BR_LCD_WF49_BPDLCD49(x) (BME_UBFX8(HW_LCD_WF49_ADDR(x), BP_LCD_WF49_BPDLCD49, BS_LCD_WF49_BPDLCD49))

/*! @brief Format value for bitfield LCD_WF49_BPDLCD49. */
#define BF_LCD_WF49_BPDLCD49(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF49_BPDLCD49) & BM_LCD_WF49_BPDLCD49)

/*! @brief Set the BPDLCD49 field to a new value. */
#define BW_LCD_WF49_BPDLCD49(x, v) (BME_BFI8(HW_LCD_WF49_ADDR(x), ((uint8_t)(v) << BP_LCD_WF49_BPDLCD49), BP_LCD_WF49_BPDLCD49, 1))
/*@}*/

/*!
 * @name Register LCD_WF49, field BPELCD49[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF49_BPELCD49 (4U)          /*!< Bit position for LCD_WF49_BPELCD49. */
#define BM_LCD_WF49_BPELCD49 (0x10U)       /*!< Bit mask for LCD_WF49_BPELCD49. */
#define BS_LCD_WF49_BPELCD49 (1U)          /*!< Bit field size in bits for LCD_WF49_BPELCD49. */

/*! @brief Read current value of the LCD_WF49_BPELCD49 field. */
#define BR_LCD_WF49_BPELCD49(x) (BME_UBFX8(HW_LCD_WF49_ADDR(x), BP_LCD_WF49_BPELCD49, BS_LCD_WF49_BPELCD49))

/*! @brief Format value for bitfield LCD_WF49_BPELCD49. */
#define BF_LCD_WF49_BPELCD49(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF49_BPELCD49) & BM_LCD_WF49_BPELCD49)

/*! @brief Set the BPELCD49 field to a new value. */
#define BW_LCD_WF49_BPELCD49(x, v) (BME_BFI8(HW_LCD_WF49_ADDR(x), ((uint8_t)(v) << BP_LCD_WF49_BPELCD49), BP_LCD_WF49_BPELCD49, 1))
/*@}*/

/*!
 * @name Register LCD_WF49, field BPFLCD49[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF49_BPFLCD49 (5U)          /*!< Bit position for LCD_WF49_BPFLCD49. */
#define BM_LCD_WF49_BPFLCD49 (0x20U)       /*!< Bit mask for LCD_WF49_BPFLCD49. */
#define BS_LCD_WF49_BPFLCD49 (1U)          /*!< Bit field size in bits for LCD_WF49_BPFLCD49. */

/*! @brief Read current value of the LCD_WF49_BPFLCD49 field. */
#define BR_LCD_WF49_BPFLCD49(x) (BME_UBFX8(HW_LCD_WF49_ADDR(x), BP_LCD_WF49_BPFLCD49, BS_LCD_WF49_BPFLCD49))

/*! @brief Format value for bitfield LCD_WF49_BPFLCD49. */
#define BF_LCD_WF49_BPFLCD49(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF49_BPFLCD49) & BM_LCD_WF49_BPFLCD49)

/*! @brief Set the BPFLCD49 field to a new value. */
#define BW_LCD_WF49_BPFLCD49(x, v) (BME_BFI8(HW_LCD_WF49_ADDR(x), ((uint8_t)(v) << BP_LCD_WF49_BPFLCD49), BP_LCD_WF49_BPFLCD49, 1))
/*@}*/

/*!
 * @name Register LCD_WF49, field BPGLCD49[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF49_BPGLCD49 (6U)          /*!< Bit position for LCD_WF49_BPGLCD49. */
#define BM_LCD_WF49_BPGLCD49 (0x40U)       /*!< Bit mask for LCD_WF49_BPGLCD49. */
#define BS_LCD_WF49_BPGLCD49 (1U)          /*!< Bit field size in bits for LCD_WF49_BPGLCD49. */

/*! @brief Read current value of the LCD_WF49_BPGLCD49 field. */
#define BR_LCD_WF49_BPGLCD49(x) (BME_UBFX8(HW_LCD_WF49_ADDR(x), BP_LCD_WF49_BPGLCD49, BS_LCD_WF49_BPGLCD49))

/*! @brief Format value for bitfield LCD_WF49_BPGLCD49. */
#define BF_LCD_WF49_BPGLCD49(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF49_BPGLCD49) & BM_LCD_WF49_BPGLCD49)

/*! @brief Set the BPGLCD49 field to a new value. */
#define BW_LCD_WF49_BPGLCD49(x, v) (BME_BFI8(HW_LCD_WF49_ADDR(x), ((uint8_t)(v) << BP_LCD_WF49_BPGLCD49), BP_LCD_WF49_BPGLCD49, 1))
/*@}*/

/*!
 * @name Register LCD_WF49, field BPHLCD49[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF49_BPHLCD49 (7U)          /*!< Bit position for LCD_WF49_BPHLCD49. */
#define BM_LCD_WF49_BPHLCD49 (0x80U)       /*!< Bit mask for LCD_WF49_BPHLCD49. */
#define BS_LCD_WF49_BPHLCD49 (1U)          /*!< Bit field size in bits for LCD_WF49_BPHLCD49. */

/*! @brief Read current value of the LCD_WF49_BPHLCD49 field. */
#define BR_LCD_WF49_BPHLCD49(x) (BME_UBFX8(HW_LCD_WF49_ADDR(x), BP_LCD_WF49_BPHLCD49, BS_LCD_WF49_BPHLCD49))

/*! @brief Format value for bitfield LCD_WF49_BPHLCD49. */
#define BF_LCD_WF49_BPHLCD49(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF49_BPHLCD49) & BM_LCD_WF49_BPHLCD49)

/*! @brief Set the BPHLCD49 field to a new value. */
#define BW_LCD_WF49_BPHLCD49(x, v) (BME_BFI8(HW_LCD_WF49_ADDR(x), ((uint8_t)(v) << BP_LCD_WF49_BPHLCD49), BP_LCD_WF49_BPHLCD49, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF50 - LCD Waveform Register 50.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF50 - LCD Waveform Register 50. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf50
{
    uint8_t U;
    struct _hw_lcd_wf50_bitfields
    {
        uint8_t BPALCD50 : 1;          /*!< [0]  */
        uint8_t BPBLCD50 : 1;          /*!< [1]  */
        uint8_t BPCLCD50 : 1;          /*!< [2]  */
        uint8_t BPDLCD50 : 1;          /*!< [3]  */
        uint8_t BPELCD50 : 1;          /*!< [4]  */
        uint8_t BPFLCD50 : 1;          /*!< [5]  */
        uint8_t BPGLCD50 : 1;          /*!< [6]  */
        uint8_t BPHLCD50 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf50_t;

/*!
 * @name Constants and macros for entire LCD_WF50 register
 */
/*@{*/
#define HW_LCD_WF50_ADDR(x)      ((x) + 0x52U)

#define HW_LCD_WF50(x)           (*(__IO hw_lcd_wf50_t *) HW_LCD_WF50_ADDR(x))
#define HW_LCD_WF50_RD(x)        (HW_LCD_WF50(x).U)
#define HW_LCD_WF50_WR(x, v)     (HW_LCD_WF50(x).U = (v))
#define HW_LCD_WF50_SET(x, v)    (BME_OR8(HW_LCD_WF50_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF50_CLR(x, v)    (BME_AND8(HW_LCD_WF50_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF50_TOG(x, v)    (BME_XOR8(HW_LCD_WF50_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF50 bitfields
 */

/*!
 * @name Register LCD_WF50, field BPALCD50[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF50_BPALCD50 (0U)          /*!< Bit position for LCD_WF50_BPALCD50. */
#define BM_LCD_WF50_BPALCD50 (0x01U)       /*!< Bit mask for LCD_WF50_BPALCD50. */
#define BS_LCD_WF50_BPALCD50 (1U)          /*!< Bit field size in bits for LCD_WF50_BPALCD50. */

/*! @brief Read current value of the LCD_WF50_BPALCD50 field. */
#define BR_LCD_WF50_BPALCD50(x) (BME_UBFX8(HW_LCD_WF50_ADDR(x), BP_LCD_WF50_BPALCD50, BS_LCD_WF50_BPALCD50))

/*! @brief Format value for bitfield LCD_WF50_BPALCD50. */
#define BF_LCD_WF50_BPALCD50(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF50_BPALCD50) & BM_LCD_WF50_BPALCD50)

/*! @brief Set the BPALCD50 field to a new value. */
#define BW_LCD_WF50_BPALCD50(x, v) (BME_BFI8(HW_LCD_WF50_ADDR(x), ((uint8_t)(v) << BP_LCD_WF50_BPALCD50), BP_LCD_WF50_BPALCD50, 1))
/*@}*/

/*!
 * @name Register LCD_WF50, field BPBLCD50[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF50_BPBLCD50 (1U)          /*!< Bit position for LCD_WF50_BPBLCD50. */
#define BM_LCD_WF50_BPBLCD50 (0x02U)       /*!< Bit mask for LCD_WF50_BPBLCD50. */
#define BS_LCD_WF50_BPBLCD50 (1U)          /*!< Bit field size in bits for LCD_WF50_BPBLCD50. */

/*! @brief Read current value of the LCD_WF50_BPBLCD50 field. */
#define BR_LCD_WF50_BPBLCD50(x) (BME_UBFX8(HW_LCD_WF50_ADDR(x), BP_LCD_WF50_BPBLCD50, BS_LCD_WF50_BPBLCD50))

/*! @brief Format value for bitfield LCD_WF50_BPBLCD50. */
#define BF_LCD_WF50_BPBLCD50(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF50_BPBLCD50) & BM_LCD_WF50_BPBLCD50)

/*! @brief Set the BPBLCD50 field to a new value. */
#define BW_LCD_WF50_BPBLCD50(x, v) (BME_BFI8(HW_LCD_WF50_ADDR(x), ((uint8_t)(v) << BP_LCD_WF50_BPBLCD50), BP_LCD_WF50_BPBLCD50, 1))
/*@}*/

/*!
 * @name Register LCD_WF50, field BPCLCD50[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF50_BPCLCD50 (2U)          /*!< Bit position for LCD_WF50_BPCLCD50. */
#define BM_LCD_WF50_BPCLCD50 (0x04U)       /*!< Bit mask for LCD_WF50_BPCLCD50. */
#define BS_LCD_WF50_BPCLCD50 (1U)          /*!< Bit field size in bits for LCD_WF50_BPCLCD50. */

/*! @brief Read current value of the LCD_WF50_BPCLCD50 field. */
#define BR_LCD_WF50_BPCLCD50(x) (BME_UBFX8(HW_LCD_WF50_ADDR(x), BP_LCD_WF50_BPCLCD50, BS_LCD_WF50_BPCLCD50))

/*! @brief Format value for bitfield LCD_WF50_BPCLCD50. */
#define BF_LCD_WF50_BPCLCD50(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF50_BPCLCD50) & BM_LCD_WF50_BPCLCD50)

/*! @brief Set the BPCLCD50 field to a new value. */
#define BW_LCD_WF50_BPCLCD50(x, v) (BME_BFI8(HW_LCD_WF50_ADDR(x), ((uint8_t)(v) << BP_LCD_WF50_BPCLCD50), BP_LCD_WF50_BPCLCD50, 1))
/*@}*/

/*!
 * @name Register LCD_WF50, field BPDLCD50[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF50_BPDLCD50 (3U)          /*!< Bit position for LCD_WF50_BPDLCD50. */
#define BM_LCD_WF50_BPDLCD50 (0x08U)       /*!< Bit mask for LCD_WF50_BPDLCD50. */
#define BS_LCD_WF50_BPDLCD50 (1U)          /*!< Bit field size in bits for LCD_WF50_BPDLCD50. */

/*! @brief Read current value of the LCD_WF50_BPDLCD50 field. */
#define BR_LCD_WF50_BPDLCD50(x) (BME_UBFX8(HW_LCD_WF50_ADDR(x), BP_LCD_WF50_BPDLCD50, BS_LCD_WF50_BPDLCD50))

/*! @brief Format value for bitfield LCD_WF50_BPDLCD50. */
#define BF_LCD_WF50_BPDLCD50(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF50_BPDLCD50) & BM_LCD_WF50_BPDLCD50)

/*! @brief Set the BPDLCD50 field to a new value. */
#define BW_LCD_WF50_BPDLCD50(x, v) (BME_BFI8(HW_LCD_WF50_ADDR(x), ((uint8_t)(v) << BP_LCD_WF50_BPDLCD50), BP_LCD_WF50_BPDLCD50, 1))
/*@}*/

/*!
 * @name Register LCD_WF50, field BPELCD50[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF50_BPELCD50 (4U)          /*!< Bit position for LCD_WF50_BPELCD50. */
#define BM_LCD_WF50_BPELCD50 (0x10U)       /*!< Bit mask for LCD_WF50_BPELCD50. */
#define BS_LCD_WF50_BPELCD50 (1U)          /*!< Bit field size in bits for LCD_WF50_BPELCD50. */

/*! @brief Read current value of the LCD_WF50_BPELCD50 field. */
#define BR_LCD_WF50_BPELCD50(x) (BME_UBFX8(HW_LCD_WF50_ADDR(x), BP_LCD_WF50_BPELCD50, BS_LCD_WF50_BPELCD50))

/*! @brief Format value for bitfield LCD_WF50_BPELCD50. */
#define BF_LCD_WF50_BPELCD50(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF50_BPELCD50) & BM_LCD_WF50_BPELCD50)

/*! @brief Set the BPELCD50 field to a new value. */
#define BW_LCD_WF50_BPELCD50(x, v) (BME_BFI8(HW_LCD_WF50_ADDR(x), ((uint8_t)(v) << BP_LCD_WF50_BPELCD50), BP_LCD_WF50_BPELCD50, 1))
/*@}*/

/*!
 * @name Register LCD_WF50, field BPFLCD50[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF50_BPFLCD50 (5U)          /*!< Bit position for LCD_WF50_BPFLCD50. */
#define BM_LCD_WF50_BPFLCD50 (0x20U)       /*!< Bit mask for LCD_WF50_BPFLCD50. */
#define BS_LCD_WF50_BPFLCD50 (1U)          /*!< Bit field size in bits for LCD_WF50_BPFLCD50. */

/*! @brief Read current value of the LCD_WF50_BPFLCD50 field. */
#define BR_LCD_WF50_BPFLCD50(x) (BME_UBFX8(HW_LCD_WF50_ADDR(x), BP_LCD_WF50_BPFLCD50, BS_LCD_WF50_BPFLCD50))

/*! @brief Format value for bitfield LCD_WF50_BPFLCD50. */
#define BF_LCD_WF50_BPFLCD50(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF50_BPFLCD50) & BM_LCD_WF50_BPFLCD50)

/*! @brief Set the BPFLCD50 field to a new value. */
#define BW_LCD_WF50_BPFLCD50(x, v) (BME_BFI8(HW_LCD_WF50_ADDR(x), ((uint8_t)(v) << BP_LCD_WF50_BPFLCD50), BP_LCD_WF50_BPFLCD50, 1))
/*@}*/

/*!
 * @name Register LCD_WF50, field BPGLCD50[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF50_BPGLCD50 (6U)          /*!< Bit position for LCD_WF50_BPGLCD50. */
#define BM_LCD_WF50_BPGLCD50 (0x40U)       /*!< Bit mask for LCD_WF50_BPGLCD50. */
#define BS_LCD_WF50_BPGLCD50 (1U)          /*!< Bit field size in bits for LCD_WF50_BPGLCD50. */

/*! @brief Read current value of the LCD_WF50_BPGLCD50 field. */
#define BR_LCD_WF50_BPGLCD50(x) (BME_UBFX8(HW_LCD_WF50_ADDR(x), BP_LCD_WF50_BPGLCD50, BS_LCD_WF50_BPGLCD50))

/*! @brief Format value for bitfield LCD_WF50_BPGLCD50. */
#define BF_LCD_WF50_BPGLCD50(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF50_BPGLCD50) & BM_LCD_WF50_BPGLCD50)

/*! @brief Set the BPGLCD50 field to a new value. */
#define BW_LCD_WF50_BPGLCD50(x, v) (BME_BFI8(HW_LCD_WF50_ADDR(x), ((uint8_t)(v) << BP_LCD_WF50_BPGLCD50), BP_LCD_WF50_BPGLCD50, 1))
/*@}*/

/*!
 * @name Register LCD_WF50, field BPHLCD50[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF50_BPHLCD50 (7U)          /*!< Bit position for LCD_WF50_BPHLCD50. */
#define BM_LCD_WF50_BPHLCD50 (0x80U)       /*!< Bit mask for LCD_WF50_BPHLCD50. */
#define BS_LCD_WF50_BPHLCD50 (1U)          /*!< Bit field size in bits for LCD_WF50_BPHLCD50. */

/*! @brief Read current value of the LCD_WF50_BPHLCD50 field. */
#define BR_LCD_WF50_BPHLCD50(x) (BME_UBFX8(HW_LCD_WF50_ADDR(x), BP_LCD_WF50_BPHLCD50, BS_LCD_WF50_BPHLCD50))

/*! @brief Format value for bitfield LCD_WF50_BPHLCD50. */
#define BF_LCD_WF50_BPHLCD50(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF50_BPHLCD50) & BM_LCD_WF50_BPHLCD50)

/*! @brief Set the BPHLCD50 field to a new value. */
#define BW_LCD_WF50_BPHLCD50(x, v) (BME_BFI8(HW_LCD_WF50_ADDR(x), ((uint8_t)(v) << BP_LCD_WF50_BPHLCD50), BP_LCD_WF50_BPHLCD50, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF51 - LCD Waveform Register 51.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF51 - LCD Waveform Register 51. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf51
{
    uint8_t U;
    struct _hw_lcd_wf51_bitfields
    {
        uint8_t BPALCD51 : 1;          /*!< [0]  */
        uint8_t BPBLCD51 : 1;          /*!< [1]  */
        uint8_t BPCLCD51 : 1;          /*!< [2]  */
        uint8_t BPDLCD51 : 1;          /*!< [3]  */
        uint8_t BPELCD51 : 1;          /*!< [4]  */
        uint8_t BPFLCD51 : 1;          /*!< [5]  */
        uint8_t BPGLCD51 : 1;          /*!< [6]  */
        uint8_t BPHLCD51 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf51_t;

/*!
 * @name Constants and macros for entire LCD_WF51 register
 */
/*@{*/
#define HW_LCD_WF51_ADDR(x)      ((x) + 0x53U)

#define HW_LCD_WF51(x)           (*(__IO hw_lcd_wf51_t *) HW_LCD_WF51_ADDR(x))
#define HW_LCD_WF51_RD(x)        (HW_LCD_WF51(x).U)
#define HW_LCD_WF51_WR(x, v)     (HW_LCD_WF51(x).U = (v))
#define HW_LCD_WF51_SET(x, v)    (BME_OR8(HW_LCD_WF51_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF51_CLR(x, v)    (BME_AND8(HW_LCD_WF51_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF51_TOG(x, v)    (BME_XOR8(HW_LCD_WF51_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF51 bitfields
 */

/*!
 * @name Register LCD_WF51, field BPALCD51[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF51_BPALCD51 (0U)          /*!< Bit position for LCD_WF51_BPALCD51. */
#define BM_LCD_WF51_BPALCD51 (0x01U)       /*!< Bit mask for LCD_WF51_BPALCD51. */
#define BS_LCD_WF51_BPALCD51 (1U)          /*!< Bit field size in bits for LCD_WF51_BPALCD51. */

/*! @brief Read current value of the LCD_WF51_BPALCD51 field. */
#define BR_LCD_WF51_BPALCD51(x) (BME_UBFX8(HW_LCD_WF51_ADDR(x), BP_LCD_WF51_BPALCD51, BS_LCD_WF51_BPALCD51))

/*! @brief Format value for bitfield LCD_WF51_BPALCD51. */
#define BF_LCD_WF51_BPALCD51(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF51_BPALCD51) & BM_LCD_WF51_BPALCD51)

/*! @brief Set the BPALCD51 field to a new value. */
#define BW_LCD_WF51_BPALCD51(x, v) (BME_BFI8(HW_LCD_WF51_ADDR(x), ((uint8_t)(v) << BP_LCD_WF51_BPALCD51), BP_LCD_WF51_BPALCD51, 1))
/*@}*/

/*!
 * @name Register LCD_WF51, field BPBLCD51[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF51_BPBLCD51 (1U)          /*!< Bit position for LCD_WF51_BPBLCD51. */
#define BM_LCD_WF51_BPBLCD51 (0x02U)       /*!< Bit mask for LCD_WF51_BPBLCD51. */
#define BS_LCD_WF51_BPBLCD51 (1U)          /*!< Bit field size in bits for LCD_WF51_BPBLCD51. */

/*! @brief Read current value of the LCD_WF51_BPBLCD51 field. */
#define BR_LCD_WF51_BPBLCD51(x) (BME_UBFX8(HW_LCD_WF51_ADDR(x), BP_LCD_WF51_BPBLCD51, BS_LCD_WF51_BPBLCD51))

/*! @brief Format value for bitfield LCD_WF51_BPBLCD51. */
#define BF_LCD_WF51_BPBLCD51(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF51_BPBLCD51) & BM_LCD_WF51_BPBLCD51)

/*! @brief Set the BPBLCD51 field to a new value. */
#define BW_LCD_WF51_BPBLCD51(x, v) (BME_BFI8(HW_LCD_WF51_ADDR(x), ((uint8_t)(v) << BP_LCD_WF51_BPBLCD51), BP_LCD_WF51_BPBLCD51, 1))
/*@}*/

/*!
 * @name Register LCD_WF51, field BPCLCD51[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF51_BPCLCD51 (2U)          /*!< Bit position for LCD_WF51_BPCLCD51. */
#define BM_LCD_WF51_BPCLCD51 (0x04U)       /*!< Bit mask for LCD_WF51_BPCLCD51. */
#define BS_LCD_WF51_BPCLCD51 (1U)          /*!< Bit field size in bits for LCD_WF51_BPCLCD51. */

/*! @brief Read current value of the LCD_WF51_BPCLCD51 field. */
#define BR_LCD_WF51_BPCLCD51(x) (BME_UBFX8(HW_LCD_WF51_ADDR(x), BP_LCD_WF51_BPCLCD51, BS_LCD_WF51_BPCLCD51))

/*! @brief Format value for bitfield LCD_WF51_BPCLCD51. */
#define BF_LCD_WF51_BPCLCD51(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF51_BPCLCD51) & BM_LCD_WF51_BPCLCD51)

/*! @brief Set the BPCLCD51 field to a new value. */
#define BW_LCD_WF51_BPCLCD51(x, v) (BME_BFI8(HW_LCD_WF51_ADDR(x), ((uint8_t)(v) << BP_LCD_WF51_BPCLCD51), BP_LCD_WF51_BPCLCD51, 1))
/*@}*/

/*!
 * @name Register LCD_WF51, field BPDLCD51[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF51_BPDLCD51 (3U)          /*!< Bit position for LCD_WF51_BPDLCD51. */
#define BM_LCD_WF51_BPDLCD51 (0x08U)       /*!< Bit mask for LCD_WF51_BPDLCD51. */
#define BS_LCD_WF51_BPDLCD51 (1U)          /*!< Bit field size in bits for LCD_WF51_BPDLCD51. */

/*! @brief Read current value of the LCD_WF51_BPDLCD51 field. */
#define BR_LCD_WF51_BPDLCD51(x) (BME_UBFX8(HW_LCD_WF51_ADDR(x), BP_LCD_WF51_BPDLCD51, BS_LCD_WF51_BPDLCD51))

/*! @brief Format value for bitfield LCD_WF51_BPDLCD51. */
#define BF_LCD_WF51_BPDLCD51(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF51_BPDLCD51) & BM_LCD_WF51_BPDLCD51)

/*! @brief Set the BPDLCD51 field to a new value. */
#define BW_LCD_WF51_BPDLCD51(x, v) (BME_BFI8(HW_LCD_WF51_ADDR(x), ((uint8_t)(v) << BP_LCD_WF51_BPDLCD51), BP_LCD_WF51_BPDLCD51, 1))
/*@}*/

/*!
 * @name Register LCD_WF51, field BPELCD51[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF51_BPELCD51 (4U)          /*!< Bit position for LCD_WF51_BPELCD51. */
#define BM_LCD_WF51_BPELCD51 (0x10U)       /*!< Bit mask for LCD_WF51_BPELCD51. */
#define BS_LCD_WF51_BPELCD51 (1U)          /*!< Bit field size in bits for LCD_WF51_BPELCD51. */

/*! @brief Read current value of the LCD_WF51_BPELCD51 field. */
#define BR_LCD_WF51_BPELCD51(x) (BME_UBFX8(HW_LCD_WF51_ADDR(x), BP_LCD_WF51_BPELCD51, BS_LCD_WF51_BPELCD51))

/*! @brief Format value for bitfield LCD_WF51_BPELCD51. */
#define BF_LCD_WF51_BPELCD51(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF51_BPELCD51) & BM_LCD_WF51_BPELCD51)

/*! @brief Set the BPELCD51 field to a new value. */
#define BW_LCD_WF51_BPELCD51(x, v) (BME_BFI8(HW_LCD_WF51_ADDR(x), ((uint8_t)(v) << BP_LCD_WF51_BPELCD51), BP_LCD_WF51_BPELCD51, 1))
/*@}*/

/*!
 * @name Register LCD_WF51, field BPFLCD51[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF51_BPFLCD51 (5U)          /*!< Bit position for LCD_WF51_BPFLCD51. */
#define BM_LCD_WF51_BPFLCD51 (0x20U)       /*!< Bit mask for LCD_WF51_BPFLCD51. */
#define BS_LCD_WF51_BPFLCD51 (1U)          /*!< Bit field size in bits for LCD_WF51_BPFLCD51. */

/*! @brief Read current value of the LCD_WF51_BPFLCD51 field. */
#define BR_LCD_WF51_BPFLCD51(x) (BME_UBFX8(HW_LCD_WF51_ADDR(x), BP_LCD_WF51_BPFLCD51, BS_LCD_WF51_BPFLCD51))

/*! @brief Format value for bitfield LCD_WF51_BPFLCD51. */
#define BF_LCD_WF51_BPFLCD51(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF51_BPFLCD51) & BM_LCD_WF51_BPFLCD51)

/*! @brief Set the BPFLCD51 field to a new value. */
#define BW_LCD_WF51_BPFLCD51(x, v) (BME_BFI8(HW_LCD_WF51_ADDR(x), ((uint8_t)(v) << BP_LCD_WF51_BPFLCD51), BP_LCD_WF51_BPFLCD51, 1))
/*@}*/

/*!
 * @name Register LCD_WF51, field BPGLCD51[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF51_BPGLCD51 (6U)          /*!< Bit position for LCD_WF51_BPGLCD51. */
#define BM_LCD_WF51_BPGLCD51 (0x40U)       /*!< Bit mask for LCD_WF51_BPGLCD51. */
#define BS_LCD_WF51_BPGLCD51 (1U)          /*!< Bit field size in bits for LCD_WF51_BPGLCD51. */

/*! @brief Read current value of the LCD_WF51_BPGLCD51 field. */
#define BR_LCD_WF51_BPGLCD51(x) (BME_UBFX8(HW_LCD_WF51_ADDR(x), BP_LCD_WF51_BPGLCD51, BS_LCD_WF51_BPGLCD51))

/*! @brief Format value for bitfield LCD_WF51_BPGLCD51. */
#define BF_LCD_WF51_BPGLCD51(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF51_BPGLCD51) & BM_LCD_WF51_BPGLCD51)

/*! @brief Set the BPGLCD51 field to a new value. */
#define BW_LCD_WF51_BPGLCD51(x, v) (BME_BFI8(HW_LCD_WF51_ADDR(x), ((uint8_t)(v) << BP_LCD_WF51_BPGLCD51), BP_LCD_WF51_BPGLCD51, 1))
/*@}*/

/*!
 * @name Register LCD_WF51, field BPHLCD51[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF51_BPHLCD51 (7U)          /*!< Bit position for LCD_WF51_BPHLCD51. */
#define BM_LCD_WF51_BPHLCD51 (0x80U)       /*!< Bit mask for LCD_WF51_BPHLCD51. */
#define BS_LCD_WF51_BPHLCD51 (1U)          /*!< Bit field size in bits for LCD_WF51_BPHLCD51. */

/*! @brief Read current value of the LCD_WF51_BPHLCD51 field. */
#define BR_LCD_WF51_BPHLCD51(x) (BME_UBFX8(HW_LCD_WF51_ADDR(x), BP_LCD_WF51_BPHLCD51, BS_LCD_WF51_BPHLCD51))

/*! @brief Format value for bitfield LCD_WF51_BPHLCD51. */
#define BF_LCD_WF51_BPHLCD51(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF51_BPHLCD51) & BM_LCD_WF51_BPHLCD51)

/*! @brief Set the BPHLCD51 field to a new value. */
#define BW_LCD_WF51_BPHLCD51(x, v) (BME_BFI8(HW_LCD_WF51_ADDR(x), ((uint8_t)(v) << BP_LCD_WF51_BPHLCD51), BP_LCD_WF51_BPHLCD51, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF52 - LCD Waveform Register 52.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF52 - LCD Waveform Register 52. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf52
{
    uint8_t U;
    struct _hw_lcd_wf52_bitfields
    {
        uint8_t BPALCD52 : 1;          /*!< [0]  */
        uint8_t BPBLCD52 : 1;          /*!< [1]  */
        uint8_t BPCLCD52 : 1;          /*!< [2]  */
        uint8_t BPDLCD52 : 1;          /*!< [3]  */
        uint8_t BPELCD52 : 1;          /*!< [4]  */
        uint8_t BPFLCD52 : 1;          /*!< [5]  */
        uint8_t BPGLCD52 : 1;          /*!< [6]  */
        uint8_t BPHLCD52 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf52_t;

/*!
 * @name Constants and macros for entire LCD_WF52 register
 */
/*@{*/
#define HW_LCD_WF52_ADDR(x)      ((x) + 0x54U)

#define HW_LCD_WF52(x)           (*(__IO hw_lcd_wf52_t *) HW_LCD_WF52_ADDR(x))
#define HW_LCD_WF52_RD(x)        (HW_LCD_WF52(x).U)
#define HW_LCD_WF52_WR(x, v)     (HW_LCD_WF52(x).U = (v))
#define HW_LCD_WF52_SET(x, v)    (BME_OR8(HW_LCD_WF52_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF52_CLR(x, v)    (BME_AND8(HW_LCD_WF52_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF52_TOG(x, v)    (BME_XOR8(HW_LCD_WF52_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF52 bitfields
 */

/*!
 * @name Register LCD_WF52, field BPALCD52[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF52_BPALCD52 (0U)          /*!< Bit position for LCD_WF52_BPALCD52. */
#define BM_LCD_WF52_BPALCD52 (0x01U)       /*!< Bit mask for LCD_WF52_BPALCD52. */
#define BS_LCD_WF52_BPALCD52 (1U)          /*!< Bit field size in bits for LCD_WF52_BPALCD52. */

/*! @brief Read current value of the LCD_WF52_BPALCD52 field. */
#define BR_LCD_WF52_BPALCD52(x) (BME_UBFX8(HW_LCD_WF52_ADDR(x), BP_LCD_WF52_BPALCD52, BS_LCD_WF52_BPALCD52))

/*! @brief Format value for bitfield LCD_WF52_BPALCD52. */
#define BF_LCD_WF52_BPALCD52(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF52_BPALCD52) & BM_LCD_WF52_BPALCD52)

/*! @brief Set the BPALCD52 field to a new value. */
#define BW_LCD_WF52_BPALCD52(x, v) (BME_BFI8(HW_LCD_WF52_ADDR(x), ((uint8_t)(v) << BP_LCD_WF52_BPALCD52), BP_LCD_WF52_BPALCD52, 1))
/*@}*/

/*!
 * @name Register LCD_WF52, field BPBLCD52[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF52_BPBLCD52 (1U)          /*!< Bit position for LCD_WF52_BPBLCD52. */
#define BM_LCD_WF52_BPBLCD52 (0x02U)       /*!< Bit mask for LCD_WF52_BPBLCD52. */
#define BS_LCD_WF52_BPBLCD52 (1U)          /*!< Bit field size in bits for LCD_WF52_BPBLCD52. */

/*! @brief Read current value of the LCD_WF52_BPBLCD52 field. */
#define BR_LCD_WF52_BPBLCD52(x) (BME_UBFX8(HW_LCD_WF52_ADDR(x), BP_LCD_WF52_BPBLCD52, BS_LCD_WF52_BPBLCD52))

/*! @brief Format value for bitfield LCD_WF52_BPBLCD52. */
#define BF_LCD_WF52_BPBLCD52(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF52_BPBLCD52) & BM_LCD_WF52_BPBLCD52)

/*! @brief Set the BPBLCD52 field to a new value. */
#define BW_LCD_WF52_BPBLCD52(x, v) (BME_BFI8(HW_LCD_WF52_ADDR(x), ((uint8_t)(v) << BP_LCD_WF52_BPBLCD52), BP_LCD_WF52_BPBLCD52, 1))
/*@}*/

/*!
 * @name Register LCD_WF52, field BPCLCD52[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF52_BPCLCD52 (2U)          /*!< Bit position for LCD_WF52_BPCLCD52. */
#define BM_LCD_WF52_BPCLCD52 (0x04U)       /*!< Bit mask for LCD_WF52_BPCLCD52. */
#define BS_LCD_WF52_BPCLCD52 (1U)          /*!< Bit field size in bits for LCD_WF52_BPCLCD52. */

/*! @brief Read current value of the LCD_WF52_BPCLCD52 field. */
#define BR_LCD_WF52_BPCLCD52(x) (BME_UBFX8(HW_LCD_WF52_ADDR(x), BP_LCD_WF52_BPCLCD52, BS_LCD_WF52_BPCLCD52))

/*! @brief Format value for bitfield LCD_WF52_BPCLCD52. */
#define BF_LCD_WF52_BPCLCD52(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF52_BPCLCD52) & BM_LCD_WF52_BPCLCD52)

/*! @brief Set the BPCLCD52 field to a new value. */
#define BW_LCD_WF52_BPCLCD52(x, v) (BME_BFI8(HW_LCD_WF52_ADDR(x), ((uint8_t)(v) << BP_LCD_WF52_BPCLCD52), BP_LCD_WF52_BPCLCD52, 1))
/*@}*/

/*!
 * @name Register LCD_WF52, field BPDLCD52[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF52_BPDLCD52 (3U)          /*!< Bit position for LCD_WF52_BPDLCD52. */
#define BM_LCD_WF52_BPDLCD52 (0x08U)       /*!< Bit mask for LCD_WF52_BPDLCD52. */
#define BS_LCD_WF52_BPDLCD52 (1U)          /*!< Bit field size in bits for LCD_WF52_BPDLCD52. */

/*! @brief Read current value of the LCD_WF52_BPDLCD52 field. */
#define BR_LCD_WF52_BPDLCD52(x) (BME_UBFX8(HW_LCD_WF52_ADDR(x), BP_LCD_WF52_BPDLCD52, BS_LCD_WF52_BPDLCD52))

/*! @brief Format value for bitfield LCD_WF52_BPDLCD52. */
#define BF_LCD_WF52_BPDLCD52(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF52_BPDLCD52) & BM_LCD_WF52_BPDLCD52)

/*! @brief Set the BPDLCD52 field to a new value. */
#define BW_LCD_WF52_BPDLCD52(x, v) (BME_BFI8(HW_LCD_WF52_ADDR(x), ((uint8_t)(v) << BP_LCD_WF52_BPDLCD52), BP_LCD_WF52_BPDLCD52, 1))
/*@}*/

/*!
 * @name Register LCD_WF52, field BPELCD52[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF52_BPELCD52 (4U)          /*!< Bit position for LCD_WF52_BPELCD52. */
#define BM_LCD_WF52_BPELCD52 (0x10U)       /*!< Bit mask for LCD_WF52_BPELCD52. */
#define BS_LCD_WF52_BPELCD52 (1U)          /*!< Bit field size in bits for LCD_WF52_BPELCD52. */

/*! @brief Read current value of the LCD_WF52_BPELCD52 field. */
#define BR_LCD_WF52_BPELCD52(x) (BME_UBFX8(HW_LCD_WF52_ADDR(x), BP_LCD_WF52_BPELCD52, BS_LCD_WF52_BPELCD52))

/*! @brief Format value for bitfield LCD_WF52_BPELCD52. */
#define BF_LCD_WF52_BPELCD52(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF52_BPELCD52) & BM_LCD_WF52_BPELCD52)

/*! @brief Set the BPELCD52 field to a new value. */
#define BW_LCD_WF52_BPELCD52(x, v) (BME_BFI8(HW_LCD_WF52_ADDR(x), ((uint8_t)(v) << BP_LCD_WF52_BPELCD52), BP_LCD_WF52_BPELCD52, 1))
/*@}*/

/*!
 * @name Register LCD_WF52, field BPFLCD52[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF52_BPFLCD52 (5U)          /*!< Bit position for LCD_WF52_BPFLCD52. */
#define BM_LCD_WF52_BPFLCD52 (0x20U)       /*!< Bit mask for LCD_WF52_BPFLCD52. */
#define BS_LCD_WF52_BPFLCD52 (1U)          /*!< Bit field size in bits for LCD_WF52_BPFLCD52. */

/*! @brief Read current value of the LCD_WF52_BPFLCD52 field. */
#define BR_LCD_WF52_BPFLCD52(x) (BME_UBFX8(HW_LCD_WF52_ADDR(x), BP_LCD_WF52_BPFLCD52, BS_LCD_WF52_BPFLCD52))

/*! @brief Format value for bitfield LCD_WF52_BPFLCD52. */
#define BF_LCD_WF52_BPFLCD52(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF52_BPFLCD52) & BM_LCD_WF52_BPFLCD52)

/*! @brief Set the BPFLCD52 field to a new value. */
#define BW_LCD_WF52_BPFLCD52(x, v) (BME_BFI8(HW_LCD_WF52_ADDR(x), ((uint8_t)(v) << BP_LCD_WF52_BPFLCD52), BP_LCD_WF52_BPFLCD52, 1))
/*@}*/

/*!
 * @name Register LCD_WF52, field BPGLCD52[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF52_BPGLCD52 (6U)          /*!< Bit position for LCD_WF52_BPGLCD52. */
#define BM_LCD_WF52_BPGLCD52 (0x40U)       /*!< Bit mask for LCD_WF52_BPGLCD52. */
#define BS_LCD_WF52_BPGLCD52 (1U)          /*!< Bit field size in bits for LCD_WF52_BPGLCD52. */

/*! @brief Read current value of the LCD_WF52_BPGLCD52 field. */
#define BR_LCD_WF52_BPGLCD52(x) (BME_UBFX8(HW_LCD_WF52_ADDR(x), BP_LCD_WF52_BPGLCD52, BS_LCD_WF52_BPGLCD52))

/*! @brief Format value for bitfield LCD_WF52_BPGLCD52. */
#define BF_LCD_WF52_BPGLCD52(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF52_BPGLCD52) & BM_LCD_WF52_BPGLCD52)

/*! @brief Set the BPGLCD52 field to a new value. */
#define BW_LCD_WF52_BPGLCD52(x, v) (BME_BFI8(HW_LCD_WF52_ADDR(x), ((uint8_t)(v) << BP_LCD_WF52_BPGLCD52), BP_LCD_WF52_BPGLCD52, 1))
/*@}*/

/*!
 * @name Register LCD_WF52, field BPHLCD52[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF52_BPHLCD52 (7U)          /*!< Bit position for LCD_WF52_BPHLCD52. */
#define BM_LCD_WF52_BPHLCD52 (0x80U)       /*!< Bit mask for LCD_WF52_BPHLCD52. */
#define BS_LCD_WF52_BPHLCD52 (1U)          /*!< Bit field size in bits for LCD_WF52_BPHLCD52. */

/*! @brief Read current value of the LCD_WF52_BPHLCD52 field. */
#define BR_LCD_WF52_BPHLCD52(x) (BME_UBFX8(HW_LCD_WF52_ADDR(x), BP_LCD_WF52_BPHLCD52, BS_LCD_WF52_BPHLCD52))

/*! @brief Format value for bitfield LCD_WF52_BPHLCD52. */
#define BF_LCD_WF52_BPHLCD52(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF52_BPHLCD52) & BM_LCD_WF52_BPHLCD52)

/*! @brief Set the BPHLCD52 field to a new value. */
#define BW_LCD_WF52_BPHLCD52(x, v) (BME_BFI8(HW_LCD_WF52_ADDR(x), ((uint8_t)(v) << BP_LCD_WF52_BPHLCD52), BP_LCD_WF52_BPHLCD52, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF53 - LCD Waveform Register 53.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF53 - LCD Waveform Register 53. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf53
{
    uint8_t U;
    struct _hw_lcd_wf53_bitfields
    {
        uint8_t BPALCD53 : 1;          /*!< [0]  */
        uint8_t BPBLCD53 : 1;          /*!< [1]  */
        uint8_t BPCLCD53 : 1;          /*!< [2]  */
        uint8_t BPDLCD53 : 1;          /*!< [3]  */
        uint8_t BPELCD53 : 1;          /*!< [4]  */
        uint8_t BPFLCD53 : 1;          /*!< [5]  */
        uint8_t BPGLCD53 : 1;          /*!< [6]  */
        uint8_t BPHLCD53 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf53_t;

/*!
 * @name Constants and macros for entire LCD_WF53 register
 */
/*@{*/
#define HW_LCD_WF53_ADDR(x)      ((x) + 0x55U)

#define HW_LCD_WF53(x)           (*(__IO hw_lcd_wf53_t *) HW_LCD_WF53_ADDR(x))
#define HW_LCD_WF53_RD(x)        (HW_LCD_WF53(x).U)
#define HW_LCD_WF53_WR(x, v)     (HW_LCD_WF53(x).U = (v))
#define HW_LCD_WF53_SET(x, v)    (BME_OR8(HW_LCD_WF53_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF53_CLR(x, v)    (BME_AND8(HW_LCD_WF53_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF53_TOG(x, v)    (BME_XOR8(HW_LCD_WF53_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF53 bitfields
 */

/*!
 * @name Register LCD_WF53, field BPALCD53[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF53_BPALCD53 (0U)          /*!< Bit position for LCD_WF53_BPALCD53. */
#define BM_LCD_WF53_BPALCD53 (0x01U)       /*!< Bit mask for LCD_WF53_BPALCD53. */
#define BS_LCD_WF53_BPALCD53 (1U)          /*!< Bit field size in bits for LCD_WF53_BPALCD53. */

/*! @brief Read current value of the LCD_WF53_BPALCD53 field. */
#define BR_LCD_WF53_BPALCD53(x) (BME_UBFX8(HW_LCD_WF53_ADDR(x), BP_LCD_WF53_BPALCD53, BS_LCD_WF53_BPALCD53))

/*! @brief Format value for bitfield LCD_WF53_BPALCD53. */
#define BF_LCD_WF53_BPALCD53(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF53_BPALCD53) & BM_LCD_WF53_BPALCD53)

/*! @brief Set the BPALCD53 field to a new value. */
#define BW_LCD_WF53_BPALCD53(x, v) (BME_BFI8(HW_LCD_WF53_ADDR(x), ((uint8_t)(v) << BP_LCD_WF53_BPALCD53), BP_LCD_WF53_BPALCD53, 1))
/*@}*/

/*!
 * @name Register LCD_WF53, field BPBLCD53[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF53_BPBLCD53 (1U)          /*!< Bit position for LCD_WF53_BPBLCD53. */
#define BM_LCD_WF53_BPBLCD53 (0x02U)       /*!< Bit mask for LCD_WF53_BPBLCD53. */
#define BS_LCD_WF53_BPBLCD53 (1U)          /*!< Bit field size in bits for LCD_WF53_BPBLCD53. */

/*! @brief Read current value of the LCD_WF53_BPBLCD53 field. */
#define BR_LCD_WF53_BPBLCD53(x) (BME_UBFX8(HW_LCD_WF53_ADDR(x), BP_LCD_WF53_BPBLCD53, BS_LCD_WF53_BPBLCD53))

/*! @brief Format value for bitfield LCD_WF53_BPBLCD53. */
#define BF_LCD_WF53_BPBLCD53(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF53_BPBLCD53) & BM_LCD_WF53_BPBLCD53)

/*! @brief Set the BPBLCD53 field to a new value. */
#define BW_LCD_WF53_BPBLCD53(x, v) (BME_BFI8(HW_LCD_WF53_ADDR(x), ((uint8_t)(v) << BP_LCD_WF53_BPBLCD53), BP_LCD_WF53_BPBLCD53, 1))
/*@}*/

/*!
 * @name Register LCD_WF53, field BPCLCD53[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF53_BPCLCD53 (2U)          /*!< Bit position for LCD_WF53_BPCLCD53. */
#define BM_LCD_WF53_BPCLCD53 (0x04U)       /*!< Bit mask for LCD_WF53_BPCLCD53. */
#define BS_LCD_WF53_BPCLCD53 (1U)          /*!< Bit field size in bits for LCD_WF53_BPCLCD53. */

/*! @brief Read current value of the LCD_WF53_BPCLCD53 field. */
#define BR_LCD_WF53_BPCLCD53(x) (BME_UBFX8(HW_LCD_WF53_ADDR(x), BP_LCD_WF53_BPCLCD53, BS_LCD_WF53_BPCLCD53))

/*! @brief Format value for bitfield LCD_WF53_BPCLCD53. */
#define BF_LCD_WF53_BPCLCD53(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF53_BPCLCD53) & BM_LCD_WF53_BPCLCD53)

/*! @brief Set the BPCLCD53 field to a new value. */
#define BW_LCD_WF53_BPCLCD53(x, v) (BME_BFI8(HW_LCD_WF53_ADDR(x), ((uint8_t)(v) << BP_LCD_WF53_BPCLCD53), BP_LCD_WF53_BPCLCD53, 1))
/*@}*/

/*!
 * @name Register LCD_WF53, field BPDLCD53[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF53_BPDLCD53 (3U)          /*!< Bit position for LCD_WF53_BPDLCD53. */
#define BM_LCD_WF53_BPDLCD53 (0x08U)       /*!< Bit mask for LCD_WF53_BPDLCD53. */
#define BS_LCD_WF53_BPDLCD53 (1U)          /*!< Bit field size in bits for LCD_WF53_BPDLCD53. */

/*! @brief Read current value of the LCD_WF53_BPDLCD53 field. */
#define BR_LCD_WF53_BPDLCD53(x) (BME_UBFX8(HW_LCD_WF53_ADDR(x), BP_LCD_WF53_BPDLCD53, BS_LCD_WF53_BPDLCD53))

/*! @brief Format value for bitfield LCD_WF53_BPDLCD53. */
#define BF_LCD_WF53_BPDLCD53(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF53_BPDLCD53) & BM_LCD_WF53_BPDLCD53)

/*! @brief Set the BPDLCD53 field to a new value. */
#define BW_LCD_WF53_BPDLCD53(x, v) (BME_BFI8(HW_LCD_WF53_ADDR(x), ((uint8_t)(v) << BP_LCD_WF53_BPDLCD53), BP_LCD_WF53_BPDLCD53, 1))
/*@}*/

/*!
 * @name Register LCD_WF53, field BPELCD53[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF53_BPELCD53 (4U)          /*!< Bit position for LCD_WF53_BPELCD53. */
#define BM_LCD_WF53_BPELCD53 (0x10U)       /*!< Bit mask for LCD_WF53_BPELCD53. */
#define BS_LCD_WF53_BPELCD53 (1U)          /*!< Bit field size in bits for LCD_WF53_BPELCD53. */

/*! @brief Read current value of the LCD_WF53_BPELCD53 field. */
#define BR_LCD_WF53_BPELCD53(x) (BME_UBFX8(HW_LCD_WF53_ADDR(x), BP_LCD_WF53_BPELCD53, BS_LCD_WF53_BPELCD53))

/*! @brief Format value for bitfield LCD_WF53_BPELCD53. */
#define BF_LCD_WF53_BPELCD53(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF53_BPELCD53) & BM_LCD_WF53_BPELCD53)

/*! @brief Set the BPELCD53 field to a new value. */
#define BW_LCD_WF53_BPELCD53(x, v) (BME_BFI8(HW_LCD_WF53_ADDR(x), ((uint8_t)(v) << BP_LCD_WF53_BPELCD53), BP_LCD_WF53_BPELCD53, 1))
/*@}*/

/*!
 * @name Register LCD_WF53, field BPFLCD53[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF53_BPFLCD53 (5U)          /*!< Bit position for LCD_WF53_BPFLCD53. */
#define BM_LCD_WF53_BPFLCD53 (0x20U)       /*!< Bit mask for LCD_WF53_BPFLCD53. */
#define BS_LCD_WF53_BPFLCD53 (1U)          /*!< Bit field size in bits for LCD_WF53_BPFLCD53. */

/*! @brief Read current value of the LCD_WF53_BPFLCD53 field. */
#define BR_LCD_WF53_BPFLCD53(x) (BME_UBFX8(HW_LCD_WF53_ADDR(x), BP_LCD_WF53_BPFLCD53, BS_LCD_WF53_BPFLCD53))

/*! @brief Format value for bitfield LCD_WF53_BPFLCD53. */
#define BF_LCD_WF53_BPFLCD53(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF53_BPFLCD53) & BM_LCD_WF53_BPFLCD53)

/*! @brief Set the BPFLCD53 field to a new value. */
#define BW_LCD_WF53_BPFLCD53(x, v) (BME_BFI8(HW_LCD_WF53_ADDR(x), ((uint8_t)(v) << BP_LCD_WF53_BPFLCD53), BP_LCD_WF53_BPFLCD53, 1))
/*@}*/

/*!
 * @name Register LCD_WF53, field BPGLCD53[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF53_BPGLCD53 (6U)          /*!< Bit position for LCD_WF53_BPGLCD53. */
#define BM_LCD_WF53_BPGLCD53 (0x40U)       /*!< Bit mask for LCD_WF53_BPGLCD53. */
#define BS_LCD_WF53_BPGLCD53 (1U)          /*!< Bit field size in bits for LCD_WF53_BPGLCD53. */

/*! @brief Read current value of the LCD_WF53_BPGLCD53 field. */
#define BR_LCD_WF53_BPGLCD53(x) (BME_UBFX8(HW_LCD_WF53_ADDR(x), BP_LCD_WF53_BPGLCD53, BS_LCD_WF53_BPGLCD53))

/*! @brief Format value for bitfield LCD_WF53_BPGLCD53. */
#define BF_LCD_WF53_BPGLCD53(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF53_BPGLCD53) & BM_LCD_WF53_BPGLCD53)

/*! @brief Set the BPGLCD53 field to a new value. */
#define BW_LCD_WF53_BPGLCD53(x, v) (BME_BFI8(HW_LCD_WF53_ADDR(x), ((uint8_t)(v) << BP_LCD_WF53_BPGLCD53), BP_LCD_WF53_BPGLCD53, 1))
/*@}*/

/*!
 * @name Register LCD_WF53, field BPHLCD53[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF53_BPHLCD53 (7U)          /*!< Bit position for LCD_WF53_BPHLCD53. */
#define BM_LCD_WF53_BPHLCD53 (0x80U)       /*!< Bit mask for LCD_WF53_BPHLCD53. */
#define BS_LCD_WF53_BPHLCD53 (1U)          /*!< Bit field size in bits for LCD_WF53_BPHLCD53. */

/*! @brief Read current value of the LCD_WF53_BPHLCD53 field. */
#define BR_LCD_WF53_BPHLCD53(x) (BME_UBFX8(HW_LCD_WF53_ADDR(x), BP_LCD_WF53_BPHLCD53, BS_LCD_WF53_BPHLCD53))

/*! @brief Format value for bitfield LCD_WF53_BPHLCD53. */
#define BF_LCD_WF53_BPHLCD53(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF53_BPHLCD53) & BM_LCD_WF53_BPHLCD53)

/*! @brief Set the BPHLCD53 field to a new value. */
#define BW_LCD_WF53_BPHLCD53(x, v) (BME_BFI8(HW_LCD_WF53_ADDR(x), ((uint8_t)(v) << BP_LCD_WF53_BPHLCD53), BP_LCD_WF53_BPHLCD53, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF54 - LCD Waveform Register 54.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF54 - LCD Waveform Register 54. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf54
{
    uint8_t U;
    struct _hw_lcd_wf54_bitfields
    {
        uint8_t BPALCD54 : 1;          /*!< [0]  */
        uint8_t BPBLCD54 : 1;          /*!< [1]  */
        uint8_t BPCLCD54 : 1;          /*!< [2]  */
        uint8_t BPDLCD54 : 1;          /*!< [3]  */
        uint8_t BPELCD54 : 1;          /*!< [4]  */
        uint8_t BPFLCD54 : 1;          /*!< [5]  */
        uint8_t BPGLCD54 : 1;          /*!< [6]  */
        uint8_t BPHLCD54 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf54_t;

/*!
 * @name Constants and macros for entire LCD_WF54 register
 */
/*@{*/
#define HW_LCD_WF54_ADDR(x)      ((x) + 0x56U)

#define HW_LCD_WF54(x)           (*(__IO hw_lcd_wf54_t *) HW_LCD_WF54_ADDR(x))
#define HW_LCD_WF54_RD(x)        (HW_LCD_WF54(x).U)
#define HW_LCD_WF54_WR(x, v)     (HW_LCD_WF54(x).U = (v))
#define HW_LCD_WF54_SET(x, v)    (BME_OR8(HW_LCD_WF54_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF54_CLR(x, v)    (BME_AND8(HW_LCD_WF54_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF54_TOG(x, v)    (BME_XOR8(HW_LCD_WF54_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF54 bitfields
 */

/*!
 * @name Register LCD_WF54, field BPALCD54[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF54_BPALCD54 (0U)          /*!< Bit position for LCD_WF54_BPALCD54. */
#define BM_LCD_WF54_BPALCD54 (0x01U)       /*!< Bit mask for LCD_WF54_BPALCD54. */
#define BS_LCD_WF54_BPALCD54 (1U)          /*!< Bit field size in bits for LCD_WF54_BPALCD54. */

/*! @brief Read current value of the LCD_WF54_BPALCD54 field. */
#define BR_LCD_WF54_BPALCD54(x) (BME_UBFX8(HW_LCD_WF54_ADDR(x), BP_LCD_WF54_BPALCD54, BS_LCD_WF54_BPALCD54))

/*! @brief Format value for bitfield LCD_WF54_BPALCD54. */
#define BF_LCD_WF54_BPALCD54(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF54_BPALCD54) & BM_LCD_WF54_BPALCD54)

/*! @brief Set the BPALCD54 field to a new value. */
#define BW_LCD_WF54_BPALCD54(x, v) (BME_BFI8(HW_LCD_WF54_ADDR(x), ((uint8_t)(v) << BP_LCD_WF54_BPALCD54), BP_LCD_WF54_BPALCD54, 1))
/*@}*/

/*!
 * @name Register LCD_WF54, field BPBLCD54[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF54_BPBLCD54 (1U)          /*!< Bit position for LCD_WF54_BPBLCD54. */
#define BM_LCD_WF54_BPBLCD54 (0x02U)       /*!< Bit mask for LCD_WF54_BPBLCD54. */
#define BS_LCD_WF54_BPBLCD54 (1U)          /*!< Bit field size in bits for LCD_WF54_BPBLCD54. */

/*! @brief Read current value of the LCD_WF54_BPBLCD54 field. */
#define BR_LCD_WF54_BPBLCD54(x) (BME_UBFX8(HW_LCD_WF54_ADDR(x), BP_LCD_WF54_BPBLCD54, BS_LCD_WF54_BPBLCD54))

/*! @brief Format value for bitfield LCD_WF54_BPBLCD54. */
#define BF_LCD_WF54_BPBLCD54(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF54_BPBLCD54) & BM_LCD_WF54_BPBLCD54)

/*! @brief Set the BPBLCD54 field to a new value. */
#define BW_LCD_WF54_BPBLCD54(x, v) (BME_BFI8(HW_LCD_WF54_ADDR(x), ((uint8_t)(v) << BP_LCD_WF54_BPBLCD54), BP_LCD_WF54_BPBLCD54, 1))
/*@}*/

/*!
 * @name Register LCD_WF54, field BPCLCD54[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF54_BPCLCD54 (2U)          /*!< Bit position for LCD_WF54_BPCLCD54. */
#define BM_LCD_WF54_BPCLCD54 (0x04U)       /*!< Bit mask for LCD_WF54_BPCLCD54. */
#define BS_LCD_WF54_BPCLCD54 (1U)          /*!< Bit field size in bits for LCD_WF54_BPCLCD54. */

/*! @brief Read current value of the LCD_WF54_BPCLCD54 field. */
#define BR_LCD_WF54_BPCLCD54(x) (BME_UBFX8(HW_LCD_WF54_ADDR(x), BP_LCD_WF54_BPCLCD54, BS_LCD_WF54_BPCLCD54))

/*! @brief Format value for bitfield LCD_WF54_BPCLCD54. */
#define BF_LCD_WF54_BPCLCD54(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF54_BPCLCD54) & BM_LCD_WF54_BPCLCD54)

/*! @brief Set the BPCLCD54 field to a new value. */
#define BW_LCD_WF54_BPCLCD54(x, v) (BME_BFI8(HW_LCD_WF54_ADDR(x), ((uint8_t)(v) << BP_LCD_WF54_BPCLCD54), BP_LCD_WF54_BPCLCD54, 1))
/*@}*/

/*!
 * @name Register LCD_WF54, field BPDLCD54[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF54_BPDLCD54 (3U)          /*!< Bit position for LCD_WF54_BPDLCD54. */
#define BM_LCD_WF54_BPDLCD54 (0x08U)       /*!< Bit mask for LCD_WF54_BPDLCD54. */
#define BS_LCD_WF54_BPDLCD54 (1U)          /*!< Bit field size in bits for LCD_WF54_BPDLCD54. */

/*! @brief Read current value of the LCD_WF54_BPDLCD54 field. */
#define BR_LCD_WF54_BPDLCD54(x) (BME_UBFX8(HW_LCD_WF54_ADDR(x), BP_LCD_WF54_BPDLCD54, BS_LCD_WF54_BPDLCD54))

/*! @brief Format value for bitfield LCD_WF54_BPDLCD54. */
#define BF_LCD_WF54_BPDLCD54(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF54_BPDLCD54) & BM_LCD_WF54_BPDLCD54)

/*! @brief Set the BPDLCD54 field to a new value. */
#define BW_LCD_WF54_BPDLCD54(x, v) (BME_BFI8(HW_LCD_WF54_ADDR(x), ((uint8_t)(v) << BP_LCD_WF54_BPDLCD54), BP_LCD_WF54_BPDLCD54, 1))
/*@}*/

/*!
 * @name Register LCD_WF54, field BPELCD54[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF54_BPELCD54 (4U)          /*!< Bit position for LCD_WF54_BPELCD54. */
#define BM_LCD_WF54_BPELCD54 (0x10U)       /*!< Bit mask for LCD_WF54_BPELCD54. */
#define BS_LCD_WF54_BPELCD54 (1U)          /*!< Bit field size in bits for LCD_WF54_BPELCD54. */

/*! @brief Read current value of the LCD_WF54_BPELCD54 field. */
#define BR_LCD_WF54_BPELCD54(x) (BME_UBFX8(HW_LCD_WF54_ADDR(x), BP_LCD_WF54_BPELCD54, BS_LCD_WF54_BPELCD54))

/*! @brief Format value for bitfield LCD_WF54_BPELCD54. */
#define BF_LCD_WF54_BPELCD54(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF54_BPELCD54) & BM_LCD_WF54_BPELCD54)

/*! @brief Set the BPELCD54 field to a new value. */
#define BW_LCD_WF54_BPELCD54(x, v) (BME_BFI8(HW_LCD_WF54_ADDR(x), ((uint8_t)(v) << BP_LCD_WF54_BPELCD54), BP_LCD_WF54_BPELCD54, 1))
/*@}*/

/*!
 * @name Register LCD_WF54, field BPFLCD54[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF54_BPFLCD54 (5U)          /*!< Bit position for LCD_WF54_BPFLCD54. */
#define BM_LCD_WF54_BPFLCD54 (0x20U)       /*!< Bit mask for LCD_WF54_BPFLCD54. */
#define BS_LCD_WF54_BPFLCD54 (1U)          /*!< Bit field size in bits for LCD_WF54_BPFLCD54. */

/*! @brief Read current value of the LCD_WF54_BPFLCD54 field. */
#define BR_LCD_WF54_BPFLCD54(x) (BME_UBFX8(HW_LCD_WF54_ADDR(x), BP_LCD_WF54_BPFLCD54, BS_LCD_WF54_BPFLCD54))

/*! @brief Format value for bitfield LCD_WF54_BPFLCD54. */
#define BF_LCD_WF54_BPFLCD54(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF54_BPFLCD54) & BM_LCD_WF54_BPFLCD54)

/*! @brief Set the BPFLCD54 field to a new value. */
#define BW_LCD_WF54_BPFLCD54(x, v) (BME_BFI8(HW_LCD_WF54_ADDR(x), ((uint8_t)(v) << BP_LCD_WF54_BPFLCD54), BP_LCD_WF54_BPFLCD54, 1))
/*@}*/

/*!
 * @name Register LCD_WF54, field BPGLCD54[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF54_BPGLCD54 (6U)          /*!< Bit position for LCD_WF54_BPGLCD54. */
#define BM_LCD_WF54_BPGLCD54 (0x40U)       /*!< Bit mask for LCD_WF54_BPGLCD54. */
#define BS_LCD_WF54_BPGLCD54 (1U)          /*!< Bit field size in bits for LCD_WF54_BPGLCD54. */

/*! @brief Read current value of the LCD_WF54_BPGLCD54 field. */
#define BR_LCD_WF54_BPGLCD54(x) (BME_UBFX8(HW_LCD_WF54_ADDR(x), BP_LCD_WF54_BPGLCD54, BS_LCD_WF54_BPGLCD54))

/*! @brief Format value for bitfield LCD_WF54_BPGLCD54. */
#define BF_LCD_WF54_BPGLCD54(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF54_BPGLCD54) & BM_LCD_WF54_BPGLCD54)

/*! @brief Set the BPGLCD54 field to a new value. */
#define BW_LCD_WF54_BPGLCD54(x, v) (BME_BFI8(HW_LCD_WF54_ADDR(x), ((uint8_t)(v) << BP_LCD_WF54_BPGLCD54), BP_LCD_WF54_BPGLCD54, 1))
/*@}*/

/*!
 * @name Register LCD_WF54, field BPHLCD54[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF54_BPHLCD54 (7U)          /*!< Bit position for LCD_WF54_BPHLCD54. */
#define BM_LCD_WF54_BPHLCD54 (0x80U)       /*!< Bit mask for LCD_WF54_BPHLCD54. */
#define BS_LCD_WF54_BPHLCD54 (1U)          /*!< Bit field size in bits for LCD_WF54_BPHLCD54. */

/*! @brief Read current value of the LCD_WF54_BPHLCD54 field. */
#define BR_LCD_WF54_BPHLCD54(x) (BME_UBFX8(HW_LCD_WF54_ADDR(x), BP_LCD_WF54_BPHLCD54, BS_LCD_WF54_BPHLCD54))

/*! @brief Format value for bitfield LCD_WF54_BPHLCD54. */
#define BF_LCD_WF54_BPHLCD54(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF54_BPHLCD54) & BM_LCD_WF54_BPHLCD54)

/*! @brief Set the BPHLCD54 field to a new value. */
#define BW_LCD_WF54_BPHLCD54(x, v) (BME_BFI8(HW_LCD_WF54_ADDR(x), ((uint8_t)(v) << BP_LCD_WF54_BPHLCD54), BP_LCD_WF54_BPHLCD54, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF55 - LCD Waveform Register 55.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF55 - LCD Waveform Register 55. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf55
{
    uint8_t U;
    struct _hw_lcd_wf55_bitfields
    {
        uint8_t BPALCD55 : 1;          /*!< [0]  */
        uint8_t BPBLCD55 : 1;          /*!< [1]  */
        uint8_t BPCLCD55 : 1;          /*!< [2]  */
        uint8_t BPDLCD55 : 1;          /*!< [3]  */
        uint8_t BPELCD55 : 1;          /*!< [4]  */
        uint8_t BPFLCD55 : 1;          /*!< [5]  */
        uint8_t BPGLCD55 : 1;          /*!< [6]  */
        uint8_t BPHLCD55 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf55_t;

/*!
 * @name Constants and macros for entire LCD_WF55 register
 */
/*@{*/
#define HW_LCD_WF55_ADDR(x)      ((x) + 0x57U)

#define HW_LCD_WF55(x)           (*(__IO hw_lcd_wf55_t *) HW_LCD_WF55_ADDR(x))
#define HW_LCD_WF55_RD(x)        (HW_LCD_WF55(x).U)
#define HW_LCD_WF55_WR(x, v)     (HW_LCD_WF55(x).U = (v))
#define HW_LCD_WF55_SET(x, v)    (BME_OR8(HW_LCD_WF55_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF55_CLR(x, v)    (BME_AND8(HW_LCD_WF55_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF55_TOG(x, v)    (BME_XOR8(HW_LCD_WF55_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF55 bitfields
 */

/*!
 * @name Register LCD_WF55, field BPALCD55[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF55_BPALCD55 (0U)          /*!< Bit position for LCD_WF55_BPALCD55. */
#define BM_LCD_WF55_BPALCD55 (0x01U)       /*!< Bit mask for LCD_WF55_BPALCD55. */
#define BS_LCD_WF55_BPALCD55 (1U)          /*!< Bit field size in bits for LCD_WF55_BPALCD55. */

/*! @brief Read current value of the LCD_WF55_BPALCD55 field. */
#define BR_LCD_WF55_BPALCD55(x) (BME_UBFX8(HW_LCD_WF55_ADDR(x), BP_LCD_WF55_BPALCD55, BS_LCD_WF55_BPALCD55))

/*! @brief Format value for bitfield LCD_WF55_BPALCD55. */
#define BF_LCD_WF55_BPALCD55(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF55_BPALCD55) & BM_LCD_WF55_BPALCD55)

/*! @brief Set the BPALCD55 field to a new value. */
#define BW_LCD_WF55_BPALCD55(x, v) (BME_BFI8(HW_LCD_WF55_ADDR(x), ((uint8_t)(v) << BP_LCD_WF55_BPALCD55), BP_LCD_WF55_BPALCD55, 1))
/*@}*/

/*!
 * @name Register LCD_WF55, field BPBLCD55[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF55_BPBLCD55 (1U)          /*!< Bit position for LCD_WF55_BPBLCD55. */
#define BM_LCD_WF55_BPBLCD55 (0x02U)       /*!< Bit mask for LCD_WF55_BPBLCD55. */
#define BS_LCD_WF55_BPBLCD55 (1U)          /*!< Bit field size in bits for LCD_WF55_BPBLCD55. */

/*! @brief Read current value of the LCD_WF55_BPBLCD55 field. */
#define BR_LCD_WF55_BPBLCD55(x) (BME_UBFX8(HW_LCD_WF55_ADDR(x), BP_LCD_WF55_BPBLCD55, BS_LCD_WF55_BPBLCD55))

/*! @brief Format value for bitfield LCD_WF55_BPBLCD55. */
#define BF_LCD_WF55_BPBLCD55(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF55_BPBLCD55) & BM_LCD_WF55_BPBLCD55)

/*! @brief Set the BPBLCD55 field to a new value. */
#define BW_LCD_WF55_BPBLCD55(x, v) (BME_BFI8(HW_LCD_WF55_ADDR(x), ((uint8_t)(v) << BP_LCD_WF55_BPBLCD55), BP_LCD_WF55_BPBLCD55, 1))
/*@}*/

/*!
 * @name Register LCD_WF55, field BPCLCD55[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF55_BPCLCD55 (2U)          /*!< Bit position for LCD_WF55_BPCLCD55. */
#define BM_LCD_WF55_BPCLCD55 (0x04U)       /*!< Bit mask for LCD_WF55_BPCLCD55. */
#define BS_LCD_WF55_BPCLCD55 (1U)          /*!< Bit field size in bits for LCD_WF55_BPCLCD55. */

/*! @brief Read current value of the LCD_WF55_BPCLCD55 field. */
#define BR_LCD_WF55_BPCLCD55(x) (BME_UBFX8(HW_LCD_WF55_ADDR(x), BP_LCD_WF55_BPCLCD55, BS_LCD_WF55_BPCLCD55))

/*! @brief Format value for bitfield LCD_WF55_BPCLCD55. */
#define BF_LCD_WF55_BPCLCD55(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF55_BPCLCD55) & BM_LCD_WF55_BPCLCD55)

/*! @brief Set the BPCLCD55 field to a new value. */
#define BW_LCD_WF55_BPCLCD55(x, v) (BME_BFI8(HW_LCD_WF55_ADDR(x), ((uint8_t)(v) << BP_LCD_WF55_BPCLCD55), BP_LCD_WF55_BPCLCD55, 1))
/*@}*/

/*!
 * @name Register LCD_WF55, field BPDLCD55[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF55_BPDLCD55 (3U)          /*!< Bit position for LCD_WF55_BPDLCD55. */
#define BM_LCD_WF55_BPDLCD55 (0x08U)       /*!< Bit mask for LCD_WF55_BPDLCD55. */
#define BS_LCD_WF55_BPDLCD55 (1U)          /*!< Bit field size in bits for LCD_WF55_BPDLCD55. */

/*! @brief Read current value of the LCD_WF55_BPDLCD55 field. */
#define BR_LCD_WF55_BPDLCD55(x) (BME_UBFX8(HW_LCD_WF55_ADDR(x), BP_LCD_WF55_BPDLCD55, BS_LCD_WF55_BPDLCD55))

/*! @brief Format value for bitfield LCD_WF55_BPDLCD55. */
#define BF_LCD_WF55_BPDLCD55(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF55_BPDLCD55) & BM_LCD_WF55_BPDLCD55)

/*! @brief Set the BPDLCD55 field to a new value. */
#define BW_LCD_WF55_BPDLCD55(x, v) (BME_BFI8(HW_LCD_WF55_ADDR(x), ((uint8_t)(v) << BP_LCD_WF55_BPDLCD55), BP_LCD_WF55_BPDLCD55, 1))
/*@}*/

/*!
 * @name Register LCD_WF55, field BPELCD55[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF55_BPELCD55 (4U)          /*!< Bit position for LCD_WF55_BPELCD55. */
#define BM_LCD_WF55_BPELCD55 (0x10U)       /*!< Bit mask for LCD_WF55_BPELCD55. */
#define BS_LCD_WF55_BPELCD55 (1U)          /*!< Bit field size in bits for LCD_WF55_BPELCD55. */

/*! @brief Read current value of the LCD_WF55_BPELCD55 field. */
#define BR_LCD_WF55_BPELCD55(x) (BME_UBFX8(HW_LCD_WF55_ADDR(x), BP_LCD_WF55_BPELCD55, BS_LCD_WF55_BPELCD55))

/*! @brief Format value for bitfield LCD_WF55_BPELCD55. */
#define BF_LCD_WF55_BPELCD55(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF55_BPELCD55) & BM_LCD_WF55_BPELCD55)

/*! @brief Set the BPELCD55 field to a new value. */
#define BW_LCD_WF55_BPELCD55(x, v) (BME_BFI8(HW_LCD_WF55_ADDR(x), ((uint8_t)(v) << BP_LCD_WF55_BPELCD55), BP_LCD_WF55_BPELCD55, 1))
/*@}*/

/*!
 * @name Register LCD_WF55, field BPFLCD55[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF55_BPFLCD55 (5U)          /*!< Bit position for LCD_WF55_BPFLCD55. */
#define BM_LCD_WF55_BPFLCD55 (0x20U)       /*!< Bit mask for LCD_WF55_BPFLCD55. */
#define BS_LCD_WF55_BPFLCD55 (1U)          /*!< Bit field size in bits for LCD_WF55_BPFLCD55. */

/*! @brief Read current value of the LCD_WF55_BPFLCD55 field. */
#define BR_LCD_WF55_BPFLCD55(x) (BME_UBFX8(HW_LCD_WF55_ADDR(x), BP_LCD_WF55_BPFLCD55, BS_LCD_WF55_BPFLCD55))

/*! @brief Format value for bitfield LCD_WF55_BPFLCD55. */
#define BF_LCD_WF55_BPFLCD55(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF55_BPFLCD55) & BM_LCD_WF55_BPFLCD55)

/*! @brief Set the BPFLCD55 field to a new value. */
#define BW_LCD_WF55_BPFLCD55(x, v) (BME_BFI8(HW_LCD_WF55_ADDR(x), ((uint8_t)(v) << BP_LCD_WF55_BPFLCD55), BP_LCD_WF55_BPFLCD55, 1))
/*@}*/

/*!
 * @name Register LCD_WF55, field BPGLCD55[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF55_BPGLCD55 (6U)          /*!< Bit position for LCD_WF55_BPGLCD55. */
#define BM_LCD_WF55_BPGLCD55 (0x40U)       /*!< Bit mask for LCD_WF55_BPGLCD55. */
#define BS_LCD_WF55_BPGLCD55 (1U)          /*!< Bit field size in bits for LCD_WF55_BPGLCD55. */

/*! @brief Read current value of the LCD_WF55_BPGLCD55 field. */
#define BR_LCD_WF55_BPGLCD55(x) (BME_UBFX8(HW_LCD_WF55_ADDR(x), BP_LCD_WF55_BPGLCD55, BS_LCD_WF55_BPGLCD55))

/*! @brief Format value for bitfield LCD_WF55_BPGLCD55. */
#define BF_LCD_WF55_BPGLCD55(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF55_BPGLCD55) & BM_LCD_WF55_BPGLCD55)

/*! @brief Set the BPGLCD55 field to a new value. */
#define BW_LCD_WF55_BPGLCD55(x, v) (BME_BFI8(HW_LCD_WF55_ADDR(x), ((uint8_t)(v) << BP_LCD_WF55_BPGLCD55), BP_LCD_WF55_BPGLCD55, 1))
/*@}*/

/*!
 * @name Register LCD_WF55, field BPHLCD55[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF55_BPHLCD55 (7U)          /*!< Bit position for LCD_WF55_BPHLCD55. */
#define BM_LCD_WF55_BPHLCD55 (0x80U)       /*!< Bit mask for LCD_WF55_BPHLCD55. */
#define BS_LCD_WF55_BPHLCD55 (1U)          /*!< Bit field size in bits for LCD_WF55_BPHLCD55. */

/*! @brief Read current value of the LCD_WF55_BPHLCD55 field. */
#define BR_LCD_WF55_BPHLCD55(x) (BME_UBFX8(HW_LCD_WF55_ADDR(x), BP_LCD_WF55_BPHLCD55, BS_LCD_WF55_BPHLCD55))

/*! @brief Format value for bitfield LCD_WF55_BPHLCD55. */
#define BF_LCD_WF55_BPHLCD55(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF55_BPHLCD55) & BM_LCD_WF55_BPHLCD55)

/*! @brief Set the BPHLCD55 field to a new value. */
#define BW_LCD_WF55_BPHLCD55(x, v) (BME_BFI8(HW_LCD_WF55_ADDR(x), ((uint8_t)(v) << BP_LCD_WF55_BPHLCD55), BP_LCD_WF55_BPHLCD55, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF56 - LCD Waveform Register 56.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF56 - LCD Waveform Register 56. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf56
{
    uint8_t U;
    struct _hw_lcd_wf56_bitfields
    {
        uint8_t BPALCD56 : 1;          /*!< [0]  */
        uint8_t BPBLCD56 : 1;          /*!< [1]  */
        uint8_t BPCLCD56 : 1;          /*!< [2]  */
        uint8_t BPDLCD56 : 1;          /*!< [3]  */
        uint8_t BPELCD56 : 1;          /*!< [4]  */
        uint8_t BPFLCD56 : 1;          /*!< [5]  */
        uint8_t BPGLCD56 : 1;          /*!< [6]  */
        uint8_t BPHLCD56 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf56_t;

/*!
 * @name Constants and macros for entire LCD_WF56 register
 */
/*@{*/
#define HW_LCD_WF56_ADDR(x)      ((x) + 0x58U)

#define HW_LCD_WF56(x)           (*(__IO hw_lcd_wf56_t *) HW_LCD_WF56_ADDR(x))
#define HW_LCD_WF56_RD(x)        (HW_LCD_WF56(x).U)
#define HW_LCD_WF56_WR(x, v)     (HW_LCD_WF56(x).U = (v))
#define HW_LCD_WF56_SET(x, v)    (BME_OR8(HW_LCD_WF56_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF56_CLR(x, v)    (BME_AND8(HW_LCD_WF56_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF56_TOG(x, v)    (BME_XOR8(HW_LCD_WF56_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF56 bitfields
 */

/*!
 * @name Register LCD_WF56, field BPALCD56[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF56_BPALCD56 (0U)          /*!< Bit position for LCD_WF56_BPALCD56. */
#define BM_LCD_WF56_BPALCD56 (0x01U)       /*!< Bit mask for LCD_WF56_BPALCD56. */
#define BS_LCD_WF56_BPALCD56 (1U)          /*!< Bit field size in bits for LCD_WF56_BPALCD56. */

/*! @brief Read current value of the LCD_WF56_BPALCD56 field. */
#define BR_LCD_WF56_BPALCD56(x) (BME_UBFX8(HW_LCD_WF56_ADDR(x), BP_LCD_WF56_BPALCD56, BS_LCD_WF56_BPALCD56))

/*! @brief Format value for bitfield LCD_WF56_BPALCD56. */
#define BF_LCD_WF56_BPALCD56(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF56_BPALCD56) & BM_LCD_WF56_BPALCD56)

/*! @brief Set the BPALCD56 field to a new value. */
#define BW_LCD_WF56_BPALCD56(x, v) (BME_BFI8(HW_LCD_WF56_ADDR(x), ((uint8_t)(v) << BP_LCD_WF56_BPALCD56), BP_LCD_WF56_BPALCD56, 1))
/*@}*/

/*!
 * @name Register LCD_WF56, field BPBLCD56[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF56_BPBLCD56 (1U)          /*!< Bit position for LCD_WF56_BPBLCD56. */
#define BM_LCD_WF56_BPBLCD56 (0x02U)       /*!< Bit mask for LCD_WF56_BPBLCD56. */
#define BS_LCD_WF56_BPBLCD56 (1U)          /*!< Bit field size in bits for LCD_WF56_BPBLCD56. */

/*! @brief Read current value of the LCD_WF56_BPBLCD56 field. */
#define BR_LCD_WF56_BPBLCD56(x) (BME_UBFX8(HW_LCD_WF56_ADDR(x), BP_LCD_WF56_BPBLCD56, BS_LCD_WF56_BPBLCD56))

/*! @brief Format value for bitfield LCD_WF56_BPBLCD56. */
#define BF_LCD_WF56_BPBLCD56(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF56_BPBLCD56) & BM_LCD_WF56_BPBLCD56)

/*! @brief Set the BPBLCD56 field to a new value. */
#define BW_LCD_WF56_BPBLCD56(x, v) (BME_BFI8(HW_LCD_WF56_ADDR(x), ((uint8_t)(v) << BP_LCD_WF56_BPBLCD56), BP_LCD_WF56_BPBLCD56, 1))
/*@}*/

/*!
 * @name Register LCD_WF56, field BPCLCD56[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF56_BPCLCD56 (2U)          /*!< Bit position for LCD_WF56_BPCLCD56. */
#define BM_LCD_WF56_BPCLCD56 (0x04U)       /*!< Bit mask for LCD_WF56_BPCLCD56. */
#define BS_LCD_WF56_BPCLCD56 (1U)          /*!< Bit field size in bits for LCD_WF56_BPCLCD56. */

/*! @brief Read current value of the LCD_WF56_BPCLCD56 field. */
#define BR_LCD_WF56_BPCLCD56(x) (BME_UBFX8(HW_LCD_WF56_ADDR(x), BP_LCD_WF56_BPCLCD56, BS_LCD_WF56_BPCLCD56))

/*! @brief Format value for bitfield LCD_WF56_BPCLCD56. */
#define BF_LCD_WF56_BPCLCD56(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF56_BPCLCD56) & BM_LCD_WF56_BPCLCD56)

/*! @brief Set the BPCLCD56 field to a new value. */
#define BW_LCD_WF56_BPCLCD56(x, v) (BME_BFI8(HW_LCD_WF56_ADDR(x), ((uint8_t)(v) << BP_LCD_WF56_BPCLCD56), BP_LCD_WF56_BPCLCD56, 1))
/*@}*/

/*!
 * @name Register LCD_WF56, field BPDLCD56[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF56_BPDLCD56 (3U)          /*!< Bit position for LCD_WF56_BPDLCD56. */
#define BM_LCD_WF56_BPDLCD56 (0x08U)       /*!< Bit mask for LCD_WF56_BPDLCD56. */
#define BS_LCD_WF56_BPDLCD56 (1U)          /*!< Bit field size in bits for LCD_WF56_BPDLCD56. */

/*! @brief Read current value of the LCD_WF56_BPDLCD56 field. */
#define BR_LCD_WF56_BPDLCD56(x) (BME_UBFX8(HW_LCD_WF56_ADDR(x), BP_LCD_WF56_BPDLCD56, BS_LCD_WF56_BPDLCD56))

/*! @brief Format value for bitfield LCD_WF56_BPDLCD56. */
#define BF_LCD_WF56_BPDLCD56(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF56_BPDLCD56) & BM_LCD_WF56_BPDLCD56)

/*! @brief Set the BPDLCD56 field to a new value. */
#define BW_LCD_WF56_BPDLCD56(x, v) (BME_BFI8(HW_LCD_WF56_ADDR(x), ((uint8_t)(v) << BP_LCD_WF56_BPDLCD56), BP_LCD_WF56_BPDLCD56, 1))
/*@}*/

/*!
 * @name Register LCD_WF56, field BPELCD56[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF56_BPELCD56 (4U)          /*!< Bit position for LCD_WF56_BPELCD56. */
#define BM_LCD_WF56_BPELCD56 (0x10U)       /*!< Bit mask for LCD_WF56_BPELCD56. */
#define BS_LCD_WF56_BPELCD56 (1U)          /*!< Bit field size in bits for LCD_WF56_BPELCD56. */

/*! @brief Read current value of the LCD_WF56_BPELCD56 field. */
#define BR_LCD_WF56_BPELCD56(x) (BME_UBFX8(HW_LCD_WF56_ADDR(x), BP_LCD_WF56_BPELCD56, BS_LCD_WF56_BPELCD56))

/*! @brief Format value for bitfield LCD_WF56_BPELCD56. */
#define BF_LCD_WF56_BPELCD56(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF56_BPELCD56) & BM_LCD_WF56_BPELCD56)

/*! @brief Set the BPELCD56 field to a new value. */
#define BW_LCD_WF56_BPELCD56(x, v) (BME_BFI8(HW_LCD_WF56_ADDR(x), ((uint8_t)(v) << BP_LCD_WF56_BPELCD56), BP_LCD_WF56_BPELCD56, 1))
/*@}*/

/*!
 * @name Register LCD_WF56, field BPFLCD56[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF56_BPFLCD56 (5U)          /*!< Bit position for LCD_WF56_BPFLCD56. */
#define BM_LCD_WF56_BPFLCD56 (0x20U)       /*!< Bit mask for LCD_WF56_BPFLCD56. */
#define BS_LCD_WF56_BPFLCD56 (1U)          /*!< Bit field size in bits for LCD_WF56_BPFLCD56. */

/*! @brief Read current value of the LCD_WF56_BPFLCD56 field. */
#define BR_LCD_WF56_BPFLCD56(x) (BME_UBFX8(HW_LCD_WF56_ADDR(x), BP_LCD_WF56_BPFLCD56, BS_LCD_WF56_BPFLCD56))

/*! @brief Format value for bitfield LCD_WF56_BPFLCD56. */
#define BF_LCD_WF56_BPFLCD56(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF56_BPFLCD56) & BM_LCD_WF56_BPFLCD56)

/*! @brief Set the BPFLCD56 field to a new value. */
#define BW_LCD_WF56_BPFLCD56(x, v) (BME_BFI8(HW_LCD_WF56_ADDR(x), ((uint8_t)(v) << BP_LCD_WF56_BPFLCD56), BP_LCD_WF56_BPFLCD56, 1))
/*@}*/

/*!
 * @name Register LCD_WF56, field BPGLCD56[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF56_BPGLCD56 (6U)          /*!< Bit position for LCD_WF56_BPGLCD56. */
#define BM_LCD_WF56_BPGLCD56 (0x40U)       /*!< Bit mask for LCD_WF56_BPGLCD56. */
#define BS_LCD_WF56_BPGLCD56 (1U)          /*!< Bit field size in bits for LCD_WF56_BPGLCD56. */

/*! @brief Read current value of the LCD_WF56_BPGLCD56 field. */
#define BR_LCD_WF56_BPGLCD56(x) (BME_UBFX8(HW_LCD_WF56_ADDR(x), BP_LCD_WF56_BPGLCD56, BS_LCD_WF56_BPGLCD56))

/*! @brief Format value for bitfield LCD_WF56_BPGLCD56. */
#define BF_LCD_WF56_BPGLCD56(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF56_BPGLCD56) & BM_LCD_WF56_BPGLCD56)

/*! @brief Set the BPGLCD56 field to a new value. */
#define BW_LCD_WF56_BPGLCD56(x, v) (BME_BFI8(HW_LCD_WF56_ADDR(x), ((uint8_t)(v) << BP_LCD_WF56_BPGLCD56), BP_LCD_WF56_BPGLCD56, 1))
/*@}*/

/*!
 * @name Register LCD_WF56, field BPHLCD56[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF56_BPHLCD56 (7U)          /*!< Bit position for LCD_WF56_BPHLCD56. */
#define BM_LCD_WF56_BPHLCD56 (0x80U)       /*!< Bit mask for LCD_WF56_BPHLCD56. */
#define BS_LCD_WF56_BPHLCD56 (1U)          /*!< Bit field size in bits for LCD_WF56_BPHLCD56. */

/*! @brief Read current value of the LCD_WF56_BPHLCD56 field. */
#define BR_LCD_WF56_BPHLCD56(x) (BME_UBFX8(HW_LCD_WF56_ADDR(x), BP_LCD_WF56_BPHLCD56, BS_LCD_WF56_BPHLCD56))

/*! @brief Format value for bitfield LCD_WF56_BPHLCD56. */
#define BF_LCD_WF56_BPHLCD56(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF56_BPHLCD56) & BM_LCD_WF56_BPHLCD56)

/*! @brief Set the BPHLCD56 field to a new value. */
#define BW_LCD_WF56_BPHLCD56(x, v) (BME_BFI8(HW_LCD_WF56_ADDR(x), ((uint8_t)(v) << BP_LCD_WF56_BPHLCD56), BP_LCD_WF56_BPHLCD56, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF57 - LCD Waveform Register 57.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF57 - LCD Waveform Register 57. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf57
{
    uint8_t U;
    struct _hw_lcd_wf57_bitfields
    {
        uint8_t BPALCD57 : 1;          /*!< [0]  */
        uint8_t BPBLCD57 : 1;          /*!< [1]  */
        uint8_t BPCLCD57 : 1;          /*!< [2]  */
        uint8_t BPDLCD57 : 1;          /*!< [3]  */
        uint8_t BPELCD57 : 1;          /*!< [4]  */
        uint8_t BPFLCD57 : 1;          /*!< [5]  */
        uint8_t BPGLCD57 : 1;          /*!< [6]  */
        uint8_t BPHLCD57 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf57_t;

/*!
 * @name Constants and macros for entire LCD_WF57 register
 */
/*@{*/
#define HW_LCD_WF57_ADDR(x)      ((x) + 0x59U)

#define HW_LCD_WF57(x)           (*(__IO hw_lcd_wf57_t *) HW_LCD_WF57_ADDR(x))
#define HW_LCD_WF57_RD(x)        (HW_LCD_WF57(x).U)
#define HW_LCD_WF57_WR(x, v)     (HW_LCD_WF57(x).U = (v))
#define HW_LCD_WF57_SET(x, v)    (BME_OR8(HW_LCD_WF57_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF57_CLR(x, v)    (BME_AND8(HW_LCD_WF57_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF57_TOG(x, v)    (BME_XOR8(HW_LCD_WF57_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF57 bitfields
 */

/*!
 * @name Register LCD_WF57, field BPALCD57[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF57_BPALCD57 (0U)          /*!< Bit position for LCD_WF57_BPALCD57. */
#define BM_LCD_WF57_BPALCD57 (0x01U)       /*!< Bit mask for LCD_WF57_BPALCD57. */
#define BS_LCD_WF57_BPALCD57 (1U)          /*!< Bit field size in bits for LCD_WF57_BPALCD57. */

/*! @brief Read current value of the LCD_WF57_BPALCD57 field. */
#define BR_LCD_WF57_BPALCD57(x) (BME_UBFX8(HW_LCD_WF57_ADDR(x), BP_LCD_WF57_BPALCD57, BS_LCD_WF57_BPALCD57))

/*! @brief Format value for bitfield LCD_WF57_BPALCD57. */
#define BF_LCD_WF57_BPALCD57(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF57_BPALCD57) & BM_LCD_WF57_BPALCD57)

/*! @brief Set the BPALCD57 field to a new value. */
#define BW_LCD_WF57_BPALCD57(x, v) (BME_BFI8(HW_LCD_WF57_ADDR(x), ((uint8_t)(v) << BP_LCD_WF57_BPALCD57), BP_LCD_WF57_BPALCD57, 1))
/*@}*/

/*!
 * @name Register LCD_WF57, field BPBLCD57[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF57_BPBLCD57 (1U)          /*!< Bit position for LCD_WF57_BPBLCD57. */
#define BM_LCD_WF57_BPBLCD57 (0x02U)       /*!< Bit mask for LCD_WF57_BPBLCD57. */
#define BS_LCD_WF57_BPBLCD57 (1U)          /*!< Bit field size in bits for LCD_WF57_BPBLCD57. */

/*! @brief Read current value of the LCD_WF57_BPBLCD57 field. */
#define BR_LCD_WF57_BPBLCD57(x) (BME_UBFX8(HW_LCD_WF57_ADDR(x), BP_LCD_WF57_BPBLCD57, BS_LCD_WF57_BPBLCD57))

/*! @brief Format value for bitfield LCD_WF57_BPBLCD57. */
#define BF_LCD_WF57_BPBLCD57(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF57_BPBLCD57) & BM_LCD_WF57_BPBLCD57)

/*! @brief Set the BPBLCD57 field to a new value. */
#define BW_LCD_WF57_BPBLCD57(x, v) (BME_BFI8(HW_LCD_WF57_ADDR(x), ((uint8_t)(v) << BP_LCD_WF57_BPBLCD57), BP_LCD_WF57_BPBLCD57, 1))
/*@}*/

/*!
 * @name Register LCD_WF57, field BPCLCD57[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF57_BPCLCD57 (2U)          /*!< Bit position for LCD_WF57_BPCLCD57. */
#define BM_LCD_WF57_BPCLCD57 (0x04U)       /*!< Bit mask for LCD_WF57_BPCLCD57. */
#define BS_LCD_WF57_BPCLCD57 (1U)          /*!< Bit field size in bits for LCD_WF57_BPCLCD57. */

/*! @brief Read current value of the LCD_WF57_BPCLCD57 field. */
#define BR_LCD_WF57_BPCLCD57(x) (BME_UBFX8(HW_LCD_WF57_ADDR(x), BP_LCD_WF57_BPCLCD57, BS_LCD_WF57_BPCLCD57))

/*! @brief Format value for bitfield LCD_WF57_BPCLCD57. */
#define BF_LCD_WF57_BPCLCD57(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF57_BPCLCD57) & BM_LCD_WF57_BPCLCD57)

/*! @brief Set the BPCLCD57 field to a new value. */
#define BW_LCD_WF57_BPCLCD57(x, v) (BME_BFI8(HW_LCD_WF57_ADDR(x), ((uint8_t)(v) << BP_LCD_WF57_BPCLCD57), BP_LCD_WF57_BPCLCD57, 1))
/*@}*/

/*!
 * @name Register LCD_WF57, field BPDLCD57[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF57_BPDLCD57 (3U)          /*!< Bit position for LCD_WF57_BPDLCD57. */
#define BM_LCD_WF57_BPDLCD57 (0x08U)       /*!< Bit mask for LCD_WF57_BPDLCD57. */
#define BS_LCD_WF57_BPDLCD57 (1U)          /*!< Bit field size in bits for LCD_WF57_BPDLCD57. */

/*! @brief Read current value of the LCD_WF57_BPDLCD57 field. */
#define BR_LCD_WF57_BPDLCD57(x) (BME_UBFX8(HW_LCD_WF57_ADDR(x), BP_LCD_WF57_BPDLCD57, BS_LCD_WF57_BPDLCD57))

/*! @brief Format value for bitfield LCD_WF57_BPDLCD57. */
#define BF_LCD_WF57_BPDLCD57(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF57_BPDLCD57) & BM_LCD_WF57_BPDLCD57)

/*! @brief Set the BPDLCD57 field to a new value. */
#define BW_LCD_WF57_BPDLCD57(x, v) (BME_BFI8(HW_LCD_WF57_ADDR(x), ((uint8_t)(v) << BP_LCD_WF57_BPDLCD57), BP_LCD_WF57_BPDLCD57, 1))
/*@}*/

/*!
 * @name Register LCD_WF57, field BPELCD57[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF57_BPELCD57 (4U)          /*!< Bit position for LCD_WF57_BPELCD57. */
#define BM_LCD_WF57_BPELCD57 (0x10U)       /*!< Bit mask for LCD_WF57_BPELCD57. */
#define BS_LCD_WF57_BPELCD57 (1U)          /*!< Bit field size in bits for LCD_WF57_BPELCD57. */

/*! @brief Read current value of the LCD_WF57_BPELCD57 field. */
#define BR_LCD_WF57_BPELCD57(x) (BME_UBFX8(HW_LCD_WF57_ADDR(x), BP_LCD_WF57_BPELCD57, BS_LCD_WF57_BPELCD57))

/*! @brief Format value for bitfield LCD_WF57_BPELCD57. */
#define BF_LCD_WF57_BPELCD57(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF57_BPELCD57) & BM_LCD_WF57_BPELCD57)

/*! @brief Set the BPELCD57 field to a new value. */
#define BW_LCD_WF57_BPELCD57(x, v) (BME_BFI8(HW_LCD_WF57_ADDR(x), ((uint8_t)(v) << BP_LCD_WF57_BPELCD57), BP_LCD_WF57_BPELCD57, 1))
/*@}*/

/*!
 * @name Register LCD_WF57, field BPFLCD57[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF57_BPFLCD57 (5U)          /*!< Bit position for LCD_WF57_BPFLCD57. */
#define BM_LCD_WF57_BPFLCD57 (0x20U)       /*!< Bit mask for LCD_WF57_BPFLCD57. */
#define BS_LCD_WF57_BPFLCD57 (1U)          /*!< Bit field size in bits for LCD_WF57_BPFLCD57. */

/*! @brief Read current value of the LCD_WF57_BPFLCD57 field. */
#define BR_LCD_WF57_BPFLCD57(x) (BME_UBFX8(HW_LCD_WF57_ADDR(x), BP_LCD_WF57_BPFLCD57, BS_LCD_WF57_BPFLCD57))

/*! @brief Format value for bitfield LCD_WF57_BPFLCD57. */
#define BF_LCD_WF57_BPFLCD57(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF57_BPFLCD57) & BM_LCD_WF57_BPFLCD57)

/*! @brief Set the BPFLCD57 field to a new value. */
#define BW_LCD_WF57_BPFLCD57(x, v) (BME_BFI8(HW_LCD_WF57_ADDR(x), ((uint8_t)(v) << BP_LCD_WF57_BPFLCD57), BP_LCD_WF57_BPFLCD57, 1))
/*@}*/

/*!
 * @name Register LCD_WF57, field BPGLCD57[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF57_BPGLCD57 (6U)          /*!< Bit position for LCD_WF57_BPGLCD57. */
#define BM_LCD_WF57_BPGLCD57 (0x40U)       /*!< Bit mask for LCD_WF57_BPGLCD57. */
#define BS_LCD_WF57_BPGLCD57 (1U)          /*!< Bit field size in bits for LCD_WF57_BPGLCD57. */

/*! @brief Read current value of the LCD_WF57_BPGLCD57 field. */
#define BR_LCD_WF57_BPGLCD57(x) (BME_UBFX8(HW_LCD_WF57_ADDR(x), BP_LCD_WF57_BPGLCD57, BS_LCD_WF57_BPGLCD57))

/*! @brief Format value for bitfield LCD_WF57_BPGLCD57. */
#define BF_LCD_WF57_BPGLCD57(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF57_BPGLCD57) & BM_LCD_WF57_BPGLCD57)

/*! @brief Set the BPGLCD57 field to a new value. */
#define BW_LCD_WF57_BPGLCD57(x, v) (BME_BFI8(HW_LCD_WF57_ADDR(x), ((uint8_t)(v) << BP_LCD_WF57_BPGLCD57), BP_LCD_WF57_BPGLCD57, 1))
/*@}*/

/*!
 * @name Register LCD_WF57, field BPHLCD57[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF57_BPHLCD57 (7U)          /*!< Bit position for LCD_WF57_BPHLCD57. */
#define BM_LCD_WF57_BPHLCD57 (0x80U)       /*!< Bit mask for LCD_WF57_BPHLCD57. */
#define BS_LCD_WF57_BPHLCD57 (1U)          /*!< Bit field size in bits for LCD_WF57_BPHLCD57. */

/*! @brief Read current value of the LCD_WF57_BPHLCD57 field. */
#define BR_LCD_WF57_BPHLCD57(x) (BME_UBFX8(HW_LCD_WF57_ADDR(x), BP_LCD_WF57_BPHLCD57, BS_LCD_WF57_BPHLCD57))

/*! @brief Format value for bitfield LCD_WF57_BPHLCD57. */
#define BF_LCD_WF57_BPHLCD57(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF57_BPHLCD57) & BM_LCD_WF57_BPHLCD57)

/*! @brief Set the BPHLCD57 field to a new value. */
#define BW_LCD_WF57_BPHLCD57(x, v) (BME_BFI8(HW_LCD_WF57_ADDR(x), ((uint8_t)(v) << BP_LCD_WF57_BPHLCD57), BP_LCD_WF57_BPHLCD57, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF58 - LCD Waveform Register 58.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF58 - LCD Waveform Register 58. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf58
{
    uint8_t U;
    struct _hw_lcd_wf58_bitfields
    {
        uint8_t BPALCD58 : 1;          /*!< [0]  */
        uint8_t BPBLCD58 : 1;          /*!< [1]  */
        uint8_t BPCLCD58 : 1;          /*!< [2]  */
        uint8_t BPDLCD58 : 1;          /*!< [3]  */
        uint8_t BPELCD58 : 1;          /*!< [4]  */
        uint8_t BPFLCD58 : 1;          /*!< [5]  */
        uint8_t BPGLCD58 : 1;          /*!< [6]  */
        uint8_t BPHLCD58 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf58_t;

/*!
 * @name Constants and macros for entire LCD_WF58 register
 */
/*@{*/
#define HW_LCD_WF58_ADDR(x)      ((x) + 0x5AU)

#define HW_LCD_WF58(x)           (*(__IO hw_lcd_wf58_t *) HW_LCD_WF58_ADDR(x))
#define HW_LCD_WF58_RD(x)        (HW_LCD_WF58(x).U)
#define HW_LCD_WF58_WR(x, v)     (HW_LCD_WF58(x).U = (v))
#define HW_LCD_WF58_SET(x, v)    (BME_OR8(HW_LCD_WF58_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF58_CLR(x, v)    (BME_AND8(HW_LCD_WF58_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF58_TOG(x, v)    (BME_XOR8(HW_LCD_WF58_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF58 bitfields
 */

/*!
 * @name Register LCD_WF58, field BPALCD58[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF58_BPALCD58 (0U)          /*!< Bit position for LCD_WF58_BPALCD58. */
#define BM_LCD_WF58_BPALCD58 (0x01U)       /*!< Bit mask for LCD_WF58_BPALCD58. */
#define BS_LCD_WF58_BPALCD58 (1U)          /*!< Bit field size in bits for LCD_WF58_BPALCD58. */

/*! @brief Read current value of the LCD_WF58_BPALCD58 field. */
#define BR_LCD_WF58_BPALCD58(x) (BME_UBFX8(HW_LCD_WF58_ADDR(x), BP_LCD_WF58_BPALCD58, BS_LCD_WF58_BPALCD58))

/*! @brief Format value for bitfield LCD_WF58_BPALCD58. */
#define BF_LCD_WF58_BPALCD58(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF58_BPALCD58) & BM_LCD_WF58_BPALCD58)

/*! @brief Set the BPALCD58 field to a new value. */
#define BW_LCD_WF58_BPALCD58(x, v) (BME_BFI8(HW_LCD_WF58_ADDR(x), ((uint8_t)(v) << BP_LCD_WF58_BPALCD58), BP_LCD_WF58_BPALCD58, 1))
/*@}*/

/*!
 * @name Register LCD_WF58, field BPBLCD58[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF58_BPBLCD58 (1U)          /*!< Bit position for LCD_WF58_BPBLCD58. */
#define BM_LCD_WF58_BPBLCD58 (0x02U)       /*!< Bit mask for LCD_WF58_BPBLCD58. */
#define BS_LCD_WF58_BPBLCD58 (1U)          /*!< Bit field size in bits for LCD_WF58_BPBLCD58. */

/*! @brief Read current value of the LCD_WF58_BPBLCD58 field. */
#define BR_LCD_WF58_BPBLCD58(x) (BME_UBFX8(HW_LCD_WF58_ADDR(x), BP_LCD_WF58_BPBLCD58, BS_LCD_WF58_BPBLCD58))

/*! @brief Format value for bitfield LCD_WF58_BPBLCD58. */
#define BF_LCD_WF58_BPBLCD58(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF58_BPBLCD58) & BM_LCD_WF58_BPBLCD58)

/*! @brief Set the BPBLCD58 field to a new value. */
#define BW_LCD_WF58_BPBLCD58(x, v) (BME_BFI8(HW_LCD_WF58_ADDR(x), ((uint8_t)(v) << BP_LCD_WF58_BPBLCD58), BP_LCD_WF58_BPBLCD58, 1))
/*@}*/

/*!
 * @name Register LCD_WF58, field BPCLCD58[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF58_BPCLCD58 (2U)          /*!< Bit position for LCD_WF58_BPCLCD58. */
#define BM_LCD_WF58_BPCLCD58 (0x04U)       /*!< Bit mask for LCD_WF58_BPCLCD58. */
#define BS_LCD_WF58_BPCLCD58 (1U)          /*!< Bit field size in bits for LCD_WF58_BPCLCD58. */

/*! @brief Read current value of the LCD_WF58_BPCLCD58 field. */
#define BR_LCD_WF58_BPCLCD58(x) (BME_UBFX8(HW_LCD_WF58_ADDR(x), BP_LCD_WF58_BPCLCD58, BS_LCD_WF58_BPCLCD58))

/*! @brief Format value for bitfield LCD_WF58_BPCLCD58. */
#define BF_LCD_WF58_BPCLCD58(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF58_BPCLCD58) & BM_LCD_WF58_BPCLCD58)

/*! @brief Set the BPCLCD58 field to a new value. */
#define BW_LCD_WF58_BPCLCD58(x, v) (BME_BFI8(HW_LCD_WF58_ADDR(x), ((uint8_t)(v) << BP_LCD_WF58_BPCLCD58), BP_LCD_WF58_BPCLCD58, 1))
/*@}*/

/*!
 * @name Register LCD_WF58, field BPDLCD58[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF58_BPDLCD58 (3U)          /*!< Bit position for LCD_WF58_BPDLCD58. */
#define BM_LCD_WF58_BPDLCD58 (0x08U)       /*!< Bit mask for LCD_WF58_BPDLCD58. */
#define BS_LCD_WF58_BPDLCD58 (1U)          /*!< Bit field size in bits for LCD_WF58_BPDLCD58. */

/*! @brief Read current value of the LCD_WF58_BPDLCD58 field. */
#define BR_LCD_WF58_BPDLCD58(x) (BME_UBFX8(HW_LCD_WF58_ADDR(x), BP_LCD_WF58_BPDLCD58, BS_LCD_WF58_BPDLCD58))

/*! @brief Format value for bitfield LCD_WF58_BPDLCD58. */
#define BF_LCD_WF58_BPDLCD58(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF58_BPDLCD58) & BM_LCD_WF58_BPDLCD58)

/*! @brief Set the BPDLCD58 field to a new value. */
#define BW_LCD_WF58_BPDLCD58(x, v) (BME_BFI8(HW_LCD_WF58_ADDR(x), ((uint8_t)(v) << BP_LCD_WF58_BPDLCD58), BP_LCD_WF58_BPDLCD58, 1))
/*@}*/

/*!
 * @name Register LCD_WF58, field BPELCD58[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF58_BPELCD58 (4U)          /*!< Bit position for LCD_WF58_BPELCD58. */
#define BM_LCD_WF58_BPELCD58 (0x10U)       /*!< Bit mask for LCD_WF58_BPELCD58. */
#define BS_LCD_WF58_BPELCD58 (1U)          /*!< Bit field size in bits for LCD_WF58_BPELCD58. */

/*! @brief Read current value of the LCD_WF58_BPELCD58 field. */
#define BR_LCD_WF58_BPELCD58(x) (BME_UBFX8(HW_LCD_WF58_ADDR(x), BP_LCD_WF58_BPELCD58, BS_LCD_WF58_BPELCD58))

/*! @brief Format value for bitfield LCD_WF58_BPELCD58. */
#define BF_LCD_WF58_BPELCD58(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF58_BPELCD58) & BM_LCD_WF58_BPELCD58)

/*! @brief Set the BPELCD58 field to a new value. */
#define BW_LCD_WF58_BPELCD58(x, v) (BME_BFI8(HW_LCD_WF58_ADDR(x), ((uint8_t)(v) << BP_LCD_WF58_BPELCD58), BP_LCD_WF58_BPELCD58, 1))
/*@}*/

/*!
 * @name Register LCD_WF58, field BPFLCD58[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF58_BPFLCD58 (5U)          /*!< Bit position for LCD_WF58_BPFLCD58. */
#define BM_LCD_WF58_BPFLCD58 (0x20U)       /*!< Bit mask for LCD_WF58_BPFLCD58. */
#define BS_LCD_WF58_BPFLCD58 (1U)          /*!< Bit field size in bits for LCD_WF58_BPFLCD58. */

/*! @brief Read current value of the LCD_WF58_BPFLCD58 field. */
#define BR_LCD_WF58_BPFLCD58(x) (BME_UBFX8(HW_LCD_WF58_ADDR(x), BP_LCD_WF58_BPFLCD58, BS_LCD_WF58_BPFLCD58))

/*! @brief Format value for bitfield LCD_WF58_BPFLCD58. */
#define BF_LCD_WF58_BPFLCD58(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF58_BPFLCD58) & BM_LCD_WF58_BPFLCD58)

/*! @brief Set the BPFLCD58 field to a new value. */
#define BW_LCD_WF58_BPFLCD58(x, v) (BME_BFI8(HW_LCD_WF58_ADDR(x), ((uint8_t)(v) << BP_LCD_WF58_BPFLCD58), BP_LCD_WF58_BPFLCD58, 1))
/*@}*/

/*!
 * @name Register LCD_WF58, field BPGLCD58[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF58_BPGLCD58 (6U)          /*!< Bit position for LCD_WF58_BPGLCD58. */
#define BM_LCD_WF58_BPGLCD58 (0x40U)       /*!< Bit mask for LCD_WF58_BPGLCD58. */
#define BS_LCD_WF58_BPGLCD58 (1U)          /*!< Bit field size in bits for LCD_WF58_BPGLCD58. */

/*! @brief Read current value of the LCD_WF58_BPGLCD58 field. */
#define BR_LCD_WF58_BPGLCD58(x) (BME_UBFX8(HW_LCD_WF58_ADDR(x), BP_LCD_WF58_BPGLCD58, BS_LCD_WF58_BPGLCD58))

/*! @brief Format value for bitfield LCD_WF58_BPGLCD58. */
#define BF_LCD_WF58_BPGLCD58(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF58_BPGLCD58) & BM_LCD_WF58_BPGLCD58)

/*! @brief Set the BPGLCD58 field to a new value. */
#define BW_LCD_WF58_BPGLCD58(x, v) (BME_BFI8(HW_LCD_WF58_ADDR(x), ((uint8_t)(v) << BP_LCD_WF58_BPGLCD58), BP_LCD_WF58_BPGLCD58, 1))
/*@}*/

/*!
 * @name Register LCD_WF58, field BPHLCD58[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF58_BPHLCD58 (7U)          /*!< Bit position for LCD_WF58_BPHLCD58. */
#define BM_LCD_WF58_BPHLCD58 (0x80U)       /*!< Bit mask for LCD_WF58_BPHLCD58. */
#define BS_LCD_WF58_BPHLCD58 (1U)          /*!< Bit field size in bits for LCD_WF58_BPHLCD58. */

/*! @brief Read current value of the LCD_WF58_BPHLCD58 field. */
#define BR_LCD_WF58_BPHLCD58(x) (BME_UBFX8(HW_LCD_WF58_ADDR(x), BP_LCD_WF58_BPHLCD58, BS_LCD_WF58_BPHLCD58))

/*! @brief Format value for bitfield LCD_WF58_BPHLCD58. */
#define BF_LCD_WF58_BPHLCD58(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF58_BPHLCD58) & BM_LCD_WF58_BPHLCD58)

/*! @brief Set the BPHLCD58 field to a new value. */
#define BW_LCD_WF58_BPHLCD58(x, v) (BME_BFI8(HW_LCD_WF58_ADDR(x), ((uint8_t)(v) << BP_LCD_WF58_BPHLCD58), BP_LCD_WF58_BPHLCD58, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF59 - LCD Waveform Register 59.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF59 - LCD Waveform Register 59. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf59
{
    uint8_t U;
    struct _hw_lcd_wf59_bitfields
    {
        uint8_t BPALCD59 : 1;          /*!< [0]  */
        uint8_t BPBLCD59 : 1;          /*!< [1]  */
        uint8_t BPCLCD59 : 1;          /*!< [2]  */
        uint8_t BPDLCD59 : 1;          /*!< [3]  */
        uint8_t BPELCD59 : 1;          /*!< [4]  */
        uint8_t BPFLCD59 : 1;          /*!< [5]  */
        uint8_t BPGLCD59 : 1;          /*!< [6]  */
        uint8_t BPHLCD59 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf59_t;

/*!
 * @name Constants and macros for entire LCD_WF59 register
 */
/*@{*/
#define HW_LCD_WF59_ADDR(x)      ((x) + 0x5BU)

#define HW_LCD_WF59(x)           (*(__IO hw_lcd_wf59_t *) HW_LCD_WF59_ADDR(x))
#define HW_LCD_WF59_RD(x)        (HW_LCD_WF59(x).U)
#define HW_LCD_WF59_WR(x, v)     (HW_LCD_WF59(x).U = (v))
#define HW_LCD_WF59_SET(x, v)    (BME_OR8(HW_LCD_WF59_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF59_CLR(x, v)    (BME_AND8(HW_LCD_WF59_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF59_TOG(x, v)    (BME_XOR8(HW_LCD_WF59_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF59 bitfields
 */

/*!
 * @name Register LCD_WF59, field BPALCD59[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF59_BPALCD59 (0U)          /*!< Bit position for LCD_WF59_BPALCD59. */
#define BM_LCD_WF59_BPALCD59 (0x01U)       /*!< Bit mask for LCD_WF59_BPALCD59. */
#define BS_LCD_WF59_BPALCD59 (1U)          /*!< Bit field size in bits for LCD_WF59_BPALCD59. */

/*! @brief Read current value of the LCD_WF59_BPALCD59 field. */
#define BR_LCD_WF59_BPALCD59(x) (BME_UBFX8(HW_LCD_WF59_ADDR(x), BP_LCD_WF59_BPALCD59, BS_LCD_WF59_BPALCD59))

/*! @brief Format value for bitfield LCD_WF59_BPALCD59. */
#define BF_LCD_WF59_BPALCD59(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF59_BPALCD59) & BM_LCD_WF59_BPALCD59)

/*! @brief Set the BPALCD59 field to a new value. */
#define BW_LCD_WF59_BPALCD59(x, v) (BME_BFI8(HW_LCD_WF59_ADDR(x), ((uint8_t)(v) << BP_LCD_WF59_BPALCD59), BP_LCD_WF59_BPALCD59, 1))
/*@}*/

/*!
 * @name Register LCD_WF59, field BPBLCD59[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF59_BPBLCD59 (1U)          /*!< Bit position for LCD_WF59_BPBLCD59. */
#define BM_LCD_WF59_BPBLCD59 (0x02U)       /*!< Bit mask for LCD_WF59_BPBLCD59. */
#define BS_LCD_WF59_BPBLCD59 (1U)          /*!< Bit field size in bits for LCD_WF59_BPBLCD59. */

/*! @brief Read current value of the LCD_WF59_BPBLCD59 field. */
#define BR_LCD_WF59_BPBLCD59(x) (BME_UBFX8(HW_LCD_WF59_ADDR(x), BP_LCD_WF59_BPBLCD59, BS_LCD_WF59_BPBLCD59))

/*! @brief Format value for bitfield LCD_WF59_BPBLCD59. */
#define BF_LCD_WF59_BPBLCD59(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF59_BPBLCD59) & BM_LCD_WF59_BPBLCD59)

/*! @brief Set the BPBLCD59 field to a new value. */
#define BW_LCD_WF59_BPBLCD59(x, v) (BME_BFI8(HW_LCD_WF59_ADDR(x), ((uint8_t)(v) << BP_LCD_WF59_BPBLCD59), BP_LCD_WF59_BPBLCD59, 1))
/*@}*/

/*!
 * @name Register LCD_WF59, field BPCLCD59[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF59_BPCLCD59 (2U)          /*!< Bit position for LCD_WF59_BPCLCD59. */
#define BM_LCD_WF59_BPCLCD59 (0x04U)       /*!< Bit mask for LCD_WF59_BPCLCD59. */
#define BS_LCD_WF59_BPCLCD59 (1U)          /*!< Bit field size in bits for LCD_WF59_BPCLCD59. */

/*! @brief Read current value of the LCD_WF59_BPCLCD59 field. */
#define BR_LCD_WF59_BPCLCD59(x) (BME_UBFX8(HW_LCD_WF59_ADDR(x), BP_LCD_WF59_BPCLCD59, BS_LCD_WF59_BPCLCD59))

/*! @brief Format value for bitfield LCD_WF59_BPCLCD59. */
#define BF_LCD_WF59_BPCLCD59(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF59_BPCLCD59) & BM_LCD_WF59_BPCLCD59)

/*! @brief Set the BPCLCD59 field to a new value. */
#define BW_LCD_WF59_BPCLCD59(x, v) (BME_BFI8(HW_LCD_WF59_ADDR(x), ((uint8_t)(v) << BP_LCD_WF59_BPCLCD59), BP_LCD_WF59_BPCLCD59, 1))
/*@}*/

/*!
 * @name Register LCD_WF59, field BPDLCD59[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF59_BPDLCD59 (3U)          /*!< Bit position for LCD_WF59_BPDLCD59. */
#define BM_LCD_WF59_BPDLCD59 (0x08U)       /*!< Bit mask for LCD_WF59_BPDLCD59. */
#define BS_LCD_WF59_BPDLCD59 (1U)          /*!< Bit field size in bits for LCD_WF59_BPDLCD59. */

/*! @brief Read current value of the LCD_WF59_BPDLCD59 field. */
#define BR_LCD_WF59_BPDLCD59(x) (BME_UBFX8(HW_LCD_WF59_ADDR(x), BP_LCD_WF59_BPDLCD59, BS_LCD_WF59_BPDLCD59))

/*! @brief Format value for bitfield LCD_WF59_BPDLCD59. */
#define BF_LCD_WF59_BPDLCD59(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF59_BPDLCD59) & BM_LCD_WF59_BPDLCD59)

/*! @brief Set the BPDLCD59 field to a new value. */
#define BW_LCD_WF59_BPDLCD59(x, v) (BME_BFI8(HW_LCD_WF59_ADDR(x), ((uint8_t)(v) << BP_LCD_WF59_BPDLCD59), BP_LCD_WF59_BPDLCD59, 1))
/*@}*/

/*!
 * @name Register LCD_WF59, field BPELCD59[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF59_BPELCD59 (4U)          /*!< Bit position for LCD_WF59_BPELCD59. */
#define BM_LCD_WF59_BPELCD59 (0x10U)       /*!< Bit mask for LCD_WF59_BPELCD59. */
#define BS_LCD_WF59_BPELCD59 (1U)          /*!< Bit field size in bits for LCD_WF59_BPELCD59. */

/*! @brief Read current value of the LCD_WF59_BPELCD59 field. */
#define BR_LCD_WF59_BPELCD59(x) (BME_UBFX8(HW_LCD_WF59_ADDR(x), BP_LCD_WF59_BPELCD59, BS_LCD_WF59_BPELCD59))

/*! @brief Format value for bitfield LCD_WF59_BPELCD59. */
#define BF_LCD_WF59_BPELCD59(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF59_BPELCD59) & BM_LCD_WF59_BPELCD59)

/*! @brief Set the BPELCD59 field to a new value. */
#define BW_LCD_WF59_BPELCD59(x, v) (BME_BFI8(HW_LCD_WF59_ADDR(x), ((uint8_t)(v) << BP_LCD_WF59_BPELCD59), BP_LCD_WF59_BPELCD59, 1))
/*@}*/

/*!
 * @name Register LCD_WF59, field BPFLCD59[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF59_BPFLCD59 (5U)          /*!< Bit position for LCD_WF59_BPFLCD59. */
#define BM_LCD_WF59_BPFLCD59 (0x20U)       /*!< Bit mask for LCD_WF59_BPFLCD59. */
#define BS_LCD_WF59_BPFLCD59 (1U)          /*!< Bit field size in bits for LCD_WF59_BPFLCD59. */

/*! @brief Read current value of the LCD_WF59_BPFLCD59 field. */
#define BR_LCD_WF59_BPFLCD59(x) (BME_UBFX8(HW_LCD_WF59_ADDR(x), BP_LCD_WF59_BPFLCD59, BS_LCD_WF59_BPFLCD59))

/*! @brief Format value for bitfield LCD_WF59_BPFLCD59. */
#define BF_LCD_WF59_BPFLCD59(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF59_BPFLCD59) & BM_LCD_WF59_BPFLCD59)

/*! @brief Set the BPFLCD59 field to a new value. */
#define BW_LCD_WF59_BPFLCD59(x, v) (BME_BFI8(HW_LCD_WF59_ADDR(x), ((uint8_t)(v) << BP_LCD_WF59_BPFLCD59), BP_LCD_WF59_BPFLCD59, 1))
/*@}*/

/*!
 * @name Register LCD_WF59, field BPGLCD59[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF59_BPGLCD59 (6U)          /*!< Bit position for LCD_WF59_BPGLCD59. */
#define BM_LCD_WF59_BPGLCD59 (0x40U)       /*!< Bit mask for LCD_WF59_BPGLCD59. */
#define BS_LCD_WF59_BPGLCD59 (1U)          /*!< Bit field size in bits for LCD_WF59_BPGLCD59. */

/*! @brief Read current value of the LCD_WF59_BPGLCD59 field. */
#define BR_LCD_WF59_BPGLCD59(x) (BME_UBFX8(HW_LCD_WF59_ADDR(x), BP_LCD_WF59_BPGLCD59, BS_LCD_WF59_BPGLCD59))

/*! @brief Format value for bitfield LCD_WF59_BPGLCD59. */
#define BF_LCD_WF59_BPGLCD59(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF59_BPGLCD59) & BM_LCD_WF59_BPGLCD59)

/*! @brief Set the BPGLCD59 field to a new value. */
#define BW_LCD_WF59_BPGLCD59(x, v) (BME_BFI8(HW_LCD_WF59_ADDR(x), ((uint8_t)(v) << BP_LCD_WF59_BPGLCD59), BP_LCD_WF59_BPGLCD59, 1))
/*@}*/

/*!
 * @name Register LCD_WF59, field BPHLCD59[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF59_BPHLCD59 (7U)          /*!< Bit position for LCD_WF59_BPHLCD59. */
#define BM_LCD_WF59_BPHLCD59 (0x80U)       /*!< Bit mask for LCD_WF59_BPHLCD59. */
#define BS_LCD_WF59_BPHLCD59 (1U)          /*!< Bit field size in bits for LCD_WF59_BPHLCD59. */

/*! @brief Read current value of the LCD_WF59_BPHLCD59 field. */
#define BR_LCD_WF59_BPHLCD59(x) (BME_UBFX8(HW_LCD_WF59_ADDR(x), BP_LCD_WF59_BPHLCD59, BS_LCD_WF59_BPHLCD59))

/*! @brief Format value for bitfield LCD_WF59_BPHLCD59. */
#define BF_LCD_WF59_BPHLCD59(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF59_BPHLCD59) & BM_LCD_WF59_BPHLCD59)

/*! @brief Set the BPHLCD59 field to a new value. */
#define BW_LCD_WF59_BPHLCD59(x, v) (BME_BFI8(HW_LCD_WF59_ADDR(x), ((uint8_t)(v) << BP_LCD_WF59_BPHLCD59), BP_LCD_WF59_BPHLCD59, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF60 - LCD Waveform Register 60.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF60 - LCD Waveform Register 60. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf60
{
    uint8_t U;
    struct _hw_lcd_wf60_bitfields
    {
        uint8_t BPALCD60 : 1;          /*!< [0]  */
        uint8_t BPBLCD60 : 1;          /*!< [1]  */
        uint8_t BPCLCD60 : 1;          /*!< [2]  */
        uint8_t BPDLCD60 : 1;          /*!< [3]  */
        uint8_t BPELCD60 : 1;          /*!< [4]  */
        uint8_t BPFLCD60 : 1;          /*!< [5]  */
        uint8_t BPGLCD60 : 1;          /*!< [6]  */
        uint8_t BPHLCD60 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf60_t;

/*!
 * @name Constants and macros for entire LCD_WF60 register
 */
/*@{*/
#define HW_LCD_WF60_ADDR(x)      ((x) + 0x5CU)

#define HW_LCD_WF60(x)           (*(__IO hw_lcd_wf60_t *) HW_LCD_WF60_ADDR(x))
#define HW_LCD_WF60_RD(x)        (HW_LCD_WF60(x).U)
#define HW_LCD_WF60_WR(x, v)     (HW_LCD_WF60(x).U = (v))
#define HW_LCD_WF60_SET(x, v)    (BME_OR8(HW_LCD_WF60_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF60_CLR(x, v)    (BME_AND8(HW_LCD_WF60_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF60_TOG(x, v)    (BME_XOR8(HW_LCD_WF60_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF60 bitfields
 */

/*!
 * @name Register LCD_WF60, field BPALCD60[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF60_BPALCD60 (0U)          /*!< Bit position for LCD_WF60_BPALCD60. */
#define BM_LCD_WF60_BPALCD60 (0x01U)       /*!< Bit mask for LCD_WF60_BPALCD60. */
#define BS_LCD_WF60_BPALCD60 (1U)          /*!< Bit field size in bits for LCD_WF60_BPALCD60. */

/*! @brief Read current value of the LCD_WF60_BPALCD60 field. */
#define BR_LCD_WF60_BPALCD60(x) (BME_UBFX8(HW_LCD_WF60_ADDR(x), BP_LCD_WF60_BPALCD60, BS_LCD_WF60_BPALCD60))

/*! @brief Format value for bitfield LCD_WF60_BPALCD60. */
#define BF_LCD_WF60_BPALCD60(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF60_BPALCD60) & BM_LCD_WF60_BPALCD60)

/*! @brief Set the BPALCD60 field to a new value. */
#define BW_LCD_WF60_BPALCD60(x, v) (BME_BFI8(HW_LCD_WF60_ADDR(x), ((uint8_t)(v) << BP_LCD_WF60_BPALCD60), BP_LCD_WF60_BPALCD60, 1))
/*@}*/

/*!
 * @name Register LCD_WF60, field BPBLCD60[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF60_BPBLCD60 (1U)          /*!< Bit position for LCD_WF60_BPBLCD60. */
#define BM_LCD_WF60_BPBLCD60 (0x02U)       /*!< Bit mask for LCD_WF60_BPBLCD60. */
#define BS_LCD_WF60_BPBLCD60 (1U)          /*!< Bit field size in bits for LCD_WF60_BPBLCD60. */

/*! @brief Read current value of the LCD_WF60_BPBLCD60 field. */
#define BR_LCD_WF60_BPBLCD60(x) (BME_UBFX8(HW_LCD_WF60_ADDR(x), BP_LCD_WF60_BPBLCD60, BS_LCD_WF60_BPBLCD60))

/*! @brief Format value for bitfield LCD_WF60_BPBLCD60. */
#define BF_LCD_WF60_BPBLCD60(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF60_BPBLCD60) & BM_LCD_WF60_BPBLCD60)

/*! @brief Set the BPBLCD60 field to a new value. */
#define BW_LCD_WF60_BPBLCD60(x, v) (BME_BFI8(HW_LCD_WF60_ADDR(x), ((uint8_t)(v) << BP_LCD_WF60_BPBLCD60), BP_LCD_WF60_BPBLCD60, 1))
/*@}*/

/*!
 * @name Register LCD_WF60, field BPCLCD60[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF60_BPCLCD60 (2U)          /*!< Bit position for LCD_WF60_BPCLCD60. */
#define BM_LCD_WF60_BPCLCD60 (0x04U)       /*!< Bit mask for LCD_WF60_BPCLCD60. */
#define BS_LCD_WF60_BPCLCD60 (1U)          /*!< Bit field size in bits for LCD_WF60_BPCLCD60. */

/*! @brief Read current value of the LCD_WF60_BPCLCD60 field. */
#define BR_LCD_WF60_BPCLCD60(x) (BME_UBFX8(HW_LCD_WF60_ADDR(x), BP_LCD_WF60_BPCLCD60, BS_LCD_WF60_BPCLCD60))

/*! @brief Format value for bitfield LCD_WF60_BPCLCD60. */
#define BF_LCD_WF60_BPCLCD60(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF60_BPCLCD60) & BM_LCD_WF60_BPCLCD60)

/*! @brief Set the BPCLCD60 field to a new value. */
#define BW_LCD_WF60_BPCLCD60(x, v) (BME_BFI8(HW_LCD_WF60_ADDR(x), ((uint8_t)(v) << BP_LCD_WF60_BPCLCD60), BP_LCD_WF60_BPCLCD60, 1))
/*@}*/

/*!
 * @name Register LCD_WF60, field BPDLCD60[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF60_BPDLCD60 (3U)          /*!< Bit position for LCD_WF60_BPDLCD60. */
#define BM_LCD_WF60_BPDLCD60 (0x08U)       /*!< Bit mask for LCD_WF60_BPDLCD60. */
#define BS_LCD_WF60_BPDLCD60 (1U)          /*!< Bit field size in bits for LCD_WF60_BPDLCD60. */

/*! @brief Read current value of the LCD_WF60_BPDLCD60 field. */
#define BR_LCD_WF60_BPDLCD60(x) (BME_UBFX8(HW_LCD_WF60_ADDR(x), BP_LCD_WF60_BPDLCD60, BS_LCD_WF60_BPDLCD60))

/*! @brief Format value for bitfield LCD_WF60_BPDLCD60. */
#define BF_LCD_WF60_BPDLCD60(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF60_BPDLCD60) & BM_LCD_WF60_BPDLCD60)

/*! @brief Set the BPDLCD60 field to a new value. */
#define BW_LCD_WF60_BPDLCD60(x, v) (BME_BFI8(HW_LCD_WF60_ADDR(x), ((uint8_t)(v) << BP_LCD_WF60_BPDLCD60), BP_LCD_WF60_BPDLCD60, 1))
/*@}*/

/*!
 * @name Register LCD_WF60, field BPELCD60[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF60_BPELCD60 (4U)          /*!< Bit position for LCD_WF60_BPELCD60. */
#define BM_LCD_WF60_BPELCD60 (0x10U)       /*!< Bit mask for LCD_WF60_BPELCD60. */
#define BS_LCD_WF60_BPELCD60 (1U)          /*!< Bit field size in bits for LCD_WF60_BPELCD60. */

/*! @brief Read current value of the LCD_WF60_BPELCD60 field. */
#define BR_LCD_WF60_BPELCD60(x) (BME_UBFX8(HW_LCD_WF60_ADDR(x), BP_LCD_WF60_BPELCD60, BS_LCD_WF60_BPELCD60))

/*! @brief Format value for bitfield LCD_WF60_BPELCD60. */
#define BF_LCD_WF60_BPELCD60(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF60_BPELCD60) & BM_LCD_WF60_BPELCD60)

/*! @brief Set the BPELCD60 field to a new value. */
#define BW_LCD_WF60_BPELCD60(x, v) (BME_BFI8(HW_LCD_WF60_ADDR(x), ((uint8_t)(v) << BP_LCD_WF60_BPELCD60), BP_LCD_WF60_BPELCD60, 1))
/*@}*/

/*!
 * @name Register LCD_WF60, field BPFLCD60[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF60_BPFLCD60 (5U)          /*!< Bit position for LCD_WF60_BPFLCD60. */
#define BM_LCD_WF60_BPFLCD60 (0x20U)       /*!< Bit mask for LCD_WF60_BPFLCD60. */
#define BS_LCD_WF60_BPFLCD60 (1U)          /*!< Bit field size in bits for LCD_WF60_BPFLCD60. */

/*! @brief Read current value of the LCD_WF60_BPFLCD60 field. */
#define BR_LCD_WF60_BPFLCD60(x) (BME_UBFX8(HW_LCD_WF60_ADDR(x), BP_LCD_WF60_BPFLCD60, BS_LCD_WF60_BPFLCD60))

/*! @brief Format value for bitfield LCD_WF60_BPFLCD60. */
#define BF_LCD_WF60_BPFLCD60(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF60_BPFLCD60) & BM_LCD_WF60_BPFLCD60)

/*! @brief Set the BPFLCD60 field to a new value. */
#define BW_LCD_WF60_BPFLCD60(x, v) (BME_BFI8(HW_LCD_WF60_ADDR(x), ((uint8_t)(v) << BP_LCD_WF60_BPFLCD60), BP_LCD_WF60_BPFLCD60, 1))
/*@}*/

/*!
 * @name Register LCD_WF60, field BPGLCD60[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF60_BPGLCD60 (6U)          /*!< Bit position for LCD_WF60_BPGLCD60. */
#define BM_LCD_WF60_BPGLCD60 (0x40U)       /*!< Bit mask for LCD_WF60_BPGLCD60. */
#define BS_LCD_WF60_BPGLCD60 (1U)          /*!< Bit field size in bits for LCD_WF60_BPGLCD60. */

/*! @brief Read current value of the LCD_WF60_BPGLCD60 field. */
#define BR_LCD_WF60_BPGLCD60(x) (BME_UBFX8(HW_LCD_WF60_ADDR(x), BP_LCD_WF60_BPGLCD60, BS_LCD_WF60_BPGLCD60))

/*! @brief Format value for bitfield LCD_WF60_BPGLCD60. */
#define BF_LCD_WF60_BPGLCD60(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF60_BPGLCD60) & BM_LCD_WF60_BPGLCD60)

/*! @brief Set the BPGLCD60 field to a new value. */
#define BW_LCD_WF60_BPGLCD60(x, v) (BME_BFI8(HW_LCD_WF60_ADDR(x), ((uint8_t)(v) << BP_LCD_WF60_BPGLCD60), BP_LCD_WF60_BPGLCD60, 1))
/*@}*/

/*!
 * @name Register LCD_WF60, field BPHLCD60[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF60_BPHLCD60 (7U)          /*!< Bit position for LCD_WF60_BPHLCD60. */
#define BM_LCD_WF60_BPHLCD60 (0x80U)       /*!< Bit mask for LCD_WF60_BPHLCD60. */
#define BS_LCD_WF60_BPHLCD60 (1U)          /*!< Bit field size in bits for LCD_WF60_BPHLCD60. */

/*! @brief Read current value of the LCD_WF60_BPHLCD60 field. */
#define BR_LCD_WF60_BPHLCD60(x) (BME_UBFX8(HW_LCD_WF60_ADDR(x), BP_LCD_WF60_BPHLCD60, BS_LCD_WF60_BPHLCD60))

/*! @brief Format value for bitfield LCD_WF60_BPHLCD60. */
#define BF_LCD_WF60_BPHLCD60(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF60_BPHLCD60) & BM_LCD_WF60_BPHLCD60)

/*! @brief Set the BPHLCD60 field to a new value. */
#define BW_LCD_WF60_BPHLCD60(x, v) (BME_BFI8(HW_LCD_WF60_ADDR(x), ((uint8_t)(v) << BP_LCD_WF60_BPHLCD60), BP_LCD_WF60_BPHLCD60, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF61 - LCD Waveform Register 61.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF61 - LCD Waveform Register 61. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf61
{
    uint8_t U;
    struct _hw_lcd_wf61_bitfields
    {
        uint8_t BPALCD61 : 1;          /*!< [0]  */
        uint8_t BPBLCD61 : 1;          /*!< [1]  */
        uint8_t BPCLCD61 : 1;          /*!< [2]  */
        uint8_t BPDLCD61 : 1;          /*!< [3]  */
        uint8_t BPELCD61 : 1;          /*!< [4]  */
        uint8_t BPFLCD61 : 1;          /*!< [5]  */
        uint8_t BPGLCD61 : 1;          /*!< [6]  */
        uint8_t BPHLCD61 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf61_t;

/*!
 * @name Constants and macros for entire LCD_WF61 register
 */
/*@{*/
#define HW_LCD_WF61_ADDR(x)      ((x) + 0x5DU)

#define HW_LCD_WF61(x)           (*(__IO hw_lcd_wf61_t *) HW_LCD_WF61_ADDR(x))
#define HW_LCD_WF61_RD(x)        (HW_LCD_WF61(x).U)
#define HW_LCD_WF61_WR(x, v)     (HW_LCD_WF61(x).U = (v))
#define HW_LCD_WF61_SET(x, v)    (BME_OR8(HW_LCD_WF61_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF61_CLR(x, v)    (BME_AND8(HW_LCD_WF61_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF61_TOG(x, v)    (BME_XOR8(HW_LCD_WF61_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF61 bitfields
 */

/*!
 * @name Register LCD_WF61, field BPALCD61[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF61_BPALCD61 (0U)          /*!< Bit position for LCD_WF61_BPALCD61. */
#define BM_LCD_WF61_BPALCD61 (0x01U)       /*!< Bit mask for LCD_WF61_BPALCD61. */
#define BS_LCD_WF61_BPALCD61 (1U)          /*!< Bit field size in bits for LCD_WF61_BPALCD61. */

/*! @brief Read current value of the LCD_WF61_BPALCD61 field. */
#define BR_LCD_WF61_BPALCD61(x) (BME_UBFX8(HW_LCD_WF61_ADDR(x), BP_LCD_WF61_BPALCD61, BS_LCD_WF61_BPALCD61))

/*! @brief Format value for bitfield LCD_WF61_BPALCD61. */
#define BF_LCD_WF61_BPALCD61(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF61_BPALCD61) & BM_LCD_WF61_BPALCD61)

/*! @brief Set the BPALCD61 field to a new value. */
#define BW_LCD_WF61_BPALCD61(x, v) (BME_BFI8(HW_LCD_WF61_ADDR(x), ((uint8_t)(v) << BP_LCD_WF61_BPALCD61), BP_LCD_WF61_BPALCD61, 1))
/*@}*/

/*!
 * @name Register LCD_WF61, field BPBLCD61[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF61_BPBLCD61 (1U)          /*!< Bit position for LCD_WF61_BPBLCD61. */
#define BM_LCD_WF61_BPBLCD61 (0x02U)       /*!< Bit mask for LCD_WF61_BPBLCD61. */
#define BS_LCD_WF61_BPBLCD61 (1U)          /*!< Bit field size in bits for LCD_WF61_BPBLCD61. */

/*! @brief Read current value of the LCD_WF61_BPBLCD61 field. */
#define BR_LCD_WF61_BPBLCD61(x) (BME_UBFX8(HW_LCD_WF61_ADDR(x), BP_LCD_WF61_BPBLCD61, BS_LCD_WF61_BPBLCD61))

/*! @brief Format value for bitfield LCD_WF61_BPBLCD61. */
#define BF_LCD_WF61_BPBLCD61(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF61_BPBLCD61) & BM_LCD_WF61_BPBLCD61)

/*! @brief Set the BPBLCD61 field to a new value. */
#define BW_LCD_WF61_BPBLCD61(x, v) (BME_BFI8(HW_LCD_WF61_ADDR(x), ((uint8_t)(v) << BP_LCD_WF61_BPBLCD61), BP_LCD_WF61_BPBLCD61, 1))
/*@}*/

/*!
 * @name Register LCD_WF61, field BPCLCD61[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF61_BPCLCD61 (2U)          /*!< Bit position for LCD_WF61_BPCLCD61. */
#define BM_LCD_WF61_BPCLCD61 (0x04U)       /*!< Bit mask for LCD_WF61_BPCLCD61. */
#define BS_LCD_WF61_BPCLCD61 (1U)          /*!< Bit field size in bits for LCD_WF61_BPCLCD61. */

/*! @brief Read current value of the LCD_WF61_BPCLCD61 field. */
#define BR_LCD_WF61_BPCLCD61(x) (BME_UBFX8(HW_LCD_WF61_ADDR(x), BP_LCD_WF61_BPCLCD61, BS_LCD_WF61_BPCLCD61))

/*! @brief Format value for bitfield LCD_WF61_BPCLCD61. */
#define BF_LCD_WF61_BPCLCD61(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF61_BPCLCD61) & BM_LCD_WF61_BPCLCD61)

/*! @brief Set the BPCLCD61 field to a new value. */
#define BW_LCD_WF61_BPCLCD61(x, v) (BME_BFI8(HW_LCD_WF61_ADDR(x), ((uint8_t)(v) << BP_LCD_WF61_BPCLCD61), BP_LCD_WF61_BPCLCD61, 1))
/*@}*/

/*!
 * @name Register LCD_WF61, field BPDLCD61[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF61_BPDLCD61 (3U)          /*!< Bit position for LCD_WF61_BPDLCD61. */
#define BM_LCD_WF61_BPDLCD61 (0x08U)       /*!< Bit mask for LCD_WF61_BPDLCD61. */
#define BS_LCD_WF61_BPDLCD61 (1U)          /*!< Bit field size in bits for LCD_WF61_BPDLCD61. */

/*! @brief Read current value of the LCD_WF61_BPDLCD61 field. */
#define BR_LCD_WF61_BPDLCD61(x) (BME_UBFX8(HW_LCD_WF61_ADDR(x), BP_LCD_WF61_BPDLCD61, BS_LCD_WF61_BPDLCD61))

/*! @brief Format value for bitfield LCD_WF61_BPDLCD61. */
#define BF_LCD_WF61_BPDLCD61(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF61_BPDLCD61) & BM_LCD_WF61_BPDLCD61)

/*! @brief Set the BPDLCD61 field to a new value. */
#define BW_LCD_WF61_BPDLCD61(x, v) (BME_BFI8(HW_LCD_WF61_ADDR(x), ((uint8_t)(v) << BP_LCD_WF61_BPDLCD61), BP_LCD_WF61_BPDLCD61, 1))
/*@}*/

/*!
 * @name Register LCD_WF61, field BPELCD61[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF61_BPELCD61 (4U)          /*!< Bit position for LCD_WF61_BPELCD61. */
#define BM_LCD_WF61_BPELCD61 (0x10U)       /*!< Bit mask for LCD_WF61_BPELCD61. */
#define BS_LCD_WF61_BPELCD61 (1U)          /*!< Bit field size in bits for LCD_WF61_BPELCD61. */

/*! @brief Read current value of the LCD_WF61_BPELCD61 field. */
#define BR_LCD_WF61_BPELCD61(x) (BME_UBFX8(HW_LCD_WF61_ADDR(x), BP_LCD_WF61_BPELCD61, BS_LCD_WF61_BPELCD61))

/*! @brief Format value for bitfield LCD_WF61_BPELCD61. */
#define BF_LCD_WF61_BPELCD61(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF61_BPELCD61) & BM_LCD_WF61_BPELCD61)

/*! @brief Set the BPELCD61 field to a new value. */
#define BW_LCD_WF61_BPELCD61(x, v) (BME_BFI8(HW_LCD_WF61_ADDR(x), ((uint8_t)(v) << BP_LCD_WF61_BPELCD61), BP_LCD_WF61_BPELCD61, 1))
/*@}*/

/*!
 * @name Register LCD_WF61, field BPFLCD61[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF61_BPFLCD61 (5U)          /*!< Bit position for LCD_WF61_BPFLCD61. */
#define BM_LCD_WF61_BPFLCD61 (0x20U)       /*!< Bit mask for LCD_WF61_BPFLCD61. */
#define BS_LCD_WF61_BPFLCD61 (1U)          /*!< Bit field size in bits for LCD_WF61_BPFLCD61. */

/*! @brief Read current value of the LCD_WF61_BPFLCD61 field. */
#define BR_LCD_WF61_BPFLCD61(x) (BME_UBFX8(HW_LCD_WF61_ADDR(x), BP_LCD_WF61_BPFLCD61, BS_LCD_WF61_BPFLCD61))

/*! @brief Format value for bitfield LCD_WF61_BPFLCD61. */
#define BF_LCD_WF61_BPFLCD61(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF61_BPFLCD61) & BM_LCD_WF61_BPFLCD61)

/*! @brief Set the BPFLCD61 field to a new value. */
#define BW_LCD_WF61_BPFLCD61(x, v) (BME_BFI8(HW_LCD_WF61_ADDR(x), ((uint8_t)(v) << BP_LCD_WF61_BPFLCD61), BP_LCD_WF61_BPFLCD61, 1))
/*@}*/

/*!
 * @name Register LCD_WF61, field BPGLCD61[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF61_BPGLCD61 (6U)          /*!< Bit position for LCD_WF61_BPGLCD61. */
#define BM_LCD_WF61_BPGLCD61 (0x40U)       /*!< Bit mask for LCD_WF61_BPGLCD61. */
#define BS_LCD_WF61_BPGLCD61 (1U)          /*!< Bit field size in bits for LCD_WF61_BPGLCD61. */

/*! @brief Read current value of the LCD_WF61_BPGLCD61 field. */
#define BR_LCD_WF61_BPGLCD61(x) (BME_UBFX8(HW_LCD_WF61_ADDR(x), BP_LCD_WF61_BPGLCD61, BS_LCD_WF61_BPGLCD61))

/*! @brief Format value for bitfield LCD_WF61_BPGLCD61. */
#define BF_LCD_WF61_BPGLCD61(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF61_BPGLCD61) & BM_LCD_WF61_BPGLCD61)

/*! @brief Set the BPGLCD61 field to a new value. */
#define BW_LCD_WF61_BPGLCD61(x, v) (BME_BFI8(HW_LCD_WF61_ADDR(x), ((uint8_t)(v) << BP_LCD_WF61_BPGLCD61), BP_LCD_WF61_BPGLCD61, 1))
/*@}*/

/*!
 * @name Register LCD_WF61, field BPHLCD61[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF61_BPHLCD61 (7U)          /*!< Bit position for LCD_WF61_BPHLCD61. */
#define BM_LCD_WF61_BPHLCD61 (0x80U)       /*!< Bit mask for LCD_WF61_BPHLCD61. */
#define BS_LCD_WF61_BPHLCD61 (1U)          /*!< Bit field size in bits for LCD_WF61_BPHLCD61. */

/*! @brief Read current value of the LCD_WF61_BPHLCD61 field. */
#define BR_LCD_WF61_BPHLCD61(x) (BME_UBFX8(HW_LCD_WF61_ADDR(x), BP_LCD_WF61_BPHLCD61, BS_LCD_WF61_BPHLCD61))

/*! @brief Format value for bitfield LCD_WF61_BPHLCD61. */
#define BF_LCD_WF61_BPHLCD61(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF61_BPHLCD61) & BM_LCD_WF61_BPHLCD61)

/*! @brief Set the BPHLCD61 field to a new value. */
#define BW_LCD_WF61_BPHLCD61(x, v) (BME_BFI8(HW_LCD_WF61_ADDR(x), ((uint8_t)(v) << BP_LCD_WF61_BPHLCD61), BP_LCD_WF61_BPHLCD61, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF62 - LCD Waveform Register 62.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF62 - LCD Waveform Register 62. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf62
{
    uint8_t U;
    struct _hw_lcd_wf62_bitfields
    {
        uint8_t BPALCD62 : 1;          /*!< [0]  */
        uint8_t BPBLCD62 : 1;          /*!< [1]  */
        uint8_t BPCLCD62 : 1;          /*!< [2]  */
        uint8_t BPDLCD62 : 1;          /*!< [3]  */
        uint8_t BPELCD62 : 1;          /*!< [4]  */
        uint8_t BPFLCD62 : 1;          /*!< [5]  */
        uint8_t BPGLCD62 : 1;          /*!< [6]  */
        uint8_t BPHLCD62 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf62_t;

/*!
 * @name Constants and macros for entire LCD_WF62 register
 */
/*@{*/
#define HW_LCD_WF62_ADDR(x)      ((x) + 0x5EU)

#define HW_LCD_WF62(x)           (*(__IO hw_lcd_wf62_t *) HW_LCD_WF62_ADDR(x))
#define HW_LCD_WF62_RD(x)        (HW_LCD_WF62(x).U)
#define HW_LCD_WF62_WR(x, v)     (HW_LCD_WF62(x).U = (v))
#define HW_LCD_WF62_SET(x, v)    (BME_OR8(HW_LCD_WF62_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF62_CLR(x, v)    (BME_AND8(HW_LCD_WF62_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF62_TOG(x, v)    (BME_XOR8(HW_LCD_WF62_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF62 bitfields
 */

/*!
 * @name Register LCD_WF62, field BPALCD62[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF62_BPALCD62 (0U)          /*!< Bit position for LCD_WF62_BPALCD62. */
#define BM_LCD_WF62_BPALCD62 (0x01U)       /*!< Bit mask for LCD_WF62_BPALCD62. */
#define BS_LCD_WF62_BPALCD62 (1U)          /*!< Bit field size in bits for LCD_WF62_BPALCD62. */

/*! @brief Read current value of the LCD_WF62_BPALCD62 field. */
#define BR_LCD_WF62_BPALCD62(x) (BME_UBFX8(HW_LCD_WF62_ADDR(x), BP_LCD_WF62_BPALCD62, BS_LCD_WF62_BPALCD62))

/*! @brief Format value for bitfield LCD_WF62_BPALCD62. */
#define BF_LCD_WF62_BPALCD62(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF62_BPALCD62) & BM_LCD_WF62_BPALCD62)

/*! @brief Set the BPALCD62 field to a new value. */
#define BW_LCD_WF62_BPALCD62(x, v) (BME_BFI8(HW_LCD_WF62_ADDR(x), ((uint8_t)(v) << BP_LCD_WF62_BPALCD62), BP_LCD_WF62_BPALCD62, 1))
/*@}*/

/*!
 * @name Register LCD_WF62, field BPBLCD62[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF62_BPBLCD62 (1U)          /*!< Bit position for LCD_WF62_BPBLCD62. */
#define BM_LCD_WF62_BPBLCD62 (0x02U)       /*!< Bit mask for LCD_WF62_BPBLCD62. */
#define BS_LCD_WF62_BPBLCD62 (1U)          /*!< Bit field size in bits for LCD_WF62_BPBLCD62. */

/*! @brief Read current value of the LCD_WF62_BPBLCD62 field. */
#define BR_LCD_WF62_BPBLCD62(x) (BME_UBFX8(HW_LCD_WF62_ADDR(x), BP_LCD_WF62_BPBLCD62, BS_LCD_WF62_BPBLCD62))

/*! @brief Format value for bitfield LCD_WF62_BPBLCD62. */
#define BF_LCD_WF62_BPBLCD62(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF62_BPBLCD62) & BM_LCD_WF62_BPBLCD62)

/*! @brief Set the BPBLCD62 field to a new value. */
#define BW_LCD_WF62_BPBLCD62(x, v) (BME_BFI8(HW_LCD_WF62_ADDR(x), ((uint8_t)(v) << BP_LCD_WF62_BPBLCD62), BP_LCD_WF62_BPBLCD62, 1))
/*@}*/

/*!
 * @name Register LCD_WF62, field BPCLCD62[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF62_BPCLCD62 (2U)          /*!< Bit position for LCD_WF62_BPCLCD62. */
#define BM_LCD_WF62_BPCLCD62 (0x04U)       /*!< Bit mask for LCD_WF62_BPCLCD62. */
#define BS_LCD_WF62_BPCLCD62 (1U)          /*!< Bit field size in bits for LCD_WF62_BPCLCD62. */

/*! @brief Read current value of the LCD_WF62_BPCLCD62 field. */
#define BR_LCD_WF62_BPCLCD62(x) (BME_UBFX8(HW_LCD_WF62_ADDR(x), BP_LCD_WF62_BPCLCD62, BS_LCD_WF62_BPCLCD62))

/*! @brief Format value for bitfield LCD_WF62_BPCLCD62. */
#define BF_LCD_WF62_BPCLCD62(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF62_BPCLCD62) & BM_LCD_WF62_BPCLCD62)

/*! @brief Set the BPCLCD62 field to a new value. */
#define BW_LCD_WF62_BPCLCD62(x, v) (BME_BFI8(HW_LCD_WF62_ADDR(x), ((uint8_t)(v) << BP_LCD_WF62_BPCLCD62), BP_LCD_WF62_BPCLCD62, 1))
/*@}*/

/*!
 * @name Register LCD_WF62, field BPDLCD62[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF62_BPDLCD62 (3U)          /*!< Bit position for LCD_WF62_BPDLCD62. */
#define BM_LCD_WF62_BPDLCD62 (0x08U)       /*!< Bit mask for LCD_WF62_BPDLCD62. */
#define BS_LCD_WF62_BPDLCD62 (1U)          /*!< Bit field size in bits for LCD_WF62_BPDLCD62. */

/*! @brief Read current value of the LCD_WF62_BPDLCD62 field. */
#define BR_LCD_WF62_BPDLCD62(x) (BME_UBFX8(HW_LCD_WF62_ADDR(x), BP_LCD_WF62_BPDLCD62, BS_LCD_WF62_BPDLCD62))

/*! @brief Format value for bitfield LCD_WF62_BPDLCD62. */
#define BF_LCD_WF62_BPDLCD62(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF62_BPDLCD62) & BM_LCD_WF62_BPDLCD62)

/*! @brief Set the BPDLCD62 field to a new value. */
#define BW_LCD_WF62_BPDLCD62(x, v) (BME_BFI8(HW_LCD_WF62_ADDR(x), ((uint8_t)(v) << BP_LCD_WF62_BPDLCD62), BP_LCD_WF62_BPDLCD62, 1))
/*@}*/

/*!
 * @name Register LCD_WF62, field BPELCD62[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF62_BPELCD62 (4U)          /*!< Bit position for LCD_WF62_BPELCD62. */
#define BM_LCD_WF62_BPELCD62 (0x10U)       /*!< Bit mask for LCD_WF62_BPELCD62. */
#define BS_LCD_WF62_BPELCD62 (1U)          /*!< Bit field size in bits for LCD_WF62_BPELCD62. */

/*! @brief Read current value of the LCD_WF62_BPELCD62 field. */
#define BR_LCD_WF62_BPELCD62(x) (BME_UBFX8(HW_LCD_WF62_ADDR(x), BP_LCD_WF62_BPELCD62, BS_LCD_WF62_BPELCD62))

/*! @brief Format value for bitfield LCD_WF62_BPELCD62. */
#define BF_LCD_WF62_BPELCD62(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF62_BPELCD62) & BM_LCD_WF62_BPELCD62)

/*! @brief Set the BPELCD62 field to a new value. */
#define BW_LCD_WF62_BPELCD62(x, v) (BME_BFI8(HW_LCD_WF62_ADDR(x), ((uint8_t)(v) << BP_LCD_WF62_BPELCD62), BP_LCD_WF62_BPELCD62, 1))
/*@}*/

/*!
 * @name Register LCD_WF62, field BPFLCD62[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF62_BPFLCD62 (5U)          /*!< Bit position for LCD_WF62_BPFLCD62. */
#define BM_LCD_WF62_BPFLCD62 (0x20U)       /*!< Bit mask for LCD_WF62_BPFLCD62. */
#define BS_LCD_WF62_BPFLCD62 (1U)          /*!< Bit field size in bits for LCD_WF62_BPFLCD62. */

/*! @brief Read current value of the LCD_WF62_BPFLCD62 field. */
#define BR_LCD_WF62_BPFLCD62(x) (BME_UBFX8(HW_LCD_WF62_ADDR(x), BP_LCD_WF62_BPFLCD62, BS_LCD_WF62_BPFLCD62))

/*! @brief Format value for bitfield LCD_WF62_BPFLCD62. */
#define BF_LCD_WF62_BPFLCD62(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF62_BPFLCD62) & BM_LCD_WF62_BPFLCD62)

/*! @brief Set the BPFLCD62 field to a new value. */
#define BW_LCD_WF62_BPFLCD62(x, v) (BME_BFI8(HW_LCD_WF62_ADDR(x), ((uint8_t)(v) << BP_LCD_WF62_BPFLCD62), BP_LCD_WF62_BPFLCD62, 1))
/*@}*/

/*!
 * @name Register LCD_WF62, field BPGLCD62[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF62_BPGLCD62 (6U)          /*!< Bit position for LCD_WF62_BPGLCD62. */
#define BM_LCD_WF62_BPGLCD62 (0x40U)       /*!< Bit mask for LCD_WF62_BPGLCD62. */
#define BS_LCD_WF62_BPGLCD62 (1U)          /*!< Bit field size in bits for LCD_WF62_BPGLCD62. */

/*! @brief Read current value of the LCD_WF62_BPGLCD62 field. */
#define BR_LCD_WF62_BPGLCD62(x) (BME_UBFX8(HW_LCD_WF62_ADDR(x), BP_LCD_WF62_BPGLCD62, BS_LCD_WF62_BPGLCD62))

/*! @brief Format value for bitfield LCD_WF62_BPGLCD62. */
#define BF_LCD_WF62_BPGLCD62(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF62_BPGLCD62) & BM_LCD_WF62_BPGLCD62)

/*! @brief Set the BPGLCD62 field to a new value. */
#define BW_LCD_WF62_BPGLCD62(x, v) (BME_BFI8(HW_LCD_WF62_ADDR(x), ((uint8_t)(v) << BP_LCD_WF62_BPGLCD62), BP_LCD_WF62_BPGLCD62, 1))
/*@}*/

/*!
 * @name Register LCD_WF62, field BPHLCD62[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF62_BPHLCD62 (7U)          /*!< Bit position for LCD_WF62_BPHLCD62. */
#define BM_LCD_WF62_BPHLCD62 (0x80U)       /*!< Bit mask for LCD_WF62_BPHLCD62. */
#define BS_LCD_WF62_BPHLCD62 (1U)          /*!< Bit field size in bits for LCD_WF62_BPHLCD62. */

/*! @brief Read current value of the LCD_WF62_BPHLCD62 field. */
#define BR_LCD_WF62_BPHLCD62(x) (BME_UBFX8(HW_LCD_WF62_ADDR(x), BP_LCD_WF62_BPHLCD62, BS_LCD_WF62_BPHLCD62))

/*! @brief Format value for bitfield LCD_WF62_BPHLCD62. */
#define BF_LCD_WF62_BPHLCD62(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF62_BPHLCD62) & BM_LCD_WF62_BPHLCD62)

/*! @brief Set the BPHLCD62 field to a new value. */
#define BW_LCD_WF62_BPHLCD62(x, v) (BME_BFI8(HW_LCD_WF62_ADDR(x), ((uint8_t)(v) << BP_LCD_WF62_BPHLCD62), BP_LCD_WF62_BPHLCD62, 1))
/*@}*/
/*******************************************************************************
 * HW_LCD_WF63 - LCD Waveform Register 63.
 ******************************************************************************/

/*!
 * @brief HW_LCD_WF63 - LCD Waveform Register 63. (RW)
 *
 * Reset value: 0x00U
 */
typedef union _hw_lcd_wf63
{
    uint8_t U;
    struct _hw_lcd_wf63_bitfields
    {
        uint8_t BPALCD63 : 1;          /*!< [0]  */
        uint8_t BPBLCD63 : 1;          /*!< [1]  */
        uint8_t BPCLCD63 : 1;          /*!< [2]  */
        uint8_t BPDLCD63 : 1;          /*!< [3]  */
        uint8_t BPELCD63 : 1;          /*!< [4]  */
        uint8_t BPFLCD63 : 1;          /*!< [5]  */
        uint8_t BPGLCD63 : 1;          /*!< [6]  */
        uint8_t BPHLCD63 : 1;          /*!< [7]  */
    } B;
} hw_lcd_wf63_t;

/*!
 * @name Constants and macros for entire LCD_WF63 register
 */
/*@{*/
#define HW_LCD_WF63_ADDR(x)      ((x) + 0x5FU)

#define HW_LCD_WF63(x)           (*(__IO hw_lcd_wf63_t *) HW_LCD_WF63_ADDR(x))
#define HW_LCD_WF63_RD(x)        (HW_LCD_WF63(x).U)
#define HW_LCD_WF63_WR(x, v)     (HW_LCD_WF63(x).U = (v))
#define HW_LCD_WF63_SET(x, v)    (BME_OR8(HW_LCD_WF63_ADDR(x), (uint8_t)(v)))
#define HW_LCD_WF63_CLR(x, v)    (BME_AND8(HW_LCD_WF63_ADDR(x), (uint8_t)(~(v))))
#define HW_LCD_WF63_TOG(x, v)    (BME_XOR8(HW_LCD_WF63_ADDR(x), (uint8_t)(v)))
/*@}*/

/*
 * Constants & macros for individual LCD_WF63 bitfields
 */

/*!
 * @name Register LCD_WF63, field BPALCD63[0] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase A
 * - 1 - LCD segment on or LCD backplane active for phase A
 */
/*@{*/
#define BP_LCD_WF63_BPALCD63 (0U)          /*!< Bit position for LCD_WF63_BPALCD63. */
#define BM_LCD_WF63_BPALCD63 (0x01U)       /*!< Bit mask for LCD_WF63_BPALCD63. */
#define BS_LCD_WF63_BPALCD63 (1U)          /*!< Bit field size in bits for LCD_WF63_BPALCD63. */

/*! @brief Read current value of the LCD_WF63_BPALCD63 field. */
#define BR_LCD_WF63_BPALCD63(x) (BME_UBFX8(HW_LCD_WF63_ADDR(x), BP_LCD_WF63_BPALCD63, BS_LCD_WF63_BPALCD63))

/*! @brief Format value for bitfield LCD_WF63_BPALCD63. */
#define BF_LCD_WF63_BPALCD63(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF63_BPALCD63) & BM_LCD_WF63_BPALCD63)

/*! @brief Set the BPALCD63 field to a new value. */
#define BW_LCD_WF63_BPALCD63(x, v) (BME_BFI8(HW_LCD_WF63_ADDR(x), ((uint8_t)(v) << BP_LCD_WF63_BPALCD63), BP_LCD_WF63_BPALCD63, 1))
/*@}*/

/*!
 * @name Register LCD_WF63, field BPBLCD63[1] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase B
 * - 1 - LCD segment on or LCD backplane active for phase B
 */
/*@{*/
#define BP_LCD_WF63_BPBLCD63 (1U)          /*!< Bit position for LCD_WF63_BPBLCD63. */
#define BM_LCD_WF63_BPBLCD63 (0x02U)       /*!< Bit mask for LCD_WF63_BPBLCD63. */
#define BS_LCD_WF63_BPBLCD63 (1U)          /*!< Bit field size in bits for LCD_WF63_BPBLCD63. */

/*! @brief Read current value of the LCD_WF63_BPBLCD63 field. */
#define BR_LCD_WF63_BPBLCD63(x) (BME_UBFX8(HW_LCD_WF63_ADDR(x), BP_LCD_WF63_BPBLCD63, BS_LCD_WF63_BPBLCD63))

/*! @brief Format value for bitfield LCD_WF63_BPBLCD63. */
#define BF_LCD_WF63_BPBLCD63(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF63_BPBLCD63) & BM_LCD_WF63_BPBLCD63)

/*! @brief Set the BPBLCD63 field to a new value. */
#define BW_LCD_WF63_BPBLCD63(x, v) (BME_BFI8(HW_LCD_WF63_ADDR(x), ((uint8_t)(v) << BP_LCD_WF63_BPBLCD63), BP_LCD_WF63_BPBLCD63, 1))
/*@}*/

/*!
 * @name Register LCD_WF63, field BPCLCD63[2] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase C
 * - 1 - LCD segment on or LCD backplane active for phase C
 */
/*@{*/
#define BP_LCD_WF63_BPCLCD63 (2U)          /*!< Bit position for LCD_WF63_BPCLCD63. */
#define BM_LCD_WF63_BPCLCD63 (0x04U)       /*!< Bit mask for LCD_WF63_BPCLCD63. */
#define BS_LCD_WF63_BPCLCD63 (1U)          /*!< Bit field size in bits for LCD_WF63_BPCLCD63. */

/*! @brief Read current value of the LCD_WF63_BPCLCD63 field. */
#define BR_LCD_WF63_BPCLCD63(x) (BME_UBFX8(HW_LCD_WF63_ADDR(x), BP_LCD_WF63_BPCLCD63, BS_LCD_WF63_BPCLCD63))

/*! @brief Format value for bitfield LCD_WF63_BPCLCD63. */
#define BF_LCD_WF63_BPCLCD63(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF63_BPCLCD63) & BM_LCD_WF63_BPCLCD63)

/*! @brief Set the BPCLCD63 field to a new value. */
#define BW_LCD_WF63_BPCLCD63(x, v) (BME_BFI8(HW_LCD_WF63_ADDR(x), ((uint8_t)(v) << BP_LCD_WF63_BPCLCD63), BP_LCD_WF63_BPCLCD63, 1))
/*@}*/

/*!
 * @name Register LCD_WF63, field BPDLCD63[3] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase D
 * - 1 - LCD segment on or LCD backplane active for phase D
 */
/*@{*/
#define BP_LCD_WF63_BPDLCD63 (3U)          /*!< Bit position for LCD_WF63_BPDLCD63. */
#define BM_LCD_WF63_BPDLCD63 (0x08U)       /*!< Bit mask for LCD_WF63_BPDLCD63. */
#define BS_LCD_WF63_BPDLCD63 (1U)          /*!< Bit field size in bits for LCD_WF63_BPDLCD63. */

/*! @brief Read current value of the LCD_WF63_BPDLCD63 field. */
#define BR_LCD_WF63_BPDLCD63(x) (BME_UBFX8(HW_LCD_WF63_ADDR(x), BP_LCD_WF63_BPDLCD63, BS_LCD_WF63_BPDLCD63))

/*! @brief Format value for bitfield LCD_WF63_BPDLCD63. */
#define BF_LCD_WF63_BPDLCD63(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF63_BPDLCD63) & BM_LCD_WF63_BPDLCD63)

/*! @brief Set the BPDLCD63 field to a new value. */
#define BW_LCD_WF63_BPDLCD63(x, v) (BME_BFI8(HW_LCD_WF63_ADDR(x), ((uint8_t)(v) << BP_LCD_WF63_BPDLCD63), BP_LCD_WF63_BPDLCD63, 1))
/*@}*/

/*!
 * @name Register LCD_WF63, field BPELCD63[4] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase E
 * - 1 - LCD segment on or LCD backplane active for phase E
 */
/*@{*/
#define BP_LCD_WF63_BPELCD63 (4U)          /*!< Bit position for LCD_WF63_BPELCD63. */
#define BM_LCD_WF63_BPELCD63 (0x10U)       /*!< Bit mask for LCD_WF63_BPELCD63. */
#define BS_LCD_WF63_BPELCD63 (1U)          /*!< Bit field size in bits for LCD_WF63_BPELCD63. */

/*! @brief Read current value of the LCD_WF63_BPELCD63 field. */
#define BR_LCD_WF63_BPELCD63(x) (BME_UBFX8(HW_LCD_WF63_ADDR(x), BP_LCD_WF63_BPELCD63, BS_LCD_WF63_BPELCD63))

/*! @brief Format value for bitfield LCD_WF63_BPELCD63. */
#define BF_LCD_WF63_BPELCD63(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF63_BPELCD63) & BM_LCD_WF63_BPELCD63)

/*! @brief Set the BPELCD63 field to a new value. */
#define BW_LCD_WF63_BPELCD63(x, v) (BME_BFI8(HW_LCD_WF63_ADDR(x), ((uint8_t)(v) << BP_LCD_WF63_BPELCD63), BP_LCD_WF63_BPELCD63, 1))
/*@}*/

/*!
 * @name Register LCD_WF63, field BPFLCD63[5] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase F
 * - 1 - LCD segment on or LCD backplane active for phase F
 */
/*@{*/
#define BP_LCD_WF63_BPFLCD63 (5U)          /*!< Bit position for LCD_WF63_BPFLCD63. */
#define BM_LCD_WF63_BPFLCD63 (0x20U)       /*!< Bit mask for LCD_WF63_BPFLCD63. */
#define BS_LCD_WF63_BPFLCD63 (1U)          /*!< Bit field size in bits for LCD_WF63_BPFLCD63. */

/*! @brief Read current value of the LCD_WF63_BPFLCD63 field. */
#define BR_LCD_WF63_BPFLCD63(x) (BME_UBFX8(HW_LCD_WF63_ADDR(x), BP_LCD_WF63_BPFLCD63, BS_LCD_WF63_BPFLCD63))

/*! @brief Format value for bitfield LCD_WF63_BPFLCD63. */
#define BF_LCD_WF63_BPFLCD63(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF63_BPFLCD63) & BM_LCD_WF63_BPFLCD63)

/*! @brief Set the BPFLCD63 field to a new value. */
#define BW_LCD_WF63_BPFLCD63(x, v) (BME_BFI8(HW_LCD_WF63_ADDR(x), ((uint8_t)(v) << BP_LCD_WF63_BPFLCD63), BP_LCD_WF63_BPFLCD63, 1))
/*@}*/

/*!
 * @name Register LCD_WF63, field BPGLCD63[6] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase G
 * - 1 - LCD segment on or LCD backplane active for phase G
 */
/*@{*/
#define BP_LCD_WF63_BPGLCD63 (6U)          /*!< Bit position for LCD_WF63_BPGLCD63. */
#define BM_LCD_WF63_BPGLCD63 (0x40U)       /*!< Bit mask for LCD_WF63_BPGLCD63. */
#define BS_LCD_WF63_BPGLCD63 (1U)          /*!< Bit field size in bits for LCD_WF63_BPGLCD63. */

/*! @brief Read current value of the LCD_WF63_BPGLCD63 field. */
#define BR_LCD_WF63_BPGLCD63(x) (BME_UBFX8(HW_LCD_WF63_ADDR(x), BP_LCD_WF63_BPGLCD63, BS_LCD_WF63_BPGLCD63))

/*! @brief Format value for bitfield LCD_WF63_BPGLCD63. */
#define BF_LCD_WF63_BPGLCD63(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF63_BPGLCD63) & BM_LCD_WF63_BPGLCD63)

/*! @brief Set the BPGLCD63 field to a new value. */
#define BW_LCD_WF63_BPGLCD63(x, v) (BME_BFI8(HW_LCD_WF63_ADDR(x), ((uint8_t)(v) << BP_LCD_WF63_BPGLCD63), BP_LCD_WF63_BPGLCD63, 1))
/*@}*/

/*!
 * @name Register LCD_WF63, field BPHLCD63[7] (RW)
 *
 * Values:
 * - 0 - LCD segment off or LCD backplane inactive for phase H
 * - 1 - LCD segment on or LCD backplane active for phase H
 */
/*@{*/
#define BP_LCD_WF63_BPHLCD63 (7U)          /*!< Bit position for LCD_WF63_BPHLCD63. */
#define BM_LCD_WF63_BPHLCD63 (0x80U)       /*!< Bit mask for LCD_WF63_BPHLCD63. */
#define BS_LCD_WF63_BPHLCD63 (1U)          /*!< Bit field size in bits for LCD_WF63_BPHLCD63. */

/*! @brief Read current value of the LCD_WF63_BPHLCD63 field. */
#define BR_LCD_WF63_BPHLCD63(x) (BME_UBFX8(HW_LCD_WF63_ADDR(x), BP_LCD_WF63_BPHLCD63, BS_LCD_WF63_BPHLCD63))

/*! @brief Format value for bitfield LCD_WF63_BPHLCD63. */
#define BF_LCD_WF63_BPHLCD63(v) ((uint8_t)((uint8_t)(v) << BP_LCD_WF63_BPHLCD63) & BM_LCD_WF63_BPHLCD63)

/*! @brief Set the BPHLCD63 field to a new value. */
#define BW_LCD_WF63_BPHLCD63(x, v) (BME_BFI8(HW_LCD_WF63_ADDR(x), ((uint8_t)(v) << BP_LCD_WF63_BPHLCD63), BP_LCD_WF63_BPHLCD63, 1))
/*@}*/

/*
** Start of section using anonymous unions
*/

#if defined(__ARMCC_VERSION)
  #pragma push
  #pragma anon_unions
#elif defined(__CWCC__)
  #pragma push
  #pragma cpp_extensions on
#elif defined(__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma language=extended
#else
  #error Not supported compiler type
#endif

/*******************************************************************************
 * hw_lcd_t - module struct
 ******************************************************************************/
/*!
 * @brief All LCD module registers.
 */
#pragma pack(1)
typedef struct _hw_lcd
{
    __IO hw_lcd_gcr_t GCR;                 /*!< [0x0] LCD General Control Register */
    __IO hw_lcd_ar_t AR;                   /*!< [0x4] LCD Auxiliary Register */
    __IO hw_lcd_fdcr_t FDCR;               /*!< [0x8] LCD Fault Detect Control Register */
    __IO hw_lcd_fdsr_t FDSR;               /*!< [0xC] LCD Fault Detect Status Register */
    __IO hw_lcd_penl_t PENL;               /*!< [0x10] LCD Pin Enable register */
    __IO hw_lcd_penh_t PENH;               /*!< [0x14] LCD Pin Enable register */
    __IO hw_lcd_bpenl_t BPENL;             /*!< [0x18] LCD Back Plane Enable register */
    __IO hw_lcd_bpenh_t BPENH;             /*!< [0x1C] LCD Back Plane Enable register */
    union {
        struct {
            __IO hw_lcd_wf3to0_t WF3TO0;   /*!< [0x20] LCD Waveform register */
            __IO hw_lcd_wf7to4_t WF7TO4;   /*!< [0x24] LCD Waveform register */
            __IO hw_lcd_wf11to8_t WF11TO8; /*!< [0x28] LCD Waveform register */
            __IO hw_lcd_wf15to12_t WF15TO12; /*!< [0x2C] LCD Waveform register */
            __IO hw_lcd_wf19to16_t WF19TO16; /*!< [0x30] LCD Waveform register */
            __IO hw_lcd_wf23to20_t WF23TO20; /*!< [0x34] LCD Waveform register */
            __IO hw_lcd_wf27to24_t WF27TO24; /*!< [0x38] LCD Waveform register */
            __IO hw_lcd_wf31to28_t WF31TO28; /*!< [0x3C] LCD Waveform register */
            __IO hw_lcd_wf35to32_t WF35TO32; /*!< [0x40] LCD Waveform register */
            __IO hw_lcd_wf39to36_t WF39TO36; /*!< [0x44] LCD Waveform register */
            __IO hw_lcd_wf43to40_t WF43TO40; /*!< [0x48] LCD Waveform register */
            __IO hw_lcd_wf47to44_t WF47TO44; /*!< [0x4C] LCD Waveform register */
            __IO hw_lcd_wf51to48_t WF51TO48; /*!< [0x50] LCD Waveform register */
            __IO hw_lcd_wf55to52_t WF55TO52; /*!< [0x54] LCD Waveform register */
            __IO hw_lcd_wf59to56_t WF59TO56; /*!< [0x58] LCD Waveform register */
            __IO hw_lcd_wf63to60_t WF63TO60; /*!< [0x5C] LCD Waveform register */
        } WFACCESS32BIT;
        struct {
            __IO hw_lcd_wf0_t WF0;         /*!< [0x20] LCD Waveform Register 0. */
            __IO hw_lcd_wf1_t WF1;         /*!< [0x21] LCD Waveform Register 1. */
            __IO hw_lcd_wf2_t WF2;         /*!< [0x22] LCD Waveform Register 2. */
            __IO hw_lcd_wf3_t WF3;         /*!< [0x23] LCD Waveform Register 3. */
            __IO hw_lcd_wf4_t WF4;         /*!< [0x24] LCD Waveform Register 4. */
            __IO hw_lcd_wf5_t WF5;         /*!< [0x25] LCD Waveform Register 5. */
            __IO hw_lcd_wf6_t WF6;         /*!< [0x26] LCD Waveform Register 6. */
            __IO hw_lcd_wf7_t WF7;         /*!< [0x27] LCD Waveform Register 7. */
            __IO hw_lcd_wf8_t WF8;         /*!< [0x28] LCD Waveform Register 8. */
            __IO hw_lcd_wf9_t WF9;         /*!< [0x29] LCD Waveform Register 9. */
            __IO hw_lcd_wf10_t WF10;       /*!< [0x2A] LCD Waveform Register 10. */
            __IO hw_lcd_wf11_t WF11;       /*!< [0x2B] LCD Waveform Register 11. */
            __IO hw_lcd_wf12_t WF12;       /*!< [0x2C] LCD Waveform Register 12. */
            __IO hw_lcd_wf13_t WF13;       /*!< [0x2D] LCD Waveform Register 13. */
            __IO hw_lcd_wf14_t WF14;       /*!< [0x2E] LCD Waveform Register 14. */
            __IO hw_lcd_wf15_t WF15;       /*!< [0x2F] LCD Waveform Register 15. */
            __IO hw_lcd_wf16_t WF16;       /*!< [0x30] LCD Waveform Register 16. */
            __IO hw_lcd_wf17_t WF17;       /*!< [0x31] LCD Waveform Register 17. */
            __IO hw_lcd_wf18_t WF18;       /*!< [0x32] LCD Waveform Register 18. */
            __IO hw_lcd_wf19_t WF19;       /*!< [0x33] LCD Waveform Register 19. */
            __IO hw_lcd_wf20_t WF20;       /*!< [0x34] LCD Waveform Register 20. */
            __IO hw_lcd_wf21_t WF21;       /*!< [0x35] LCD Waveform Register 21. */
            __IO hw_lcd_wf22_t WF22;       /*!< [0x36] LCD Waveform Register 22. */
            __IO hw_lcd_wf23_t WF23;       /*!< [0x37] LCD Waveform Register 23. */
            __IO hw_lcd_wf24_t WF24;       /*!< [0x38] LCD Waveform Register 24. */
            __IO hw_lcd_wf25_t WF25;       /*!< [0x39] LCD Waveform Register 25. */
            __IO hw_lcd_wf26_t WF26;       /*!< [0x3A] LCD Waveform Register 26. */
            __IO hw_lcd_wf27_t WF27;       /*!< [0x3B] LCD Waveform Register 27. */
            __IO hw_lcd_wf28_t WF28;       /*!< [0x3C] LCD Waveform Register 28. */
            __IO hw_lcd_wf29_t WF29;       /*!< [0x3D] LCD Waveform Register 29. */
            __IO hw_lcd_wf30_t WF30;       /*!< [0x3E] LCD Waveform Register 30. */
            __IO hw_lcd_wf31_t WF31;       /*!< [0x3F] LCD Waveform Register 31. */
            __IO hw_lcd_wf32_t WF32;       /*!< [0x40] LCD Waveform Register 32. */
            __IO hw_lcd_wf33_t WF33;       /*!< [0x41] LCD Waveform Register 33. */
            __IO hw_lcd_wf34_t WF34;       /*!< [0x42] LCD Waveform Register 34. */
            __IO hw_lcd_wf35_t WF35;       /*!< [0x43] LCD Waveform Register 35. */
            __IO hw_lcd_wf36_t WF36;       /*!< [0x44] LCD Waveform Register 36. */
            __IO hw_lcd_wf37_t WF37;       /*!< [0x45] LCD Waveform Register 37. */
            __IO hw_lcd_wf38_t WF38;       /*!< [0x46] LCD Waveform Register 38. */
            __IO hw_lcd_wf39_t WF39;       /*!< [0x47] LCD Waveform Register 39. */
            __IO hw_lcd_wf40_t WF40;       /*!< [0x48] LCD Waveform Register 40. */
            __IO hw_lcd_wf41_t WF41;       /*!< [0x49] LCD Waveform Register 41. */
            __IO hw_lcd_wf42_t WF42;       /*!< [0x4A] LCD Waveform Register 42. */
            __IO hw_lcd_wf43_t WF43;       /*!< [0x4B] LCD Waveform Register 43. */
            __IO hw_lcd_wf44_t WF44;       /*!< [0x4C] LCD Waveform Register 44. */
            __IO hw_lcd_wf45_t WF45;       /*!< [0x4D] LCD Waveform Register 45. */
            __IO hw_lcd_wf46_t WF46;       /*!< [0x4E] LCD Waveform Register 46. */
            __IO hw_lcd_wf47_t WF47;       /*!< [0x4F] LCD Waveform Register 47. */
            __IO hw_lcd_wf48_t WF48;       /*!< [0x50] LCD Waveform Register 48. */
            __IO hw_lcd_wf49_t WF49;       /*!< [0x51] LCD Waveform Register 49. */
            __IO hw_lcd_wf50_t WF50;       /*!< [0x52] LCD Waveform Register 50. */
            __IO hw_lcd_wf51_t WF51;       /*!< [0x53] LCD Waveform Register 51. */
            __IO hw_lcd_wf52_t WF52;       /*!< [0x54] LCD Waveform Register 52. */
            __IO hw_lcd_wf53_t WF53;       /*!< [0x55] LCD Waveform Register 53. */
            __IO hw_lcd_wf54_t WF54;       /*!< [0x56] LCD Waveform Register 54. */
            __IO hw_lcd_wf55_t WF55;       /*!< [0x57] LCD Waveform Register 55. */
            __IO hw_lcd_wf56_t WF56;       /*!< [0x58] LCD Waveform Register 56. */
            __IO hw_lcd_wf57_t WF57;       /*!< [0x59] LCD Waveform Register 57. */
            __IO hw_lcd_wf58_t WF58;       /*!< [0x5A] LCD Waveform Register 58. */
            __IO hw_lcd_wf59_t WF59;       /*!< [0x5B] LCD Waveform Register 59. */
            __IO hw_lcd_wf60_t WF60;       /*!< [0x5C] LCD Waveform Register 60. */
            __IO hw_lcd_wf61_t WF61;       /*!< [0x5D] LCD Waveform Register 61. */
            __IO hw_lcd_wf62_t WF62;       /*!< [0x5E] LCD Waveform Register 62. */
            __IO hw_lcd_wf63_t WF63;       /*!< [0x5F] LCD Waveform Register 63. */
        } WFACCESS8BIT;
    };
} hw_lcd_t;
#pragma pack()

/*! @brief Macro to access all LCD registers. */
/*! @param x LCD module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 *     use the '&' operator, like <code>&HW_LCD(LCD_BASE)</code>. */
#define HW_LCD(x)      (*(hw_lcd_t *)(x))

/*
** End of section using anonymous unions
*/

#if defined(__ARMCC_VERSION)
  #pragma pop
#elif defined(__CWCC__)
  #pragma pop
#elif defined(__GNUC__)
  /* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma language=default
#else
  #error Not supported compiler type
#endif

#endif /* __HW_LCD_REGISTERS_H__ */
/* v33/140401/2.1.0 */
/* EOF */
